Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2836433	1			T1	1		T2	1		T3	1
all_values[1]	2836433	1			T1	1		T2	1		T3	1
all_values[2]	2836433	1			T1	1		T2	1		T3	1
all_values[3]	2836433	1			T1	1		T2	1		T3	1
all_values[4]	2836433	1			T1	1		T2	1		T3	1
all_values[5]	2836433	1			T1	1		T2	1		T3	1
all_values[6]	2836433	1			T1	1		T2	1		T3	1
all_values[7]	2836433	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22535852

1

T1

8

T2

8

T3

8

auto[1]

155612

1

T6

107

T12

84

T29

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22667308

1

T1

8

T2

8

T3

8

auto[1]

24156

1

T5

6

T6

72

T10

109

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2809387	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	12497	1			T6	3		T10	71		T12	54
all_values[0]	auto[1]	auto[0]	14200	1			T6	7		T12	13		T29	4
all_values[0]	auto[1]	auto[1]	349	1			T6	4		T12	1		T29	1
all_values[1]	auto[0]	auto[0]	2809477	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	6202	1			T6	5		T10	30		T15	44
all_values[1]	auto[1]	auto[0]	20479	1			T6	7		T12	14		T29	2
all_values[1]	auto[1]	auto[1]	275	1			T6	8		T29	2		T152	2
all_values[2]	auto[0]	auto[0]	2809134	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2374	1			T6	2		T10	8		T12	2
all_values[2]	auto[1]	auto[0]	24716	1			T6	6		T12	4		T29	4
all_values[2]	auto[1]	auto[1]	209	1			T6	8		T12	2		T29	1
all_values[3]	auto[0]	auto[0]	2819986	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	199	1			T6	5		T12	4		T29	3
all_values[3]	auto[1]	auto[0]	16017	1			T6	7		T12	5		T29	1
all_values[3]	auto[1]	auto[1]	231	1			T6	6		T12	2		T57	2
all_values[4]	auto[0]	auto[0]	2821326	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	214	1			T6	3		T29	2		T57	6
all_values[4]	auto[1]	auto[0]	14674	1			T6	5		T12	15		T29	2
all_values[4]	auto[1]	auto[1]	219	1			T6	4		T29	2		T57	2
all_values[5]	auto[0]	auto[0]	2822545	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	351	1			T5	6		T6	2		T12	5
all_values[5]	auto[1]	auto[0]	13353	1			T6	13		T12	5		T57	3
all_values[5]	auto[1]	auto[1]	184	1			T6	3		T12	2		T29	1
all_values[6]	auto[0]	auto[0]	2816775	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	227	1			T6	5		T29	1		T57	4
all_values[6]	auto[1]	auto[0]	19212	1			T6	7		T12	12		T29	2
all_values[6]	auto[1]	auto[1]	219	1			T6	6		T12	3		T29	3
all_values[7]	auto[0]	auto[0]	2804956	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	202	1			T6	4		T57	2		T152	3
all_values[7]	auto[1]	auto[0]	31071	1			T6	12		T12	4		T57	5437
all_values[7]	auto[1]	auto[1]	204	1			T6	4		T12	2		T57	2