Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	28757	1			T1	2		T3	6		T7	2
auto[SpiFlashAddrCfg]	6787	1			T1	2		T4	3		T10	60
auto[SpiFlashAddr3b]	7872	1			T1	10		T3	4		T4	1
auto[SpiFlashAddr4b]	6667	1			T1	8		T4	2		T10	53

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27522

1

T3

10

T4

6

T7

2

auto[1]

22561

1

T1

22

T10

146

T12

115

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27181

1

T1

16

T3

4

T4

3

auto[1]

22902

1

T1

6

T3

6

T4

3

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	32697	1			T1	6		T3	10		T7	2
values[1]	992	1			T10	8		T12	6		T15	5
values[2]	1319	1			T10	14		T12	12		T13	1
values[3]	1342	1			T1	4		T10	14		T12	16
values[4]	1268	1			T4	1		T10	7		T12	14
values[5]	1290	1			T10	14		T12	3		T13	1
values[6]	1315	1			T10	9		T12	10		T13	3
values[7]	1352	1			T1	2		T4	2		T10	11
values[8]	8508	1			T1	10		T4	3		T10	68

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26911

1

T1

22

T3

10

T7

2

auto[1]

23172

1

T4

6

T12

163

T13

146

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

48272

1

T1

20

T3

10

T4

6

write

1811

1

T1

2

T10

7

T12

8

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

17361

1

T1

14

T4

3

T10

137

valids[0x1]

32722

1

T1

8

T3

10

T4

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1357	1			T3	2		T10	13		T12	10
internal_process_ops[0x5a]	1436	1			T3	4		T10	12		T12	12
internal_process_ops[0x05]	16569	1			T10	40		T12	36		T13	70
internal_process_ops[0x35]	1402	1			T1	2		T3	2		T7	2
internal_process_ops[0x15]	1354	1			T3	2		T10	14		T12	7
internal_process_ops[0x03]	959	1			T4	2		T10	9		T12	4
internal_process_ops[0x0b]	884	1			T4	1		T10	12		T12	6
internal_process_ops[0x3b]	975	1			T1	6		T4	3		T10	12
internal_process_ops[0x6b]	936	1			T10	7		T12	11		T13	1
internal_process_ops[0xbb]	961	1			T10	11		T12	7		T15	1
internal_process_ops[0xeb]	997	1			T1	4		T10	10		T12	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49263

1

T1

20

T3

10

T4

6

auto[1]

820

1

T1

2

T10

3

T12

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48381

1

T1

22

T3

10

T4

6

auto[1]

1702

1

T10

10

T12

10

T13

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8640

1

T3

6

T7

2

T10

78

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5743

1

T1

2

T10

56

T12

9

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1990

1

T10

26

T12

6

T17

16

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1727

1

T1

2

T10

33

T12

11

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2274

1

T3

4

T10

32

T12

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1920

1

T1

8

T10

29

T12

22

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1924

1

T10

26

T12

8

T17

22

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1797

1

T1

8

T10

25

T12

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

72

1

T10

2

T12

1

T29

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

46

1

T25

1

T29

3

T30

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

46

1

T17

2

T29

3

T154

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

51

1

T10

2

T17

3

T32

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

64

1

T17

1

T155

2

T153

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

44

1

T29

1

T156

2

T154

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

74

1

T10

1

T29

2

T30

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

54

1

T32

1

T33

1

T154

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

71

1

T17

2

T156

5

T153

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

55

1

T25

2

T30

1

T34

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

45

1

T30

1

T154

3

T157

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

47

1

T1

2

T17

1

T29

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

73

1

T10

1

T25

3

T29

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

52

1

T10

1

T25

1

T29

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

49

1

T17

1

T29

2

T30

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

53

1

T29

3

T31

2

T158

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7601

1

T12

55

T13

12

T15

68

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6350

1

T12

26

T13

81

T15

26

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1278

1

T4

3

T12

16

T13

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1297

1

T12

6

T13

3

T15

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1580

1

T4

1

T12

7

T13

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1644

1

T12

21

T13

12

T15

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1307

1

T4

2

T12

14

T13

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1200

1

T12

11

T13

6

T15

16

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

63

1

T13

4

T27

2

T18

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

37

1

T18

3

T159

1

T41

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

48

1

T75

2

T73

3

T159

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

60

1

T15

1

T16

1

T75

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

54

1

T75

2

T41

1

T45

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

65

1

T15

1

T26

2

T144

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

87

1

T12

1

T15

2

T18

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

53

1

T12

1

T15

3

T27

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

73

1

T27

2

T160

1

T73

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

55

1

T26

1

T18

1

T29

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

54

1

T12

2

T15

1

T16

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

54

1

T13

2

T16

1

T26

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

54

1

T12

2

T15

2

T26

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

50

1

T18

2

T56

1

T75

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

64

1

T13

1

T27

1

T56

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

44

1

T12

1

T13

1

T26

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3763	1			T1	2		T10	58		T12	11
auto[0]	values[0]	valids[0x1]	12988	1			T1	4		T3	10		T7	2
auto[0]	values[1]	valids[0x1]	534	1			T10	8		T12	5		T17	3
auto[0]	values[2]	valids[0x0]	538	1			T10	6		T12	5		T17	10
auto[0]	values[2]	valids[0x1]	247	1			T10	8		T17	4		T25	1
auto[0]	values[3]	valids[0x0]	498	1			T1	4		T10	9		T12	5
auto[0]	values[3]	valids[0x1]	292	1			T10	5		T12	1		T17	5
auto[0]	values[4]	valids[0x0]	461	1			T10	5		T12	5		T17	2
auto[0]	values[4]	valids[0x1]	269	1			T10	2		T12	3		T17	1
auto[0]	values[5]	valids[0x0]	505	1			T10	6		T12	1		T17	2
auto[0]	values[5]	valids[0x1]	286	1			T10	8		T12	1		T17	4
auto[0]	values[6]	valids[0x0]	512	1			T10	8		T17	7		T97	4
auto[0]	values[6]	valids[0x1]	265	1			T10	1		T17	3		T25	2
auto[0]	values[7]	valids[0x0]	521	1			T1	2		T10	4		T17	1
auto[0]	values[7]	valids[0x1]	321	1			T10	7		T17	2		T25	1
auto[0]	values[8]	valids[0x0]	3181	1			T1	6		T10	41		T12	13
auto[0]	values[8]	valids[0x1]	1730	1			T1	4		T10	27		T12	10
auto[1]	values[0]	valids[0x0]	3506	1			T12	40		T13	13		T15	43
auto[1]	values[0]	valids[0x1]	12440	1			T12	62		T13	97		T15	84
auto[1]	values[1]	valids[0x1]	458	1			T12	1		T15	5		T16	2
auto[1]	values[2]	valids[0x0]	280	1			T12	4		T15	2		T16	5
auto[1]	values[2]	valids[0x1]	254	1			T12	3		T13	1		T16	1
auto[1]	values[3]	valids[0x0]	300	1			T12	4		T13	2		T15	4
auto[1]	values[3]	valids[0x1]	252	1			T12	6		T13	2		T15	2
auto[1]	values[4]	valids[0x0]	318	1			T12	6		T13	4		T16	4
auto[1]	values[4]	valids[0x1]	220	1			T4	1		T15	3		T16	1
auto[1]	values[5]	valids[0x0]	279	1			T12	1		T16	1		T26	2
auto[1]	values[5]	valids[0x1]	220	1			T13	1		T15	4		T16	2
auto[1]	values[6]	valids[0x0]	309	1			T12	4		T13	1		T15	4
auto[1]	values[6]	valids[0x1]	229	1			T12	6		T13	2		T15	2
auto[1]	values[7]	valids[0x0]	295	1			T12	2		T15	2		T16	1
auto[1]	values[7]	valids[0x1]	215	1			T4	2		T12	1		T13	1
auto[1]	values[8]	valids[0x0]	2095	1			T4	3		T12	18		T13	16
auto[1]	values[8]	valids[0x1]	1502	1			T12	5		T13	6		T15	11