Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3147779

1

T1

1

T2

1

T3

222

auto[1]

15189

1

T10

32

T12

27

T13

66

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

942638

1

T1

1

T2

1

T3

222

auto[1]

2220330

1

T7

10

T10

26659

T12

10273

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	560640	1			T1	1		T2	1		T3	101
auto[524288:1048575]	344613	1			T3	52		T7	3		T10	4035
auto[1048576:1572863]	403043	1			T7	2711		T10	5695		T12	2802
auto[1572864:2097151]	376615	1			T4	1538		T7	665		T10	1718
auto[2097152:2621439]	328337	1			T3	65		T4	546		T7	335
auto[2621440:3145727]	383352	1			T4	1542		T7	333		T10	1
auto[3145728:3670015]	401517	1			T3	4		T4	336		T7	2742
auto[3670016:4194303]	364851	1			T7	8		T10	3022		T12	294

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2238805

1

T1

1

T2

1

T3

14

auto[1]

924163

1

T3

208

T4

3952

T7

7117

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2736645

1

T1

1

T2

1

T3

222

auto[1]

426323

1

T10

2415

T12

1029

T15

668

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	190892	1			T1	1		T2	1		T3	101
auto[0]	auto[0]	auto[0:524287]	auto[1]	323684	1			T10	5959		T12	1874		T13	3628
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	108152	1			T3	52		T7	3		T10	11
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	178360	1			T10	4017		T12	2161		T15	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	101734	1			T7	2711		T10	14		T12	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	242916	1			T10	5669		T12	2789		T13	64
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	118190	1			T4	1538		T7	656		T12	10
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	206270	1			T7	9		T12	1084		T15	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	106216	1			T3	65		T4	546		T7	335
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	175483	1			T10	2742		T12	1		T13	257
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	110480	1			T4	1542		T7	333		T10	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	222651	1			T12	1031		T13	1		T15	197
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	96551	1			T3	4		T4	336		T7	2742
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	233943	1			T10	3018		T13	512		T15	513
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	102101	1			T7	7		T10	5		T12	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	206585	1			T7	1		T10	2840		T12	292
auto[0]	auto[1]	auto[0:524287]	auto[0]	522	1			T10	1		T16	1		T17	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	43483	1			T10	512		T16	519		T27	756
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	600	1			T16	4		T25	1		T29	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	55930	1			T12	512		T16	1		T29	128
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	271	1			T12	3		T15	2		T26	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	56295	1			T15	660		T26	7		T18	393
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	359	1			T10	8		T12	1		T15	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	49680	1			T10	1704		T12	512		T16	1998
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	559	1			T10	1		T15	1		T17	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	44081	1			T17	3117		T25	1694		T26	276
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1370	1			T15	1		T17	2		T27	8
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	47181	1			T15	1		T17	512		T27	646
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1615	1			T10	4		T12	1		T17	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	67274	1			T10	1		T17	513		T25	638
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1321	1			T15	2		T17	1		T27	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	53030	1			T10	175		T17	4514		T27	4
auto[1]	auto[0]	auto[0:524287]	auto[0]	195	1			T13	2		T26	2		T27	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	1527	1			T13	43		T26	38		T27	14
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	162	1			T10	1		T25	2		T27	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1197	1			T10	6		T25	15		T27	37
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	172	1			T10	5		T12	2		T13	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1303	1			T10	7		T12	4		T13	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	181	1			T12	1		T15	1		T17	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1571	1			T12	1		T17	1		T27	25
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	163	1			T12	1		T16	2		T17	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1340	1			T12	3		T16	2		T17	45
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	156	1			T12	6		T13	1		T15	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1236	1			T12	9		T13	14		T15	25
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	171	1			T10	1		T15	1		T16	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1516	1			T10	1		T15	1		T17	16
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	180	1			T10	1		T17	1		T25	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1367	1			T10	1		T17	11		T25	5
auto[1]	auto[1]	auto[0:524287]	auto[0]	39	1			T16	1		T27	2		T29	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	298	1			T16	4		T27	17		T29	11
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	42	1			T75	1		T33	1		T160	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	170	1			T160	1		T73	2		T263	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	52	1			T18	5		T29	1		T75	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	300	1			T18	4		T29	17		T75	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	33	1			T10	1		T27	1		T18	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	331	1			T10	5		T27	22		T29	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	42	1			T25	1		T26	1		T27	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	453	1			T25	2		T26	10		T27	12
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	34	1			T27	2		T56	1		T73	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	244	1			T27	15		T64	3		T179	67
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	50	1			T10	1		T17	1		T18	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	397	1			T10	2		T17	18		T18	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	33	1			T18	1		T75	1		T154	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	234	1			T154	1		T163	9		T74	26

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1804321	1			T1	1		T2	1		T3	14
auto[0]	auto[0]	auto[1]	919887	1			T3	208		T4	3952		T7	7117
auto[0]	auto[1]	auto[0]	419572	1			T10	2406		T12	1029		T15	668
auto[0]	auto[1]	auto[1]	3999	1			T27	2		T29	1		T111	1
auto[1]	auto[0]	auto[0]	12211	1			T10	23		T12	27		T13	63
auto[1]	auto[0]	auto[1]	226	1			T13	3		T15	1		T17	5
auto[1]	auto[1]	auto[0]	2701	1			T10	9		T16	5		T17	18
auto[1]	auto[1]	auto[1]	51	1			T17	1		T27	5		T163	3