Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15305

1

T3

10

T7

2

T10

166

auto[1]

11606

1

T1

22

T10

146

T12

46

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3481	1			T10	51		T17	56		T29	63
values[1]	3433	1			T10	95		T17	42		T195	4
values[2]	2790	1			T7	2		T10	20		T12	20
values[3]	2826	1			T10	43		T17	20		T25	24
values[4]	3243	1			T10	20		T12	20		T17	20
values[5]	3401	1			T1	22		T3	10		T10	23
values[6]	4120	1			T10	20		T17	74		T25	73
values[7]	3617	1			T10	40		T12	20		T17	55

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3842	1			T17	54		T29	64		T30	31
values[1]	3420	1			T10	49		T12	40		T29	67
values[2]	2641	1			T10	42		T17	56		T97	10
values[3]	3731	1			T17	52		T25	27		T29	106
values[4]	3822	1			T3	10		T10	63		T17	75
values[5]	3163	1			T10	47		T25	79		T29	149
values[6]	3210	1			T1	22		T10	20		T12	44
values[7]	3082	1			T7	2		T10	91		T25	45

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	431	1			T156	30		T165	12		T154	26
auto[0]	values[0]	values[1]	275	1			T10	9		T29	13		T30	14
auto[0]	values[0]	values[2]	294	1			T10	11		T17	29		T176	11
auto[0]	values[0]	values[3]	311	1			T190	6		T33	17		T74	89
auto[0]	values[0]	values[4]	242	1			T165	65		T169	45		T269	12
auto[0]	values[0]	values[5]	161	1			T29	31		T34	9		T154	13
auto[0]	values[0]	values[6]	132	1			T17	16		T154	5		T176	10
auto[0]	values[0]	values[7]	192	1			T30	13		T175	12		T68	7
auto[0]	values[1]	values[0]	356	1			T68	13		T179	134		T166	13
auto[0]	values[1]	values[1]	274	1			T10	10		T171	15		T199	8
auto[0]	values[1]	values[2]	193	1			T34	11		T153	14		T157	12
auto[0]	values[1]	values[3]	340	1			T29	14		T176	48		T169	22
auto[0]	values[1]	values[4]	241	1			T17	12		T30	14		T156	12
auto[0]	values[1]	values[5]	232	1			T10	13		T155	20		T154	13
auto[0]	values[1]	values[6]	101	1			T17	10		T195	4		T187	2
auto[0]	values[1]	values[7]	282	1			T10	24		T29	11		T191	6
auto[0]	values[2]	values[0]	338	1			T29	8		T165	9		T169	11
auto[0]	values[2]	values[1]	264	1			T30	20		T32	14		T163	16
auto[0]	values[2]	values[2]	172	1			T154	43		T199	14		T196	6
auto[0]	values[2]	values[3]	221	1			T17	25		T33	10		T154	9
auto[0]	values[2]	values[4]	208	1			T29	16		T33	6		T176	6
auto[0]	values[2]	values[5]	147	1			T34	12		T222	14		T270	8
auto[0]	values[2]	values[6]	111	1			T10	11		T12	9		T210	25
auto[0]	values[2]	values[7]	126	1			T7	2		T25	20		T169	5
auto[0]	values[3]	values[0]	167	1			T271	2		T182	15		T164	11
auto[0]	values[3]	values[1]	232	1			T29	12		T165	16		T154	9
auto[0]	values[3]	values[2]	100	1			T156	8		T33	8		T176	10
auto[0]	values[3]	values[3]	134	1			T17	12		T154	25		T163	9
auto[0]	values[3]	values[4]	254	1			T10	13		T25	14		T34	8
auto[0]	values[3]	values[5]	170	1			T156	12		T33	16		T186	2
auto[0]	values[3]	values[6]	312	1			T30	27		T165	13		T154	11
auto[0]	values[3]	values[7]	126	1			T10	15		T194	18		T199	9
auto[0]	values[4]	values[0]	119	1			T30	8		T176	11		T177	6
auto[0]	values[4]	values[1]	191	1			T12	11		T33	15		T153	16
auto[0]	values[4]	values[2]	173	1			T17	14		T32	11		T153	11
auto[0]	values[4]	values[3]	171	1			T184	18		T166	10		T216	15
auto[0]	values[4]	values[4]	231	1			T30	11		T32	11		T34	6
auto[0]	values[4]	values[5]	257	1			T25	14		T29	11		T30	10
auto[0]	values[4]	values[6]	336	1			T25	14		T163	43		T126	14
auto[0]	values[4]	values[7]	332	1			T10	16		T87	8		T29	28
auto[0]	values[5]	values[0]	129	1			T163	8		T169	15		T194	13
auto[0]	values[5]	values[1]	201	1			T165	12		T164	27		T254	13
auto[0]	values[5]	values[2]	194	1			T33	11		T154	29		T272	16
auto[0]	values[5]	values[3]	330	1			T25	22		T29	18		T156	10
auto[0]	values[5]	values[4]	283	1			T3	10		T10	13		T156	13
auto[0]	values[5]	values[5]	346	1			T29	11		T273	14		T154	12
auto[0]	values[5]	values[6]	236	1			T12	6		T17	10		T25	11
auto[0]	values[5]	values[7]	164	1			T163	8		T199	8		T126	11
auto[0]	values[6]	values[0]	250	1			T17	45		T176	15		T171	12
auto[0]	values[6]	values[1]	312	1			T34	16		T153	13		T274	6
auto[0]	values[6]	values[2]	275	1			T29	35		T34	14		T175	14
auto[0]	values[6]	values[3]	324	1			T29	18		T32	30		T74	17
auto[0]	values[6]	values[4]	320	1			T32	11		T171	10		T248	18
auto[0]	values[6]	values[5]	310	1			T10	4		T25	38		T29	32
auto[0]	values[6]	values[6]	265	1			T17	10		T34	12		T163	16
auto[0]	values[6]	values[7]	253	1			T25	6		T32	12		T163	11
auto[0]	values[7]	values[0]	299	1			T29	13		T161	14		T153	22
auto[0]	values[7]	values[1]	347	1			T12	12		T29	19		T30	8
auto[0]	values[7]	values[2]	192	1			T10	12		T97	10		T33	11
auto[0]	values[7]	values[3]	299	1			T29	9		T30	10		T82	8
auto[0]	values[7]	values[4]	361	1			T10	15		T17	16		T154	12
auto[0]	values[7]	values[5]	154	1			T163	11		T166	26		T234	12
auto[0]	values[7]	values[6]	299	1			T33	26		T165	23		T194	19
auto[0]	values[7]	values[7]	213	1			T29	8		T176	7		T194	10
auto[1]	values[0]	values[0]	219	1			T156	53		T165	8		T154	19
auto[1]	values[0]	values[1]	196	1			T10	20		T29	9		T30	10
auto[1]	values[0]	values[2]	205	1			T10	11		T17	7		T176	59
auto[1]	values[0]	values[3]	349	1			T33	4		T74	115		T254	6
auto[1]	values[0]	values[4]	68	1			T165	6		T169	7		T171	12
auto[1]	values[0]	values[5]	139	1			T29	10		T34	11		T154	7
auto[1]	values[0]	values[6]	109	1			T17	4		T154	17		T176	10
auto[1]	values[0]	values[7]	158	1			T30	32		T31	14		T249	6
auto[1]	values[1]	values[0]	146	1			T68	30		T179	6		T166	7
auto[1]	values[1]	values[1]	154	1			T10	10		T171	5		T255	4
auto[1]	values[1]	values[2]	123	1			T34	9		T153	6		T157	8
auto[1]	values[1]	values[3]	256	1			T29	6		T176	8		T169	7
auto[1]	values[1]	values[4]	239	1			T17	8		T30	7		T156	8
auto[1]	values[1]	values[5]	133	1			T10	14		T154	7		T182	6
auto[1]	values[1]	values[6]	56	1			T17	12		T182	11		T203	9
auto[1]	values[1]	values[7]	307	1			T10	24		T29	21		T156	8
auto[1]	values[2]	values[0]	291	1			T29	36		T165	11		T169	9
auto[1]	values[2]	values[1]	97	1			T30	2		T32	6		T163	4
auto[1]	values[2]	values[2]	151	1			T154	6		T199	7		T275	8
auto[1]	values[2]	values[3]	218	1			T17	7		T33	18		T154	16
auto[1]	values[2]	values[4]	157	1			T29	24		T33	64		T176	14
auto[1]	values[2]	values[5]	106	1			T34	8		T222	13		T203	9
auto[1]	values[2]	values[6]	100	1			T10	9		T12	11		T210	20
auto[1]	values[2]	values[7]	83	1			T25	5		T169	15		T194	6
auto[1]	values[3]	values[0]	183	1			T182	5		T164	9		T179	13
auto[1]	values[3]	values[1]	221	1			T29	8		T165	4		T154	11
auto[1]	values[3]	values[2]	133	1			T156	48		T33	12		T176	10
auto[1]	values[3]	values[3]	102	1			T17	8		T154	7		T163	11
auto[1]	values[3]	values[4]	241	1			T10	7		T25	10		T34	21
auto[1]	values[3]	values[5]	166	1			T156	8		T33	4		T170	4
auto[1]	values[3]	values[6]	148	1			T30	19		T165	7		T154	9
auto[1]	values[3]	values[7]	137	1			T10	8		T194	2		T199	11
auto[1]	values[4]	values[0]	137	1			T30	23		T176	9		T163	35
auto[1]	values[4]	values[1]	164	1			T12	9		T33	5		T153	4
auto[1]	values[4]	values[2]	150	1			T17	6		T32	9		T153	9
auto[1]	values[4]	values[3]	137	1			T166	48		T216	11		T42	14
auto[1]	values[4]	values[4]	188	1			T30	9		T32	9		T34	16
auto[1]	values[4]	values[5]	272	1			T25	12		T29	9		T30	10
auto[1]	values[4]	values[6]	131	1			T25	6		T163	8		T126	11
auto[1]	values[4]	values[7]	254	1			T10	4		T29	12		T261	2
auto[1]	values[5]	values[0]	173	1			T163	12		T169	24		T194	27
auto[1]	values[5]	values[1]	125	1			T165	8		T164	6		T254	7
auto[1]	values[5]	values[2]	82	1			T33	9		T154	13		T198	5
auto[1]	values[5]	values[3]	200	1			T25	5		T29	8		T156	10
auto[1]	values[5]	values[4]	173	1			T10	10		T156	7		T33	6
auto[1]	values[5]	values[5]	237	1			T29	9		T154	16		T176	20
auto[1]	values[5]	values[6]	404	1			T1	22		T12	18		T17	12
auto[1]	values[5]	values[7]	124	1			T163	12		T199	19		T126	9
auto[1]	values[6]	values[0]	360	1			T17	9		T176	5		T171	8
auto[1]	values[6]	values[1]	221	1			T34	4		T153	9		T182	10
auto[1]	values[6]	values[2]	110	1			T29	13		T34	6		T175	6
auto[1]	values[6]	values[3]	206	1			T29	22		T32	7		T74	11
auto[1]	values[6]	values[4]	311	1			T32	64		T171	10		T168	28
auto[1]	values[6]	values[5]	166	1			T10	16		T25	15		T29	36
auto[1]	values[6]	values[6]	288	1			T17	10		T185	20		T34	9
auto[1]	values[6]	values[7]	149	1			T25	14		T32	8		T163	9
auto[1]	values[7]	values[0]	244	1			T29	7		T153	4		T154	6
auto[1]	values[7]	values[1]	146	1			T12	8		T29	6		T30	12
auto[1]	values[7]	values[2]	94	1			T10	8		T33	9		T153	9
auto[1]	values[7]	values[3]	133	1			T29	11		T30	10		T33	12
auto[1]	values[7]	values[4]	305	1			T10	5		T17	39		T154	8
auto[1]	values[7]	values[5]	167	1			T163	30		T166	34		T234	8
auto[1]	values[7]	values[6]	182	1			T33	7		T165	4		T194	6
auto[1]	values[7]	values[7]	182	1			T29	30		T176	17		T194	20