Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2836433	1			T1	1		T2	1		T3	1
all_pins[1]	2836433	1			T1	1		T2	1		T3	1
all_pins[2]	2836433	1			T1	1		T2	1		T3	1
all_pins[3]	2836433	1			T1	1		T2	1		T3	1
all_pins[4]	2836433	1			T1	1		T2	1		T3	1
all_pins[5]	2836433	1			T1	1		T2	1		T3	1
all_pins[6]	2836433	1			T1	1		T2	1		T3	1
all_pins[7]	2836433	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22675221	1			T1	8		T2	8		T3	8
values[0x1]	16243	1			T6	43		T12	12		T29	10
transitions[0x0=>0x1]	15432	1			T6	33		T12	12		T29	10
transitions[0x1=>0x0]	15441	1			T6	33		T12	12		T29	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2836053	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	380	1			T6	4		T12	1		T29	1
all_pins[0]	transitions[0x0=>0x1]	267	1			T6	4		T12	1		T29	1
all_pins[0]	transitions[0x1=>0x0]	167	1			T6	8		T29	2		T152	2
all_pins[1]	values[0x0]	2836153	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	280	1			T6	8		T29	2		T152	2
all_pins[1]	transitions[0x0=>0x1]	218	1			T6	6		T29	2		T152	2
all_pins[1]	transitions[0x1=>0x0]	151	1			T6	6		T12	2		T29	1
all_pins[2]	values[0x0]	2836220	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	213	1			T6	8		T12	2		T29	1
all_pins[2]	transitions[0x0=>0x1]	160	1			T6	5		T12	2		T29	1
all_pins[2]	transitions[0x1=>0x0]	178	1			T6	3		T12	2		T57	1
all_pins[3]	values[0x0]	2836202	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	231	1			T6	6		T12	2		T57	2
all_pins[3]	transitions[0x0=>0x1]	179	1			T6	5		T12	2		T57	2
all_pins[3]	transitions[0x1=>0x0]	167	1			T6	3		T29	2		T57	2
all_pins[4]	values[0x0]	2836214	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	219	1			T6	4		T29	2		T57	2
all_pins[4]	transitions[0x0=>0x1]	175	1			T6	3		T29	2		T57	2
all_pins[4]	transitions[0x1=>0x0]	486	1			T6	2		T12	2		T29	1
all_pins[5]	values[0x0]	2835903	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	530	1			T6	3		T12	2		T29	1
all_pins[5]	transitions[0x0=>0x1]	156	1			T6	3		T12	2		T29	1
all_pins[5]	transitions[0x1=>0x0]	13812	1			T6	6		T12	3		T29	3
all_pins[6]	values[0x0]	2822247	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	14186	1			T6	6		T12	3		T29	3
all_pins[6]	transitions[0x0=>0x1]	14128	1			T6	3		T12	3		T29	3
all_pins[6]	transitions[0x1=>0x0]	146	1			T6	1		T12	2		T57	2
all_pins[7]	values[0x0]	2836229	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	204	1			T6	4		T12	2		T57	2
all_pins[7]	transitions[0x0=>0x1]	149	1			T6	4		T12	2		T57	2
all_pins[7]	transitions[0x1=>0x0]	334	1			T6	4		T12	1		T29	1