Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	341	1			T10	9		T12	3		T17	2
auto[ReadAddrCrossIntoMailbox]	319	1			T10	3		T12	3		T17	2
auto[ReadAddrCrossOutOfMailbox]	293	1			T10	1		T12	4		T17	3
auto[ReadAddrCrossAllMailbox]	214	1			T10	2		T17	2		T29	3
auto[ReadAddrOutsideMailbox]	3269	1			T1	10		T10	46		T12	10

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2219

1

T1

5

T10

32

T12

8

auto[1]

2217

1

T1

5

T10

29

T12

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	742	1			T10	9		T12	2		T17	6
read_ops[0x0b]	675	1			T10	12		T12	2		T17	8
read_ops[0x3b]	767	1			T1	6		T10	12		T12	6
read_ops[0x6b]	730	1			T10	7		T12	7		T17	5
read_ops[0xbb]	754	1			T10	11		T12	2		T17	13
read_ops[0xeb]	768	1			T1	4		T10	10		T12	1

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T10	1		T25	1		T156	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T33	1		T153	1		T181	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T25	1		T154	1		T189	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T29	2		T165	3		T154	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T12	1		T25	1		T33	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T33	1		T169	2		T157	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T254	1		T227	3		T276	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T30	1		T153	1		T165	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	277	1			T10	1		T12	1		T17	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	287	1			T10	7		T17	2		T97	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T10	1		T87	1		T29	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T10	1		T87	1		T177	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T10	1		T30	1		T169	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T156	1		T165	1		T164	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T17	1		T29	1		T32	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T156	1		T169	1		T74	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T10	1		T176	1		T194	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T165	1		T74	1		T254	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	238	1			T10	8		T17	7		T25	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	252	1			T12	2		T25	2		T29	7
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T10	1		T34	1		T165	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T10	1		T12	1		T17	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T34	1		T165	1		T154	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T17	1		T32	1		T154	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T10	1		T12	1		T34	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T12	1		T30	1		T33	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T10	1		T30	1		T34	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T29	1		T189	1		T74	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	296	1			T1	3		T10	2		T12	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T1	3		T10	6		T12	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T12	1		T165	2		T176	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T10	1		T33	1		T153	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T165	1		T154	1		T164	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T12	3		T33	1		T154	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T12	1		T17	1		T25	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T165	1		T154	4		T177	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T17	1		T29	1		T156	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T33	1		T154	1		T176	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	265	1			T10	4		T17	2		T97	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	267	1			T10	2		T12	2		T17	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T10	1		T30	1		T33	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	16	1			T10	2		T29	1		T165	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T10	1		T17	1		T29	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T10	1		T190	2		T171	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T29	1		T33	1		T176	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T17	1		T169	2		T74	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T17	1		T165	1		T154	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T34	1		T163	1		T74	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	288	1			T10	2		T12	2		T17	9
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	273	1			T10	4		T17	1		T25	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T34	2		T154	1		T222	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T12	1		T25	1		T29	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	37	1			T33	1		T154	2		T169	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T29	1		T32	1		T165	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T34	2		T153	2		T165	3
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T29	1		T156	1		T165	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T30	1		T176	1		T189	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T29	1		T165	2		T199	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	265	1			T1	2		T10	6		T17	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T1	2		T10	4		T17	2