Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3171	1			T10	45		T25	21		T29	38
values[1]	3509	1			T10	65		T25	72		T29	63
values[2]	3094	1			T3	10		T10	20		T17	62
values[3]	3490	1			T10	40		T17	20		T25	27
values[4]	3453	1			T12	20		T17	87		T97	10
values[5]	3680	1			T10	40		T12	24		T17	90
values[6]	3300	1			T7	2		T10	53		T12	20
values[7]	3214	1			T1	22		T10	49		T12	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3824	1			T17	20		T25	21		T29	112
values[1]	2799	1			T12	24		T17	55		T25	20
values[2]	3486	1			T10	42		T17	94		T97	10
values[3]	3366	1			T10	83		T29	60		T30	26
values[4]	3749	1			T10	22		T12	20		T17	78
values[5]	3073	1			T7	2		T10	75		T25	69
values[6]	3362	1			T1	22		T3	10		T10	70
values[7]	3252	1			T10	20		T12	40		T25	27

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26509

1

T1

20

T3

10

T7

2

auto[1]

402

1

T1

2

T10

3

T17

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[2]]	[values[2]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	344	1			T25	19		T161	14		T162	24
auto[0]	values[0]	values[1]	336	1			T163	20		T157	20		T164	21
auto[0]	values[0]	values[2]	450	1			T153	20		T165	20		T166	20
auto[0]	values[0]	values[3]	446	1			T29	37		T30	25		T153	20
auto[0]	values[0]	values[4]	395	1			T10	21		T30	24		T166	44
auto[0]	values[0]	values[5]	240	1			T162	21		T167	12		T168	33
auto[0]	values[0]	values[6]	526	1			T10	23		T154	22		T169	52
auto[0]	values[0]	values[7]	371	1			T170	4		T154	20		T171	20
auto[0]	values[1]	values[0]	277	1			T172	4		T173	14		T174	20
auto[0]	values[1]	values[1]	356	1			T32	74		T154	25		T175	31
auto[0]	values[1]	values[2]	500	1			T10	22		T176	56		T177	6
auto[0]	values[1]	values[3]	399	1			T10	42		T153	20		T176	20
auto[0]	values[1]	values[4]	566	1			T25	20		T30	20		T178	22
auto[0]	values[1]	values[5]	480	1			T25	20		T29	19		T30	21
auto[0]	values[1]	values[6]	321	1			T25	32		T154	72		T179	32
auto[0]	values[1]	values[7]	573	1			T29	43		T30	19		T34	20
auto[0]	values[2]	values[0]	302	1			T33	21		T153	22		T165	16
auto[0]	values[2]	values[1]	385	1			T29	65		T31	12		T169	32
auto[0]	values[2]	values[2]	136	1			T17	20		T163	20		T168	20
auto[0]	values[2]	values[3]	355	1			T29	21		T154	46		T166	20
auto[0]	values[2]	values[4]	481	1			T17	22		T30	31		T74	20
auto[0]	values[2]	values[5]	304	1			T29	20		T32	20		T171	31
auto[0]	values[2]	values[6]	647	1			T3	10		T10	20		T17	19
auto[0]	values[2]	values[7]	429	1			T180	10		T181	4		T182	45
auto[0]	values[3]	values[0]	746	1			T29	44		T33	53		T165	20
auto[0]	values[3]	values[1]	395	1			T171	20		T183	2		T126	21
auto[0]	values[3]	values[2]	485	1			T29	19		T32	20		T165	20
auto[0]	values[3]	values[3]	428	1			T10	40		T33	20		T34	20
auto[0]	values[3]	values[4]	500	1			T17	20		T156	62		T33	21
auto[0]	values[3]	values[5]	282	1			T184	18		T169	20		T171	17
auto[0]	values[3]	values[6]	302	1			T154	20		T68	43		T171	21
auto[0]	values[3]	values[7]	316	1			T25	26		T185	20		T176	42
auto[0]	values[4]	values[0]	445	1			T186	2		T187	2		T188	26
auto[0]	values[4]	values[1]	391	1			T17	55		T34	20		T165	27
auto[0]	values[4]	values[2]	541	1			T17	31		T97	10		T155	20
auto[0]	values[4]	values[3]	187	1			T154	23		T74	21		T71	2
auto[0]	values[4]	values[4]	615	1			T87	8		T29	20		T33	20
auto[0]	values[4]	values[5]	460	1			T156	20		T34	20		T154	19
auto[0]	values[4]	values[6]	438	1			T156	21		T33	20		T34	27
auto[0]	values[4]	values[7]	322	1			T12	20		T169	29		T157	31
auto[0]	values[5]	values[0]	490	1			T29	20		T154	20		T176	20
auto[0]	values[5]	values[1]	406	1			T12	24		T25	20		T156	24
auto[0]	values[5]	values[2]	531	1			T10	20		T29	21		T165	20
auto[0]	values[5]	values[3]	346	1			T34	21		T189	20		T74	21
auto[0]	values[5]	values[4]	473	1			T17	36		T29	20		T190	6
auto[0]	values[5]	values[5]	424	1			T29	43		T30	41		T82	8
auto[0]	values[5]	values[6]	359	1			T17	52		T29	44		T163	62
auto[0]	values[5]	values[7]	604	1			T10	20		T29	20		T191	6
auto[0]	values[6]	values[0]	501	1			T17	20		T29	25		T33	19
auto[0]	values[6]	values[1]	216	1			T189	20		T157	69		T192	8
auto[0]	values[6]	values[2]	249	1			T17	20		T163	20		T169	39
auto[0]	values[6]	values[3]	654	1			T154	20		T193	16		T194	112
auto[0]	values[6]	values[4]	492	1			T25	26		T195	4		T33	28
auto[0]	values[6]	values[5]	512	1			T7	2		T10	26		T25	24
auto[0]	values[6]	values[6]	282	1			T10	27		T29	32		T196	6
auto[0]	values[6]	values[7]	333	1			T12	20		T197	8		T198	25
auto[0]	values[7]	values[0]	664	1			T29	20		T32	19		T153	26
auto[0]	values[7]	values[1]	268	1			T153	20		T163	39		T166	18
auto[0]	values[7]	values[2]	547	1			T17	22		T32	37		T156	76
auto[0]	values[7]	values[3]	487	1			T176	20		T74	78		T199	36
auto[0]	values[7]	values[4]	191	1			T12	20		T182	19		T157	23
auto[0]	values[7]	values[5]	319	1			T10	48		T25	24		T30	40
auto[0]	values[7]	values[6]	432	1			T1	20		T29	20		T163	20
auto[0]	values[7]	values[7]	257	1			T30	25		T33	20		T171	20
auto[1]	values[0]	values[0]	5	1			T25	2		T162	1		T200	1
auto[1]	values[0]	values[1]	6	1			T174	1		T201	2		T202	2
auto[1]	values[0]	values[2]	11	1			T203	1		T204	1		T205	5
auto[1]	values[0]	values[3]	19	1			T29	1		T30	1		T154	2
auto[1]	values[0]	values[4]	5	1			T10	1		T205	1		T200	2
auto[1]	values[0]	values[5]	4	1			T168	2		T206	1		T207	1
auto[1]	values[0]	values[6]	3	1			T203	1		T208	1		T209	1
auto[1]	values[0]	values[7]	10	1			T199	4		T210	1		T203	1
auto[1]	values[1]	values[0]	3	1			T211	1		T130	1		T212	1
auto[1]	values[1]	values[1]	3	1			T32	1		T213	1		T214	1
auto[1]	values[1]	values[2]	6	1			T182	2		T147	1		T215	1
auto[1]	values[1]	values[3]	6	1			T10	1		T162	1		T179	1
auto[1]	values[1]	values[4]	3	1			T216	1		T42	1		T148	1
auto[1]	values[1]	values[5]	6	1			T29	1		T30	1		T126	2
auto[1]	values[1]	values[6]	4	1			T217	1		T198	1		T218	2
auto[1]	values[1]	values[7]	6	1			T30	1		T174	1		T147	1
auto[1]	values[2]	values[0]	8	1			T33	2		T165	4		T217	1
auto[1]	values[2]	values[1]	9	1			T29	2		T31	2		T169	1
auto[1]	values[2]	values[3]	8	1			T29	1		T154	3		T219	1
auto[1]	values[2]	values[4]	7	1			T126	1		T162	3		T220	2
auto[1]	values[2]	values[5]	6	1			T126	2		T221	4		-	-
auto[1]	values[2]	values[6]	14	1			T17	1		T165	1		T162	3
auto[1]	values[2]	values[7]	3	1			T126	1		T203	1		T209	1
auto[1]	values[3]	values[0]	5	1			T29	1		T33	1		T176	1
auto[1]	values[3]	values[1]	2	1			T126	1		T210	1		-	-
auto[1]	values[3]	values[2]	4	1			T29	1		T222	1		T210	1
auto[1]	values[3]	values[3]	8	1			T203	2		T148	1		T215	1
auto[1]	values[3]	values[4]	1	1			T223	1		-	-		-	-
auto[1]	values[3]	values[5]	9	1			T171	3		T224	2		T211	2
auto[1]	values[3]	values[6]	5	1			T154	1		T201	2		T225	2
auto[1]	values[3]	values[7]	2	1			T25	1		T214	1		-	-
auto[1]	values[4]	values[0]	7	1			T198	2		T226	1		T148	2
auto[1]	values[4]	values[1]	13	1			T74	4		T174	3		T220	3
auto[1]	values[4]	values[2]	11	1			T17	1		T32	2		T33	2
auto[1]	values[4]	values[3]	2	1			T42	2		-	-		-	-
auto[1]	values[4]	values[4]	5	1			T154	1		T179	1		T129	1
auto[1]	values[4]	values[5]	5	1			T154	1		T182	2		T227	1
auto[1]	values[4]	values[6]	9	1			T34	2		T163	1		T42	2
auto[1]	values[4]	values[7]	2	1			T228	2		-	-		-	-
auto[1]	values[5]	values[0]	8	1			T198	2		T227	2		T219	2
auto[1]	values[5]	values[1]	4	1			T156	2		T145	1		T147	1
auto[1]	values[5]	values[2]	4	1			T163	2		T166	1		T208	1
auto[1]	values[5]	values[3]	5	1			T229	4		T215	1		-	-
auto[1]	values[5]	values[4]	6	1			T154	2		T221	1		T223	2
auto[1]	values[5]	values[5]	4	1			T29	2		T211	1		T230	1
auto[1]	values[5]	values[6]	7	1			T17	2		T231	2		T216	1
auto[1]	values[5]	values[7]	9	1			T163	2		T42	1		T145	2
auto[1]	values[6]	values[0]	9	1			T29	2		T33	1		T224	2
auto[1]	values[6]	values[1]	2	1			T223	2		-	-		-	-
auto[1]	values[6]	values[2]	3	1			T147	1		T232	1		T215	1
auto[1]	values[6]	values[3]	8	1			T194	2		T216	2		T203	2
auto[1]	values[6]	values[4]	8	1			T233	2		T129	1		T205	1
auto[1]	values[6]	values[5]	11	1			T156	1		T33	1		T154	2
auto[1]	values[6]	values[6]	8	1			T166	5		T234	1		T235	2
auto[1]	values[6]	values[7]	12	1			T198	4		T208	1		T236	6
auto[1]	values[7]	values[0]	10	1			T32	1		T165	2		T220	3
auto[1]	values[7]	values[1]	7	1			T163	2		T166	2		T237	1
auto[1]	values[7]	values[2]	8	1			T158	2		T157	1		T208	3
auto[1]	values[7]	values[3]	8	1			T166	3		T201	3		T205	2
auto[1]	values[7]	values[4]	1	1			T182	1		-	-		-	-
auto[1]	values[7]	values[5]	7	1			T10	1		T25	1		T203	2
auto[1]	values[7]	values[6]	5	1			T1	2		T179	1		T228	1
auto[1]	values[7]	values[7]	3	1			T179	1		T238	1		T223	1