Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1804

1

T9

11

T10

10

T11

5

auto[1]

1763

1

T9

4

T10

14

T11

13

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1974

1

T10

24

T12

16

T15

1

auto[1]

1593

1

T9

15

T11

18

T12

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2832

1

T9

15

T10

17

T11

18

auto[1]

735

1

T10

7

T12

10

T16

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	699	1			T9	4		T10	4		T11	5
valid[1]	720	1			T9	5		T10	7		T11	1
valid[2]	701	1			T10	4		T11	3		T12	3
valid[3]	763	1			T9	2		T10	6		T11	7
valid[4]	684	1			T9	4		T10	3		T11	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	130	1			T10	2		T12	2		T17	1
auto[0]	auto[0]	valid[0]	auto[1]	163	1			T9	2		T12	2		T14	1
auto[0]	auto[0]	valid[1]	auto[0]	116	1			T10	2		T17	1		T25	1
auto[0]	auto[0]	valid[1]	auto[1]	155	1			T9	4		T11	1		T25	1
auto[0]	auto[0]	valid[2]	auto[0]	122	1			T10	1		T12	1		T15	1
auto[0]	auto[0]	valid[2]	auto[1]	157	1			T11	1		T29	1		T81	7
auto[0]	auto[0]	valid[3]	auto[0]	125	1			T10	1		T12	1		T16	2
auto[0]	auto[0]	valid[3]	auto[1]	175	1			T9	2		T11	2		T14	2
auto[0]	auto[0]	valid[4]	auto[0]	129	1			T10	1		T16	2		T18	1
auto[0]	auto[0]	valid[4]	auto[1]	165	1			T9	3		T11	1		T29	1
auto[0]	auto[1]	valid[0]	auto[0]	138	1			T10	2		T12	1		T16	2
auto[0]	auto[1]	valid[0]	auto[1]	148	1			T9	2		T11	5		T80	1
auto[0]	auto[1]	valid[1]	auto[0]	124	1			T10	3		T12	1		T16	1
auto[0]	auto[1]	valid[1]	auto[1]	170	1			T9	1		T14	1		T25	1
auto[0]	auto[1]	valid[2]	auto[0]	123	1			T10	2		T18	1		T30	2
auto[0]	auto[1]	valid[2]	auto[1]	136	1			T11	2		T29	1		T81	3
auto[0]	auto[1]	valid[3]	auto[0]	123	1			T10	2		T18	3		T29	1
auto[0]	auto[1]	valid[3]	auto[1]	179	1			T11	5		T14	3		T29	1
auto[0]	auto[1]	valid[4]	auto[0]	109	1			T10	1		T16	2		T18	2
auto[0]	auto[1]	valid[4]	auto[1]	145	1			T9	1		T11	1		T14	1
auto[1]	auto[0]	valid[0]	auto[0]	65	1			T12	1		T40	1		T29	2
auto[1]	auto[0]	valid[1]	auto[0]	81	1			T10	1		T12	2		T16	1
auto[1]	auto[0]	valid[2]	auto[0]	75	1			T16	1		T25	1		T18	1
auto[1]	auto[0]	valid[3]	auto[0]	79	1			T10	2		T12	2		T56	1
auto[1]	auto[0]	valid[4]	auto[0]	67	1			T25	1		T40	1		T29	1
auto[1]	auto[1]	valid[0]	auto[0]	55	1			T16	1		T17	1		T25	1
auto[1]	auto[1]	valid[1]	auto[0]	74	1			T10	1		T24	1		T18	1
auto[1]	auto[1]	valid[2]	auto[0]	88	1			T10	1		T12	2		T16	2
auto[1]	auto[1]	valid[3]	auto[0]	82	1			T10	1		T12	2		T17	1
auto[1]	auto[1]	valid[4]	auto[0]	69	1			T10	1		T12	1		T16	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal