Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	874	1			T6	17		T12	14		T29	4
all_values[1]	874	1			T6	17		T12	14		T29	4
all_values[2]	874	1			T6	17		T12	14		T29	4
all_values[3]	874	1			T6	17		T12	14		T29	4
all_values[4]	874	1			T6	17		T12	14		T29	4
all_values[5]	874	1			T6	17		T12	14		T29	4
all_values[6]	874	1			T6	17		T12	14		T29	4
all_values[7]	874	1			T6	17		T12	14		T29	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3725

1

T6

67

T12

53

T29

19

auto[1]

3267

1

T6

69

T12

59

T29

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2802

1

T6

57

T12

66

T29

14

auto[1]

4190

1

T6

79

T12

46

T29

18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3964

1

T6

72

T12

73

T29

20

auto[1]

3028

1

T6

64

T12

39

T29

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	177	1			T6	5		T12	3		T57	4
all_values[0]	auto[0]	auto[0]	auto[1]	82	1			T6	1		T57	2		T151	1
all_values[0]	auto[0]	auto[1]	auto[0]	177	1			T6	5		T12	6		T29	2
all_values[0]	auto[0]	auto[1]	auto[1]	75	1			T6	1		T12	1		T151	2
all_values[0]	auto[1]	auto[0]	auto[1]	197	1			T6	3		T12	1		T29	2
all_values[0]	auto[1]	auto[1]	auto[1]	166	1			T6	2		T12	3		T57	3
all_values[1]	auto[0]	auto[0]	auto[0]	178	1			T29	2		T57	5		T152	2
all_values[1]	auto[0]	auto[0]	auto[1]	78	1			T6	2		T151	3		T144	2
all_values[1]	auto[0]	auto[1]	auto[0]	151	1			T6	2		T12	9		T57	3
all_values[1]	auto[0]	auto[1]	auto[1]	91	1			T6	1		T29	1		T57	1
all_values[1]	auto[1]	auto[0]	auto[1]	191	1			T6	8		T12	4		T29	1
all_values[1]	auto[1]	auto[1]	auto[1]	185	1			T6	4		T12	1		T152	6
all_values[2]	auto[0]	auto[0]	auto[0]	191	1			T6	2		T12	5		T29	1
all_values[2]	auto[0]	auto[0]	auto[1]	63	1			T12	1		T151	1		T153	1
all_values[2]	auto[0]	auto[1]	auto[0]	151	1			T6	4		T12	2		T29	2
all_values[2]	auto[0]	auto[1]	auto[1]	81	1			T6	2		T12	1		T57	1
all_values[2]	auto[1]	auto[0]	auto[1]	199	1			T6	2		T12	4		T57	2
all_values[2]	auto[1]	auto[1]	auto[1]	189	1			T6	7		T12	1		T29	1
all_values[3]	auto[0]	auto[0]	auto[0]	182	1			T6	3		T12	4		T57	3
all_values[3]	auto[0]	auto[0]	auto[1]	83	1			T6	1		T12	2		T29	2
all_values[3]	auto[0]	auto[1]	auto[0]	149	1			T6	2		T12	2		T29	1
all_values[3]	auto[0]	auto[1]	auto[1]	86	1			T6	2		T12	1		T152	1
all_values[3]	auto[1]	auto[0]	auto[1]	184	1			T6	4		T12	4		T57	2
all_values[3]	auto[1]	auto[1]	auto[1]	190	1			T6	5		T12	1		T29	1
all_values[4]	auto[0]	auto[0]	auto[0]	168	1			T6	7		T12	3		T57	2
all_values[4]	auto[0]	auto[0]	auto[1]	79	1			T29	1		T57	3		T152	3
all_values[4]	auto[0]	auto[1]	auto[0]	158	1			T6	1		T12	9		T57	3
all_values[4]	auto[0]	auto[1]	auto[1]	88	1			T6	1		T29	1		T57	1
all_values[4]	auto[1]	auto[0]	auto[1]	207	1			T6	5		T12	1		T29	2
all_values[4]	auto[1]	auto[1]	auto[1]	174	1			T6	3		T12	1		T57	2
all_values[5]	auto[0]	auto[0]	auto[0]	279	1			T6	3		T12	5		T29	1
all_values[5]	auto[0]	auto[1]	auto[0]	216	1			T6	9		T12	2		T29	1
all_values[5]	auto[1]	auto[0]	auto[1]	214	1			T6	2		T12	4		T29	2
all_values[5]	auto[1]	auto[1]	auto[1]	165	1			T6	3		T12	3		T57	2
all_values[6]	auto[0]	auto[0]	auto[0]	174	1			T6	2		T12	1		T152	2
all_values[6]	auto[0]	auto[0]	auto[1]	102	1			T57	1		T151	1		T144	3
all_values[6]	auto[0]	auto[1]	auto[0]	116	1			T6	4		T12	6		T57	3
all_values[6]	auto[0]	auto[1]	auto[1]	89	1			T6	2		T29	1		T57	1
all_values[6]	auto[1]	auto[0]	auto[1]	226	1			T6	8		T12	2		T29	1
all_values[6]	auto[1]	auto[1]	auto[1]	167	1			T6	1		T12	5		T29	2
all_values[7]	auto[0]	auto[0]	auto[0]	180	1			T6	3		T12	6		T29	4
all_values[7]	auto[0]	auto[0]	auto[1]	81	1			T6	1		T152	1		T151	2
all_values[7]	auto[0]	auto[1]	auto[0]	155	1			T6	5		T12	3		T57	4
all_values[7]	auto[0]	auto[1]	auto[1]	84	1			T6	1		T12	1		T152	2
all_values[7]	auto[1]	auto[0]	auto[1]	210	1			T6	5		T12	3		T57	4
all_values[7]	auto[1]	auto[1]	auto[1]	164	1			T6	2		T12	1		T57	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal