Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49851

1

T5

11

T10

484

T12

452

auto[1]

17597

1

T9

172

T11

168

T12

44

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49297

1

T5

7

T9

172

T10

300

auto[1]

18151

1

T5

4

T10

184

T12

177

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34795	1			T5	4		T9	94		T10	251
others[1]	5635	1			T5	2		T9	10		T10	26
others[2]	5681	1			T9	15		T10	48		T11	15
others[3]	6371	1			T5	2		T9	17		T10	56
interest[1]	3724	1			T5	2		T9	11		T10	24
interest[4]	22664	1			T5	3		T9	60		T10	164
interest[64]	11242	1			T5	1		T9	25		T10	79

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16256	1			T5	2		T10	157		T12	134
auto[0]	auto[0]	others[1]	2744	1			T5	2		T10	18		T12	21
auto[0]	auto[0]	others[2]	2717	1			T10	34		T12	27		T15	6
auto[0]	auto[0]	others[3]	3042	1			T5	1		T10	32		T12	33
auto[0]	auto[0]	interest[1]	1752	1			T5	2		T10	13		T12	18
auto[0]	auto[0]	interest[4]	10597	1			T5	2		T10	99		T12	83
auto[0]	auto[0]	interest[64]	5189	1			T10	46		T12	42		T15	7
auto[0]	auto[1]	others[0]	9265	1			T9	94		T11	82		T12	19
auto[0]	auto[1]	others[1]	1401	1			T9	10		T11	18		T12	3
auto[0]	auto[1]	others[2]	1404	1			T9	15		T11	15		T12	4
auto[0]	auto[1]	others[3]	1634	1			T9	17		T11	17		T12	7
auto[0]	auto[1]	interest[1]	995	1			T9	11		T11	10		T12	5
auto[0]	auto[1]	interest[4]	6085	1			T9	60		T11	60		T12	10
auto[0]	auto[1]	interest[64]	2898	1			T9	25		T11	26		T12	6
auto[1]	auto[0]	others[0]	9274	1			T5	2		T10	94		T12	87
auto[1]	auto[0]	others[1]	1490	1			T10	8		T12	27		T15	2
auto[1]	auto[0]	others[2]	1560	1			T10	14		T12	17		T15	1
auto[1]	auto[0]	others[3]	1695	1			T5	1		T10	24		T12	12
auto[1]	auto[0]	interest[1]	977	1			T10	11		T12	9		T15	2
auto[1]	auto[0]	interest[4]	5982	1			T5	1		T10	65		T12	54
auto[1]	auto[0]	interest[64]	3155	1			T5	1		T10	33		T12	25

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal