Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2956104	1			T2	20924		T3	1082		T5	1
all_values[1]	2956104	1			T2	20924		T3	1082		T5	1
all_values[2]	2956104	1			T2	20924		T3	1082		T5	1
all_values[3]	2956104	1			T2	20924		T3	1082		T5	1
all_values[4]	2956104	1			T2	20924		T3	1082		T5	1
all_values[5]	2956104	1			T2	20924		T3	1082		T5	1
all_values[6]	2956104	1			T2	20924		T3	1082		T5	1
all_values[7]	2956104	1			T2	20924		T3	1082		T5	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816986

1

T2

167392

T3

8656

T5

8

auto[1]

1831846

1

T8

24522

T53

85426

T27

29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23624315

1

T2

167311

T3

8653

T5

8

auto[1]

24517

1

T2

81

T3

3

T8

141

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2772461	1			T2	20876		T3	1081		T5	1
all_values[0]	auto[0]	auto[1]	12189	1			T2	48		T3	1		T8	79
all_values[0]	auto[1]	auto[0]	170566	1			T8	1		T53	16958		T27	4
all_values[0]	auto[1]	auto[1]	888	1			T8	1		T53	117		T27	1
all_values[1]	auto[0]	auto[0]	2679842	1			T2	20902		T3	1081		T5	1
all_values[1]	auto[0]	auto[1]	5798	1			T2	22		T3	1		T8	4
all_values[1]	auto[1]	auto[0]	269743	1			T8	4068		T53	5		T55	6
all_values[1]	auto[1]	auto[1]	721	1			T8	19		T53	3		T27	1
all_values[2]	auto[0]	auto[0]	2711233	1			T2	20913		T3	1081		T5	1
all_values[2]	auto[0]	auto[1]	2536	1			T2	11		T3	1		T8	3
all_values[2]	auto[1]	auto[0]	241964	1			T8	4086		T53	17059		T27	2
all_values[2]	auto[1]	auto[1]	371	1			T8	1		T53	21		T27	1
all_values[3]	auto[0]	auto[0]	2732109	1			T2	20924		T3	1082		T5	1
all_values[3]	auto[0]	auto[1]	195	1			T8	5		T53	3		T27	1
all_values[3]	auto[1]	auto[0]	223592	1			T8	4082		T53	17079		T27	3
all_values[3]	auto[1]	auto[1]	208	1			T8	1		T53	5		T55	4
all_values[4]	auto[0]	auto[0]	2620762	1			T2	20924		T3	1082		T5	1
all_values[4]	auto[0]	auto[1]	177	1			T8	2		T53	2		T27	1
all_values[4]	auto[1]	auto[0]	334969	1			T8	4083		T53	17082		T27	1
all_values[4]	auto[1]	auto[1]	196	1			T8	3		T53	2		T27	1
all_values[5]	auto[0]	auto[0]	2790224	1			T2	20924		T3	1082		T5	1
all_values[5]	auto[0]	auto[1]	279	1			T8	3		T17	8		T255	3
all_values[5]	auto[1]	auto[0]	165400	1			T8	4081		T53	1		T27	2
all_values[5]	auto[1]	auto[1]	201	1			T8	4		T53	3		T27	3
all_values[6]	auto[0]	auto[0]	2725776	1			T2	20924		T3	1082		T5	1
all_values[6]	auto[0]	auto[1]	194	1			T8	3		T53	5		T27	1
all_values[6]	auto[1]	auto[0]	229976	1			T8	1		T53	8		T27	4
all_values[6]	auto[1]	auto[1]	158	1			T8	4		T53	3		T27	1
all_values[7]	auto[0]	auto[0]	2763023	1			T2	20924		T3	1082		T5	1
all_values[7]	auto[0]	auto[1]	188	1			T8	3		T53	2		T27	1
all_values[7]	auto[1]	auto[0]	192675	1			T8	4081		T53	17075		T27	2
all_values[7]	auto[1]	auto[1]	218	1			T8	6		T53	5		T27	3