Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	31692	1			T2	49		T3	11		T6	2
auto[SpiFlashAddrCfg]	6668	1			T2	25		T3	6		T6	2
auto[SpiFlashAddr3b]	8060	1			T2	33		T3	3		T5	2
auto[SpiFlashAddr4b]	6823	1			T2	25		T3	2		T5	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29967

1

T2

67

T3

13

T5

6

auto[1]

23276

1

T2

65

T3

9

T8

98

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27436

1

T2

74

T3

9

T5

4

auto[1]

25807

1

T2

58

T3

13

T5

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	35824	1			T2	63		T3	13		T5	2
values[1]	942	1			T2	1		T5	2		T8	6
values[2]	1288	1			T2	1		T8	9		T10	10
values[3]	1281	1			T2	1		T3	2		T8	10
values[4]	1251	1			T2	5		T8	6		T10	6
values[5]	1404	1			T2	4		T8	5		T10	6
values[6]	1324	1			T2	4		T10	10		T12	3
values[7]	1294	1			T2	6		T3	1		T6	2
values[8]	8635	1			T2	47		T3	6		T5	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25458

1

T2

132

T3

22

T5

6

auto[1]

27785

1

T8

218

T10

373

T13

49

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

51295

1

T2

124

T3

21

T5

6

write

1948

1

T2

8

T3

1

T8

8

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

17512

1

T2

64

T3

11

T5

2

valids[0x1]

35731

1

T2

68

T3

11

T5

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1457	1			T2	2		T3	1		T8	4
internal_process_ops[0x5a]	1471	1			T2	7		T8	6		T10	11
internal_process_ops[0x05]	19373	1			T2	16		T3	2		T8	47
internal_process_ops[0x35]	1365	1			T2	4		T3	1		T8	8
internal_process_ops[0x15]	1376	1			T2	1		T8	4		T10	14
internal_process_ops[0x03]	854	1			T2	8		T5	2		T8	5
internal_process_ops[0x0b]	917	1			T2	4		T3	1		T5	2
internal_process_ops[0x3b]	913	1			T2	6		T8	2		T10	3
internal_process_ops[0x6b]	971	1			T2	7		T3	1		T6	2
internal_process_ops[0xbb]	898	1			T2	1		T3	1		T8	1
internal_process_ops[0xeb]	987	1			T2	4		T8	4		T10	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52264

1

T2

125

T3

21

T5

6

auto[1]

979

1

T2

7

T3

1

T8

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51258

1

T2

125

T3

21

T5

6

auto[1]

1985

1

T2

7

T3

1

T8

11

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8729

1

T2

25

T3

7

T6

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5139

1

T2

23

T3

3

T12

3

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1730

1

T2

10

T3

3

T6

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1604

1

T2

13

T3

3

T12

3

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2141

1

T2

14

T3

1

T5

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1813

1

T2

14

T3

2

T12

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1890

1

T2

16

T3

2

T5

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1535

1

T2

9

T12

1

T16

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

66

1

T24

1

T158

2

T18

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

47

1

T24

2

T28

1

T30

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

55

1

T12

1

T24

4

T28

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

56

1

T2

1

T3

1

T24

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

66

1

T36

4

T159

2

T160

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

46

1

T2

1

T26

2

T28

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

58

1

T2

1

T24

3

T25

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

53

1

T16

1

T18

2

T27

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

63

1

T24

1

T25

2

T18

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

66

1

T2

1

T18

2

T26

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

42

1

T24

1

T18

1

T27

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

53

1

T2

4

T26

2

T28

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

57

1

T18

1

T28

1

T30

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

64

1

T24

1

T26

3

T161

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

35

1

T16

1

T28

2

T162

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

50

1

T24

1

T27

2

T28

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9834

1

T8

74

T10

105

T13

6

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7522

1

T8

38

T10

130

T13

32

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1449

1

T8

13

T10

16

T15

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1432

1

T8

17

T10

24

T13

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1821

1

T8

13

T10

22

T15

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1766

1

T8

18

T10

24

T13

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1375

1

T8

19

T10

26

T13

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1515

1

T8

18

T10

13

T13

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

49

1

T69

2

T65

3

T163

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

84

1

T10

3

T15

1

T22

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

59

1

T8

2

T22

1

T69

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

52

1

T8

3

T69

2

T71

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

60

1

T10

1

T69

1

T71

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

56

1

T8

1

T10

2

T13

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

64

1

T71

1

T65

3

T164

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

50

1

T8

1

T10

3

T69

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

63

1

T15

1

T71

3

T165

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

84

1

T10

2

T22

6

T71

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

66

1

T53

1

T62

1

T165

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

82

1

T10

2

T22

1

T71

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

78

1

T22

3

T165

1

T166

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

49

1

T22

1

T69

3

T53

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

88

1

T22

3

T62

2

T165

6

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

87

1

T8

1

T22

1

T69

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3393	1			T2	22		T3	5		T6	2
auto[0]	values[0]	valids[0x1]	12715	1			T2	41		T3	8		T5	2
auto[0]	values[1]	valids[0x1]	444	1			T2	1		T5	2		T24	6
auto[0]	values[2]	valids[0x0]	426	1			T2	1		T16	1		T24	3
auto[0]	values[2]	valids[0x1]	248	1			T12	2		T16	3		T24	6
auto[0]	values[3]	valids[0x0]	444	1			T12	1		T16	1		T167	6
auto[0]	values[3]	valids[0x1]	262	1			T2	1		T3	2		T24	2
auto[0]	values[4]	valids[0x0]	398	1			T2	5		T12	4		T16	2
auto[0]	values[4]	valids[0x1]	240	1			T16	1		T24	11		T168	6
auto[0]	values[5]	valids[0x0]	551	1			T167	8		T24	4		T32	2
auto[0]	values[5]	valids[0x1]	256	1			T2	4		T12	3		T16	2
auto[0]	values[6]	valids[0x0]	464	1			T2	1		T12	1		T24	8
auto[0]	values[6]	valids[0x1]	276	1			T2	3		T12	2		T16	1
auto[0]	values[7]	valids[0x0]	452	1			T2	1		T3	1		T6	2
auto[0]	values[7]	valids[0x1]	233	1			T2	5		T35	2		T24	2
auto[0]	values[8]	valids[0x0]	2959	1			T2	34		T3	5		T5	2
auto[0]	values[8]	valids[0x1]	1697	1			T2	13		T3	1		T12	4
auto[1]	values[0]	valids[0x0]	4007	1			T8	48		T10	57		T13	6
auto[1]	values[0]	valids[0x1]	15709	1			T8	87		T10	212		T13	35
auto[1]	values[1]	valids[0x1]	498	1			T8	6		T10	8		T15	2
auto[1]	values[2]	valids[0x0]	399	1			T8	8		T10	5		T13	2
auto[1]	values[2]	valids[0x1]	215	1			T8	1		T10	5		T15	2
auto[1]	values[3]	valids[0x0]	320	1			T8	6		T10	2		T22	6
auto[1]	values[3]	valids[0x1]	255	1			T8	4		T10	1		T22	8
auto[1]	values[4]	valids[0x0]	345	1			T8	1		T10	1		T22	7
auto[1]	values[4]	valids[0x1]	268	1			T8	5		T10	5		T15	1
auto[1]	values[5]	valids[0x0]	367	1			T8	3		T10	4		T22	1
auto[1]	values[5]	valids[0x1]	230	1			T8	2		T10	2		T15	1
auto[1]	values[6]	valids[0x0]	345	1			T10	2		T13	1		T15	2
auto[1]	values[6]	valids[0x1]	239	1			T10	8		T22	3		T69	4
auto[1]	values[7]	valids[0x0]	340	1			T8	4		T10	4		T15	1
auto[1]	values[7]	valids[0x1]	269	1			T15	1		T22	1		T69	3
auto[1]	values[8]	valids[0x0]	2302	1			T8	26		T10	37		T13	4
auto[1]	values[8]	valids[0x1]	1677	1			T8	17		T10	20		T13	1