Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3010371

1

T2

6408

T3

135

T5

1

auto[1]

17973

1

T2

12

T3

2

T8

38

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

945238

1

T2

43

T3

7

T5

1

auto[1]

2083106

1

T2

6377

T3

130

T8

7646

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	566759	1			T2	9		T3	1		T5	1
auto[524288:1048575]	339519	1			T2	141		T7	721		T8	3388
auto[1048576:1572863]	376977	1			T2	258		T7	467		T8	1006
auto[1572864:2097151]	383853	1			T7	551		T8	1011		T10	1
auto[2097152:2621439]	339203	1			T2	6007		T3	1		T8	5
auto[2621440:3145727]	330786	1			T2	2		T3	134		T7	466
auto[3145728:3670015]	331757	1			T3	1		T8	401		T10	2
auto[3670016:4194303]	359490	1			T2	3		T8	1599		T10	261

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2102939

1

T2

6420

T3

137

T5

1

auto[1]

925405

1

T7

2798

T10

21

T13

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2621437

1

T2

6415

T3

137

T5

1

auto[1]

406907

1

T2

5

T8

1413

T10

1389

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	240774	1			T2	5		T3	1		T5	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	289253	1			T2	2		T10	225		T12	1
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	97888	1			T2	4		T7	721		T8	5
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	199965	1			T2	130		T8	3379		T10	1857
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	92024	1			T2	2		T7	467		T8	13
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	220831	1			T2	256		T8	987		T10	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	108918	1			T7	551		T8	5		T10	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	219385	1			T8	3		T15	1		T24	2542
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	92160	1			T2	15		T3	1		T8	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	193285	1			T2	5984		T8	4		T10	4527
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	102267	1			T2	2		T3	3		T7	466
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	167947	1			T3	129		T8	128		T10	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	98719	1			T3	1		T8	4		T10	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	173288	1			T8	134		T24	2		T22	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	102794	1			T2	3		T8	5		T10	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	207567	1			T8	1594		T10	257		T24	7908
auto[0]	auto[1]	auto[0:524287]	auto[0]	831	1			T2	1		T8	2		T10	15
auto[0]	auto[1]	auto[0:524287]	auto[1]	32820	1			T8	1		T10	784		T24	8
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	689	1			T2	4		T8	1		T71	6
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	39096	1			T71	515		T53	128		T26	257
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2145	1			T10	2		T24	2		T69	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	59764	1			T10	512		T24	261		T69	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	886	1			T8	1		T15	1		T69	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	52550	1			T8	979		T15	4449		T69	2188
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	750	1			T10	2		T13	1		T15	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	50824	1			T10	2		T13	1		T15	2476
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1402	1			T8	4		T10	2		T15	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	57293	1			T8	153		T16	3		T24	768
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	506	1			T8	2		T22	5		T69	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	56920	1			T8	257		T22	2513		T71	129
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	500	1			T10	1		T24	1		T22	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	46330	1			T24	1		T22	1		T18	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	295	1			T2	1		T10	7		T15	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2328	1			T10	39		T36	85		T22	23
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	186	1			T2	2		T8	1		T10	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1458	1			T2	1		T8	2		T10	13
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	209	1			T8	4		T10	2		T12	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1608	1			T8	2		T10	11		T12	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	173	1			T8	3		T15	1		T69	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1415	1			T8	13		T15	1		T69	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	177	1			T2	4		T10	1		T24	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1458	1			T2	4		T10	4		T22	8
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	164	1			T3	1		T10	1		T16	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1416	1			T3	1		T10	2		T16	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	192	1			T24	2		T22	1		T69	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1595	1			T22	2		T69	19		T268	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	200	1			T10	1		T24	6		T22	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1498	1			T24	4		T22	2		T71	5
auto[1]	auto[1]	auto[0:524287]	auto[0]	53	1			T8	1		T10	6		T24	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	405	1			T8	1		T10	62		T24	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	46	1			T71	1		T26	1		T27	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	191	1			T71	1		T26	18		T27	12
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	48	1			T69	1		T71	4		T53	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	348	1			T69	16		T71	51		T53	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	51	1			T8	1		T69	1		T53	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	475	1			T8	6		T69	33		T53	24
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	53	1			T10	1		T13	1		T71	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	496	1			T13	28		T71	37		T62	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	47	1			T22	1		T71	1		T18	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	250	1			T71	6		T18	6		T28	6
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	44	1			T8	1		T22	1		T71	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	493	1			T8	3		T22	2		T71	36
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	47	1			T24	1		T22	1		T18	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	554	1			T22	4		T18	2		T26	21

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1687477	1			T2	6403		T3	135		T5	1
auto[0]	auto[0]	auto[1]	919588	1			T7	2798		T10	5		T83	370
auto[0]	auto[1]	auto[0]	397898	1			T2	5		T8	1400		T10	1318
auto[0]	auto[1]	auto[1]	5408	1			T10	2		T13	1		T22	1
auto[1]	auto[0]	auto[0]	14038	1			T2	12		T3	2		T8	25
auto[1]	auto[0]	auto[1]	334	1			T10	10		T24	2		T36	1
auto[1]	auto[1]	auto[0]	3526	1			T8	13		T10	65		T13	29
auto[1]	auto[1]	auto[1]	75	1			T10	4		T22	1		T69	1