Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14965

1

T2

67

T3

13

T5

6

auto[1]

10493

1

T2

65

T3

9

T12

16

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3534	1			T2	20		T24	22		T63	8
values[1]	3321	1			T5	6		T36	105		T32	2
values[2]	3061	1			T12	20		T172	18		T25	20
values[3]	2904	1			T2	48		T6	4		T24	70
values[4]	3522	1			T16	20		T24	40		T85	24
values[5]	3062	1			T3	22		T16	24		T24	65
values[6]	2596	1			T2	44		T35	14		T167	22
values[7]	3458	1			T2	20		T12	22		T24	21

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3527	1			T2	60		T6	4		T35	14
values[1]	2749	1			T5	6		T24	22		T172	18
values[2]	3592	1			T2	48		T12	42		T167	22
values[3]	3535	1			T3	22		T24	24		T171	12
values[4]	2702	1			T24	20		T84	12		T173	8
values[5]	2782	1			T24	20		T32	2		T25	88
values[6]	3587	1			T24	24		T159	12		T25	35
values[7]	2984	1			T2	24		T16	20		T85	24

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	237	1			T2	9		T30	71		T185	9
auto[0]	values[0]	values[1]	209	1			T31	78		T264	10		T161	32
auto[0]	values[0]	values[2]	247	1			T24	11		T63	8		T26	13
auto[0]	values[0]	values[3]	321	1			T26	46		T211	2		T201	10
auto[0]	values[0]	values[4]	315	1			T31	150		T161	10		T177	2
auto[0]	values[0]	values[5]	265	1			T18	12		T129	26		T186	9
auto[0]	values[0]	values[6]	316	1			T26	37		T81	8		T181	18
auto[0]	values[0]	values[7]	198	1			T26	17		T29	11		T30	6
auto[0]	values[1]	values[0]	291	1			T49	2		T248	14		T186	12
auto[0]	values[1]	values[1]	164	1			T5	6		T187	8		T161	11
auto[0]	values[1]	values[2]	524	1			T36	105		T18	9		T27	12
auto[0]	values[1]	values[3]	183	1			T28	13		T193	17		T229	15
auto[0]	values[1]	values[4]	118	1			T26	9		T161	14		T186	17
auto[0]	values[1]	values[5]	206	1			T32	2		T18	12		T30	8
auto[0]	values[1]	values[6]	230	1			T29	10		T122	4		T183	11
auto[0]	values[1]	values[7]	155	1			T25	10		T129	9		T147	18
auto[0]	values[2]	values[0]	185	1			T129	8		T147	15		T193	12
auto[0]	values[2]	values[1]	203	1			T172	18		T27	17		T29	27
auto[0]	values[2]	values[2]	466	1			T12	14		T26	13		T27	103
auto[0]	values[2]	values[3]	388	1			T18	10		T170	15		T28	38
auto[0]	values[2]	values[4]	137	1			T25	12		T27	11		T29	10
auto[0]	values[2]	values[5]	205	1			T18	14		T26	12		T129	22
auto[0]	values[2]	values[6]	289	1			T198	2		T160	12		T30	9
auto[0]	values[2]	values[7]	223	1			T30	7		T185	44		T230	8
auto[0]	values[3]	values[0]	419	1			T2	11		T6	4		T30	12
auto[0]	values[3]	values[1]	318	1			T24	13		T202	14		T193	13
auto[0]	values[3]	values[2]	215	1			T2	12		T161	24		T229	17
auto[0]	values[3]	values[3]	152	1			T24	6		T171	12		T30	10
auto[0]	values[3]	values[4]	134	1			T26	11		T178	17		T147	7
auto[0]	values[3]	values[5]	175	1			T25	6		T28	12		T147	12
auto[0]	values[3]	values[6]	111	1			T24	11		T267	24		T183	10
auto[0]	values[3]	values[7]	172	1			T210	8		T182	11		T224	49
auto[0]	values[4]	values[0]	332	1			T24	13		T26	12		T27	12
auto[0]	values[4]	values[1]	178	1			T129	27		T175	8		T218	14
auto[0]	values[4]	values[2]	263	1			T29	15		T161	6		T82	6
auto[0]	values[4]	values[3]	366	1			T30	121		T277	2		T38	9
auto[0]	values[4]	values[4]	154	1			T24	18		T18	10		T206	14
auto[0]	values[4]	values[5]	124	1			T27	17		T31	12		T205	12
auto[0]	values[4]	values[6]	328	1			T30	15		T296	10		T201	15
auto[0]	values[4]	values[7]	316	1			T16	9		T85	24		T28	9
auto[0]	values[5]	values[0]	239	1			T16	15		T24	12		T26	37
auto[0]	values[5]	values[1]	128	1			T18	24		T191	2		T182	12
auto[0]	values[5]	values[2]	89	1			T24	13		T297	2		T186	16
auto[0]	values[5]	values[3]	245	1			T3	13		T207	36		T28	28
auto[0]	values[5]	values[4]	230	1			T27	9		T178	16		T176	11
auto[0]	values[5]	values[5]	156	1			T24	11		T276	6		T298	14
auto[0]	values[5]	values[6]	246	1			T159	12		T31	31		T193	34
auto[0]	values[5]	values[7]	252	1			T79	4		T31	12		T299	12
auto[0]	values[6]	values[0]	87	1			T35	14		T229	12		T40	6
auto[0]	values[6]	values[1]	100	1			T18	14		T129	27		T161	7
auto[0]	values[6]	values[2]	323	1			T2	9		T167	22		T24	15
auto[0]	values[6]	values[3]	143	1			T18	11		T212	4		T300	8
auto[0]	values[6]	values[4]	127	1			T84	12		T286	4		T193	13
auto[0]	values[6]	values[5]	237	1			T158	52		T26	10		T27	10
auto[0]	values[6]	values[6]	203	1			T201	16		T208	18		T147	12
auto[0]	values[6]	values[7]	220	1			T2	13		T26	14		T197	6
auto[0]	values[7]	values[0]	189	1			T2	13		T178	11		T196	10
auto[0]	values[7]	values[1]	227	1			T31	13		T185	15		T147	10
auto[0]	values[7]	values[2]	242	1			T12	12		T24	14		T190	10
auto[0]	values[7]	values[3]	252	1			T27	13		T28	34		T188	18
auto[0]	values[7]	values[4]	189	1			T173	8		T184	8		T129	13
auto[0]	values[7]	values[5]	321	1			T25	63		T129	57		T185	43
auto[0]	values[7]	values[6]	295	1			T25	10		T18	13		T213	31
auto[0]	values[7]	values[7]	393	1			T193	14		T200	15		T301	6
auto[1]	values[0]	values[0]	242	1			T2	11		T30	14		T185	11
auto[1]	values[0]	values[1]	148	1			T31	9		T161	12		T224	23
auto[1]	values[0]	values[2]	179	1			T24	11		T26	7		T27	18
auto[1]	values[0]	values[3]	124	1			T26	3		T192	6		T201	17
auto[1]	values[0]	values[4]	264	1			T31	23		T161	10		T193	18
auto[1]	values[0]	values[5]	128	1			T18	8		T129	8		T186	14
auto[1]	values[0]	values[6]	152	1			T26	9		T182	9		T226	8
auto[1]	values[0]	values[7]	189	1			T26	13		T29	10		T30	14
auto[1]	values[1]	values[0]	281	1			T121	22		T248	8		T186	14
auto[1]	values[1]	values[1]	239	1			T161	22		T147	12		T230	5
auto[1]	values[1]	values[2]	188	1			T18	11		T27	8		T30	32
auto[1]	values[1]	values[3]	102	1			T28	9		T193	6		T229	6
auto[1]	values[1]	values[4]	213	1			T26	52		T161	15		T186	13
auto[1]	values[1]	values[5]	162	1			T18	8		T30	53		T178	9
auto[1]	values[1]	values[6]	168	1			T29	10		T183	11		T38	9
auto[1]	values[1]	values[7]	97	1			T25	10		T129	11		T147	8
auto[1]	values[2]	values[0]	75	1			T129	12		T147	6		T193	9
auto[1]	values[2]	values[1]	84	1			T27	6		T29	11		T129	10
auto[1]	values[2]	values[2]	122	1			T12	6		T26	30		T27	6
auto[1]	values[2]	values[3]	111	1			T18	19		T170	5		T28	7
auto[1]	values[2]	values[4]	87	1			T25	8		T27	9		T29	12
auto[1]	values[2]	values[5]	127	1			T18	6		T26	10		T129	13
auto[1]	values[2]	values[6]	202	1			T30	11		T31	72		T201	5
auto[1]	values[2]	values[7]	157	1			T30	65		T185	9		T230	12
auto[1]	values[3]	values[0]	290	1			T2	9		T30	41		T178	17
auto[1]	values[3]	values[1]	112	1			T24	9		T193	9		T38	8
auto[1]	values[3]	values[2]	103	1			T2	16		T161	37		T229	5
auto[1]	values[3]	values[3]	207	1			T24	18		T30	58		T178	17
auto[1]	values[3]	values[4]	154	1			T26	9		T178	3		T147	14
auto[1]	values[3]	values[5]	147	1			T25	14		T28	8		T302	14
auto[1]	values[3]	values[6]	104	1			T24	13		T303	14		T183	10
auto[1]	values[3]	values[7]	91	1			T182	9		T224	13		T304	10
auto[1]	values[4]	values[0]	293	1			T24	7		T169	18		T26	8
auto[1]	values[4]	values[1]	165	1			T129	92		T218	6		T305	4
auto[1]	values[4]	values[2]	185	1			T29	9		T161	14		T147	9
auto[1]	values[4]	values[3]	157	1			T30	16		T38	11		T229	8
auto[1]	values[4]	values[4]	154	1			T24	2		T18	30		T129	22
auto[1]	values[4]	values[5]	187	1			T27	5		T31	8		T216	24
auto[1]	values[4]	values[6]	159	1			T30	5		T201	5		T161	10
auto[1]	values[4]	values[7]	161	1			T16	11		T28	17		T29	9
auto[1]	values[5]	values[0]	173	1			T16	9		T24	9		T66	10
auto[1]	values[5]	values[1]	251	1			T18	30		T209	22		T182	11
auto[1]	values[5]	values[2]	71	1			T24	11		T186	13		T40	5
auto[1]	values[5]	values[3]	324	1			T3	9		T28	152		T201	9
auto[1]	values[5]	values[4]	171	1			T27	34		T178	7		T176	15
auto[1]	values[5]	values[5]	86	1			T24	9		T38	11		T239	8
auto[1]	values[5]	values[6]	286	1			T31	7		T193	30		T186	11
auto[1]	values[5]	values[7]	115	1			T31	8		T193	7		T182	5
auto[1]	values[6]	values[0]	66	1			T229	11		T40	28		T245	8
auto[1]	values[6]	values[1]	111	1			T18	6		T129	4		T161	13
auto[1]	values[6]	values[2]	221	1			T2	11		T24	6		T28	17
auto[1]	values[6]	values[3]	238	1			T168	20		T18	9		T193	7
auto[1]	values[6]	values[4]	99	1			T193	7		T248	9		T183	14
auto[1]	values[6]	values[5]	152	1			T26	10		T27	25		T125	8
auto[1]	values[6]	values[6]	163	1			T201	13		T208	8		T147	13
auto[1]	values[6]	values[7]	106	1			T2	11		T26	7		T193	6
auto[1]	values[7]	values[0]	128	1			T2	7		T178	9		T38	7
auto[1]	values[7]	values[1]	112	1			T64	4		T31	7		T185	19
auto[1]	values[7]	values[2]	154	1			T12	10		T24	7		T183	7
auto[1]	values[7]	values[3]	222	1			T27	53		T28	8		T193	5
auto[1]	values[7]	values[4]	156	1			T129	11		T185	33		T306	8
auto[1]	values[7]	values[5]	104	1			T25	5		T129	10		T185	11
auto[1]	values[7]	values[6]	335	1			T25	25		T18	7		T29	42
auto[1]	values[7]	values[7]	139	1			T193	6		T200	5		T218	8