Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2956104	1			T2	20924		T3	1082		T5	1
all_pins[1]	2956104	1			T2	20924		T3	1082		T5	1
all_pins[2]	2956104	1			T2	20924		T3	1082		T5	1
all_pins[3]	2956104	1			T2	20924		T3	1082		T5	1
all_pins[4]	2956104	1			T2	20924		T3	1082		T5	1
all_pins[5]	2956104	1			T2	20924		T3	1082		T5	1
all_pins[6]	2956104	1			T2	20924		T3	1082		T5	1
all_pins[7]	2956104	1			T2	20924		T3	1082		T5	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23414228	1			T2	167392		T3	8656		T5	8
values[0x1]	234604	1			T8	382		T53	171		T27	11
transitions[0x0=>0x1]	232650	1			T8	375		T53	166		T27	7
transitions[0x1=>0x0]	232668	1			T8	375		T53	166		T27	8

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2955138	1			T2	20924		T3	1082		T5	1
all_pins[0]	values[0x1]	966	1			T8	1		T53	127		T27	1
all_pins[0]	transitions[0x0=>0x1]	816	1			T8	1		T53	127		T27	1
all_pins[0]	transitions[0x1=>0x0]	629	1			T8	22		T53	3		T27	1
all_pins[1]	values[0x0]	2955325	1			T2	20924		T3	1082		T5	1
all_pins[1]	values[0x1]	779	1			T8	22		T53	3		T27	1
all_pins[1]	transitions[0x0=>0x1]	574	1			T8	21		T53	3		T27	1
all_pins[1]	transitions[0x1=>0x0]	186	1			T53	23		T27	1		T55	3
all_pins[2]	values[0x0]	2955713	1			T2	20924		T3	1082		T5	1
all_pins[2]	values[0x1]	391	1			T8	1		T53	23		T27	1
all_pins[2]	transitions[0x0=>0x1]	336	1			T8	1		T53	21		T27	1
all_pins[2]	transitions[0x1=>0x0]	153	1			T8	1		T53	3		T55	2
all_pins[3]	values[0x0]	2955896	1			T2	20924		T3	1082		T5	1
all_pins[3]	values[0x1]	208	1			T8	1		T53	5		T55	4
all_pins[3]	transitions[0x0=>0x1]	148	1			T53	5		T55	4		T146	3
all_pins[3]	transitions[0x1=>0x0]	136	1			T8	2		T53	2		T27	1
all_pins[4]	values[0x0]	2955908	1			T2	20924		T3	1082		T5	1
all_pins[4]	values[0x1]	196	1			T8	3		T53	2		T27	1
all_pins[4]	transitions[0x0=>0x1]	146	1			T8	1		T155	4		T156	4
all_pins[4]	transitions[0x1=>0x0]	2345	1			T8	342		T53	1		T27	2
all_pins[5]	values[0x0]	2953709	1			T2	20924		T3	1082		T5	1
all_pins[5]	values[0x1]	2395	1			T8	344		T53	3		T27	3
all_pins[5]	transitions[0x0=>0x1]	1070	1			T8	343		T53	3		T27	2
all_pins[5]	transitions[0x1=>0x0]	228126	1			T8	3		T53	3		T146	1
all_pins[6]	values[0x0]	2726653	1			T2	20924		T3	1082		T5	1
all_pins[6]	values[0x1]	229451	1			T8	4		T53	3		T27	1
all_pins[6]	transitions[0x0=>0x1]	229403	1			T8	2		T53	2		T27	1
all_pins[6]	transitions[0x1=>0x0]	170	1			T8	4		T53	4		T27	3
all_pins[7]	values[0x0]	2955886	1			T2	20924		T3	1082		T5	1
all_pins[7]	values[0x1]	218	1			T8	6		T53	5		T27	3
all_pins[7]	transitions[0x0=>0x1]	157	1			T8	6		T53	5		T27	1
all_pins[7]	transitions[0x1=>0x0]	923	1			T8	1		T53	127		T55	1