Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	338	1			T2	3		T12	1		T167	4
auto[ReadAddrCrossIntoMailbox]	265	1			T2	1		T12	4		T16	1
auto[ReadAddrCrossOutOfMailbox]	265	1			T2	2		T12	2		T167	2
auto[ReadAddrCrossAllMailbox]	171	1			T167	4		T24	3		T25	1
auto[ReadAddrOutsideMailbox]	3022	1			T2	24		T3	3		T5	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2072

1

T2

15

T3

2

T5

2

auto[1]

1989

1

T2

15

T3

1

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	624	1			T2	8		T5	2		T12	3
read_ops[0x0b]	683	1			T2	4		T3	1		T5	2
read_ops[0x3b]	679	1			T2	6		T12	3		T35	4
read_ops[0x6b]	729	1			T2	7		T3	1		T6	2
read_ops[0xbb]	643	1			T2	1		T3	1		T12	1
read_ops[0xeb]	703	1			T2	4		T12	1		T35	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T172	2		T25	1		T26	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T24	1		T172	2		T26	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T16	1		T167	1		T30	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T12	2		T167	1		T24	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T167	1		T24	1		T25	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T12	1		T167	1		T170	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T25	1		T18	1		T28	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T129	1		T161	1		T193	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	232	1			T2	3		T5	1		T16	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	222	1			T2	5		T5	1		T167	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T12	1		T26	1		T28	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T24	1		T26	3		T28	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T167	1		T170	1		T201	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T167	1		T24	1		T18	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T24	1		T178	1		T208	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T129	3		T147	1		T38	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T26	1		T27	1		T28	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T129	1		T161	1		T147	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T2	3		T3	1		T5	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	217	1			T2	1		T5	1		T12	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T2	1		T25	1		T28	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	19	1			T161	1		T147	1		T48	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T12	1		T25	1		T26	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T178	1		T193	1		T307	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T2	1		T18	1		T26	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	10	1			T24	1		T26	1		T40	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T18	1		T188	1		T182	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T26	1		T188	1		T208	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	274	1			T2	4		T12	2		T35	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	261	1			T35	2		T24	2		T171	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T167	1		T24	1		T25	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T167	1		T18	1		T26	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T25	1		T26	1		T129	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T24	3		T25	1		T27	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T24	2		T129	1		T161	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T12	1		T30	2		T186	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T167	2		T161	1		T183	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T167	2		T18	1		T170	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	268	1			T2	1		T3	1		T6	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	258	1			T2	6		T6	1		T167	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T2	1		T167	1		T24	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	17	1			T167	1		T24	1		T28	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T167	1		T24	1		T28	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T12	1		T167	1		T25	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T26	3		T28	2		T129	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T25	3		T28	2		T29	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T24	1		T188	1		T161	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T24	1		T26	2		T188	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	246	1			T167	1		T24	2		T172	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	230	1			T3	1		T167	1		T172	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	17	1			T26	1		T188	1		T308	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T2	1		T24	1		T18	3
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T24	1		T26	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T2	1		T184	1		T31	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T24	1		T26	1		T208	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T2	1		T18	1		T26	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T188	1		T218	1		T309	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T24	1		T18	1		T188	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	237	1			T2	1		T35	1		T85	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	297	1			T12	1		T35	1		T16	1