Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1776

1

T2

4

T3

4

T8

4

auto[1]

1849

1

T2

8

T3

4

T8

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1923

1

T2

10

T3

8

T8

7

auto[1]

1702

1

T2

2

T8

3

T9

14

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2880

1

T2

9

T3

6

T8

6

auto[1]

745

1

T2

3

T3

2

T8

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	708	1			T2	6		T3	1		T8	4
valid[1]	747	1			T3	2		T8	2		T9	2
valid[2]	724	1			T2	4		T3	1		T8	3
valid[3]	744	1			T2	2		T3	2		T9	3
valid[4]	702	1			T3	2		T8	1		T9	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	120	1			T3	1		T8	2		T23	1
auto[0]	auto[0]	valid[0]	auto[1]	166	1			T9	3		T14	3		T16	2
auto[0]	auto[0]	valid[1]	auto[0]	97	1			T3	2		T12	1		T321	1
auto[0]	auto[0]	valid[1]	auto[1]	175	1			T9	1		T14	1		T76	1
auto[0]	auto[0]	valid[2]	auto[0]	111	1			T2	1		T10	1		T16	1
auto[0]	auto[0]	valid[2]	auto[1]	162	1			T16	1		T76	1		T23	1
auto[0]	auto[0]	valid[3]	auto[0]	119	1			T2	1		T15	1		T16	1
auto[0]	auto[0]	valid[3]	auto[1]	163	1			T9	1		T76	3		T77	2
auto[0]	auto[0]	valid[4]	auto[0]	108	1			T22	1		T322	2		T329	1
auto[0]	auto[0]	valid[4]	auto[1]	167	1			T9	4		T15	2		T16	1
auto[0]	auto[1]	valid[0]	auto[0]	116	1			T2	3		T12	4		T23	1
auto[0]	auto[1]	valid[0]	auto[1]	169	1			T2	1		T8	1		T9	2
auto[0]	auto[1]	valid[1]	auto[0]	128	1			T8	1		T15	1		T16	1
auto[0]	auto[1]	valid[1]	auto[1]	183	1			T8	1		T9	1		T15	1
auto[0]	auto[1]	valid[2]	auto[0]	124	1			T2	2		T3	1		T10	1
auto[0]	auto[1]	valid[2]	auto[1]	176	1			T14	2		T76	2		T77	1
auto[0]	auto[1]	valid[3]	auto[0]	122	1			T3	1		T15	1		T324	2
auto[0]	auto[1]	valid[3]	auto[1]	190	1			T2	1		T9	2		T14	1
auto[0]	auto[1]	valid[4]	auto[0]	133	1			T3	1		T16	1		T24	3
auto[0]	auto[1]	valid[4]	auto[1]	151	1			T8	1		T14	1		T16	1
auto[1]	auto[0]	valid[0]	auto[0]	69	1			T2	1		T8	1		T15	1
auto[1]	auto[0]	valid[1]	auto[0]	86	1			T322	1		T329	1		T18	1
auto[1]	auto[0]	valid[2]	auto[0]	74	1			T2	1		T8	1		T16	1
auto[1]	auto[0]	valid[3]	auto[0]	80	1			T3	1		T15	1		T17	1
auto[1]	auto[0]	valid[4]	auto[0]	79	1			T24	1		T22	1		T324	1
auto[1]	auto[1]	valid[0]	auto[0]	68	1			T2	1		T23	1		T326	1
auto[1]	auto[1]	valid[1]	auto[0]	78	1			T10	1		T12	1		T323	1
auto[1]	auto[1]	valid[2]	auto[0]	77	1			T8	2		T12	1		T16	1
auto[1]	auto[1]	valid[3]	auto[0]	70	1			T12	1		T322	2		T18	1
auto[1]	auto[1]	valid[4]	auto[0]	64	1			T3	1		T16	1		T62	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal