Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	803	1			T8	11		T53	17		T27	7
all_values[1]	803	1			T8	11		T53	17		T27	7
all_values[2]	803	1			T8	11		T53	17		T27	7
all_values[3]	803	1			T8	11		T53	17		T27	7
all_values[4]	803	1			T8	11		T53	17		T27	7
all_values[5]	803	1			T8	11		T53	17		T27	7
all_values[6]	803	1			T8	11		T53	17		T27	7
all_values[7]	803	1			T8	11		T53	17		T27	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3445

1

T8

49

T53

76

T27

32

auto[1]

2979

1

T8

39

T53

60

T27

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2569

1

T8

26

T53

54

T27

20

auto[1]

3855

1

T8

62

T53

82

T27

36

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3694

1

T8

44

T53

79

T27

29

auto[1]

2730

1

T8

44

T53

57

T27

27

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	175	1			T8	1		T53	6		T55	4
all_values[0]	auto[0]	auto[0]	auto[1]	78	1			T8	2		T53	2		T155	2
all_values[0]	auto[0]	auto[1]	auto[0]	128	1			T8	1		T53	1		T27	2
all_values[0]	auto[0]	auto[1]	auto[1]	81	1			T55	2		T155	2		T156	1
all_values[0]	auto[1]	auto[0]	auto[1]	189	1			T8	5		T53	4		T27	3
all_values[0]	auto[1]	auto[1]	auto[1]	152	1			T8	2		T53	4		T27	2
all_values[1]	auto[0]	auto[0]	auto[0]	147	1			T8	1		T53	1		T27	1
all_values[1]	auto[0]	auto[0]	auto[1]	86	1			T8	1		T53	2		T27	1
all_values[1]	auto[0]	auto[1]	auto[0]	143	1			T8	1		T53	3		T55	4
all_values[1]	auto[0]	auto[1]	auto[1]	74	1			T8	3		T53	3		T27	1
all_values[1]	auto[1]	auto[0]	auto[1]	180	1			T8	2		T53	5		T27	4
all_values[1]	auto[1]	auto[1]	auto[1]	173	1			T8	3		T53	3		T146	2
all_values[2]	auto[0]	auto[0]	auto[0]	167	1			T8	1		T53	2		T27	1
all_values[2]	auto[0]	auto[0]	auto[1]	71	1			T8	2		T27	1		T147	3
all_values[2]	auto[0]	auto[1]	auto[0]	149	1			T8	5		T53	4		T27	1
all_values[2]	auto[0]	auto[1]	auto[1]	89	1			T53	3		T55	2		T146	2
all_values[2]	auto[1]	auto[0]	auto[1]	182	1			T8	2		T53	8		T27	3
all_values[2]	auto[1]	auto[1]	auto[1]	145	1			T8	1		T27	1		T55	2
all_values[3]	auto[0]	auto[0]	auto[0]	157	1			T8	2		T53	1		T27	1
all_values[3]	auto[0]	auto[0]	auto[1]	77	1			T8	3		T53	1		T146	1
all_values[3]	auto[0]	auto[1]	auto[0]	133	1			T8	2		T53	4		T27	3
all_values[3]	auto[0]	auto[1]	auto[1]	93	1			T53	3		T55	2		T146	1
all_values[3]	auto[1]	auto[0]	auto[1]	189	1			T8	3		T53	5		T27	3
all_values[3]	auto[1]	auto[1]	auto[1]	154	1			T8	1		T53	3		T55	3
all_values[4]	auto[0]	auto[0]	auto[0]	165	1			T8	2		T53	2		T27	3
all_values[4]	auto[0]	auto[0]	auto[1]	86	1			T53	1		T55	1		T155	1
all_values[4]	auto[0]	auto[1]	auto[0]	150	1			T8	3		T53	6		T55	2
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T8	1		T53	2		T27	1
all_values[4]	auto[1]	auto[0]	auto[1]	185	1			T8	2		T53	5		T27	3
all_values[4]	auto[1]	auto[1]	auto[1]	139	1			T8	3		T53	1		T146	1
all_values[5]	auto[0]	auto[0]	auto[0]	224	1			T8	2		T53	10		T27	1
all_values[5]	auto[0]	auto[1]	auto[0]	226	1			T8	2		T53	2		T27	2
all_values[5]	auto[1]	auto[0]	auto[1]	189	1			T8	4		T53	4		T27	2
all_values[5]	auto[1]	auto[1]	auto[1]	164	1			T8	3		T53	1		T27	2
all_values[6]	auto[0]	auto[0]	auto[0]	190	1			T8	2		T53	1		T27	1
all_values[6]	auto[0]	auto[0]	auto[1]	72	1			T8	2		T53	2		T157	3
all_values[6]	auto[0]	auto[1]	auto[0]	135	1			T53	2		T27	2		T55	1
all_values[6]	auto[0]	auto[1]	auto[1]	67	1			T8	2		T53	4		T27	1
all_values[6]	auto[1]	auto[0]	auto[1]	199	1			T8	4		T53	5		T27	1
all_values[6]	auto[1]	auto[1]	auto[1]	140	1			T8	1		T53	3		T27	2
all_values[7]	auto[0]	auto[0]	auto[0]	162	1			T8	1		T53	7		T146	2
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T27	2		T55	2		T146	1
all_values[7]	auto[0]	auto[1]	auto[0]	118	1			T53	2		T27	2		T155	2
all_values[7]	auto[0]	auto[1]	auto[1]	96	1			T8	2		T53	2		T27	2
all_values[7]	auto[1]	auto[0]	auto[1]	198	1			T8	5		T53	2		T27	1
all_values[7]	auto[1]	auto[1]	auto[1]	152	1			T8	3		T53	4		T55	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal