Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48814

1

T2

305

T3

200

T8

314

auto[1]

18070

1

T2

70

T8

52

T9

265

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48851

1

T2

266

T3

123

T8

235

auto[1]

18033

1

T2

109

T3

77

T8

131

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34429	1			T2	171		T3	87		T8	183
others[1]	5677	1			T2	34		T3	20		T8	29
others[2]	5585	1			T2	32		T3	17		T8	26
others[3]	6328	1			T2	45		T3	24		T8	33
interest[1]	3687	1			T2	28		T3	8		T8	27
interest[4]	22568	1			T2	105		T3	57		T8	126
interest[64]	11178	1			T2	65		T3	44		T8	68

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15729	1			T2	90		T3	52		T8	93
auto[0]	auto[0]	others[1]	2636	1			T2	16		T3	14		T8	13
auto[0]	auto[0]	others[2]	2537	1			T2	22		T3	10		T8	15
auto[0]	auto[0]	others[3]	2963	1			T2	23		T3	16		T8	15
auto[0]	auto[0]	interest[1]	1754	1			T2	19		T3	5		T8	15
auto[0]	auto[0]	interest[4]	10296	1			T2	53		T3	36		T8	65
auto[0]	auto[0]	interest[64]	5162	1			T2	26		T3	26		T8	32
auto[0]	auto[1]	others[0]	9510	1			T2	31		T8	22		T9	138
auto[0]	auto[1]	others[1]	1471	1			T2	7		T8	4		T9	21
auto[0]	auto[1]	others[2]	1505	1			T2	2		T8	4		T9	32
auto[0]	auto[1]	others[3]	1676	1			T2	12		T8	5		T9	23
auto[0]	auto[1]	interest[1]	957	1			T2	5		T8	3		T9	11
auto[0]	auto[1]	interest[4]	6282	1			T2	21		T8	15		T9	94
auto[0]	auto[1]	interest[64]	2951	1			T2	13		T8	14		T9	40
auto[1]	auto[0]	others[0]	9190	1			T2	50		T3	35		T8	68
auto[1]	auto[0]	others[1]	1570	1			T2	11		T3	6		T8	12
auto[1]	auto[0]	others[2]	1543	1			T2	8		T3	7		T8	7
auto[1]	auto[0]	others[3]	1689	1			T2	10		T3	8		T8	13
auto[1]	auto[0]	interest[1]	976	1			T2	4		T3	3		T8	9
auto[1]	auto[0]	interest[4]	5990	1			T2	31		T3	21		T8	46
auto[1]	auto[0]	interest[64]	3065	1			T2	26		T3	18		T8	22

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal