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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.10 98.35 94.20 98.61 89.36 97.23 95.82 99.15


Total test records in report: 1101
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1011 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1258048778 Jun 06 01:37:16 PM PDT 24 Jun 06 01:37:17 PM PDT 24 13959543 ps
T1012 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1007392530 Jun 06 01:37:12 PM PDT 24 Jun 06 01:37:13 PM PDT 24 443499208 ps
T1013 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1345691916 Jun 06 01:37:13 PM PDT 24 Jun 06 01:37:16 PM PDT 24 494800590 ps
T1014 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2889440781 Jun 06 01:37:20 PM PDT 24 Jun 06 01:37:22 PM PDT 24 59309327 ps
T1015 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1210599770 Jun 06 01:37:19 PM PDT 24 Jun 06 01:37:39 PM PDT 24 310259908 ps
T1016 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.150088550 Jun 06 01:38:02 PM PDT 24 Jun 06 01:38:04 PM PDT 24 18303779 ps
T1017 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2403317990 Jun 06 01:38:00 PM PDT 24 Jun 06 01:38:02 PM PDT 24 15159592 ps
T102 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3580550806 Jun 06 01:37:26 PM PDT 24 Jun 06 01:37:31 PM PDT 24 254126451 ps
T257 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1980503848 Jun 06 01:37:16 PM PDT 24 Jun 06 01:37:31 PM PDT 24 1098391203 ps
T1018 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1025918844 Jun 06 01:37:57 PM PDT 24 Jun 06 01:38:00 PM PDT 24 158459564 ps
T1019 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4103461628 Jun 06 01:37:14 PM PDT 24 Jun 06 01:37:15 PM PDT 24 42338790 ps
T1020 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.433016655 Jun 06 01:38:02 PM PDT 24 Jun 06 01:38:06 PM PDT 24 52230936 ps
T261 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2783188477 Jun 06 01:37:46 PM PDT 24 Jun 06 01:38:08 PM PDT 24 1736605074 ps
T1021 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.326052945 Jun 06 01:37:28 PM PDT 24 Jun 06 01:37:47 PM PDT 24 369278876 ps
T1022 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4278803657 Jun 06 01:37:58 PM PDT 24 Jun 06 01:38:00 PM PDT 24 191495076 ps
T118 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4237000305 Jun 06 01:37:08 PM PDT 24 Jun 06 01:37:44 PM PDT 24 972521052 ps
T1023 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3096977024 Jun 06 01:37:57 PM PDT 24 Jun 06 01:37:59 PM PDT 24 17702489 ps
T1024 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1707916370 Jun 06 01:37:46 PM PDT 24 Jun 06 01:37:50 PM PDT 24 60574331 ps
T1025 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.511871895 Jun 06 01:37:45 PM PDT 24 Jun 06 01:37:48 PM PDT 24 89070476 ps
T75 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2546614252 Jun 06 01:37:07 PM PDT 24 Jun 06 01:37:09 PM PDT 24 25494658 ps
T1026 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1677780209 Jun 06 01:37:46 PM PDT 24 Jun 06 01:37:48 PM PDT 24 14465725 ps
T1027 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2465578600 Jun 06 01:37:46 PM PDT 24 Jun 06 01:37:49 PM PDT 24 122516314 ps
T1028 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1968466012 Jun 06 01:37:46 PM PDT 24 Jun 06 01:37:50 PM PDT 24 150006223 ps
T1029 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3894925814 Jun 06 01:38:00 PM PDT 24 Jun 06 01:38:02 PM PDT 24 12779519 ps
T1030 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.850157591 Jun 06 01:37:16 PM PDT 24 Jun 06 01:37:21 PM PDT 24 1310604491 ps
T1031 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1267036017 Jun 06 01:37:58 PM PDT 24 Jun 06 01:38:01 PM PDT 24 13460242 ps
T119 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3392590797 Jun 06 01:37:19 PM PDT 24 Jun 06 01:37:22 PM PDT 24 1660559832 ps
T1032 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.221358604 Jun 06 01:37:07 PM PDT 24 Jun 06 01:37:09 PM PDT 24 111243220 ps
T1033 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1107880934 Jun 06 01:37:47 PM PDT 24 Jun 06 01:37:49 PM PDT 24 89762719 ps
T1034 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3939971243 Jun 06 01:37:57 PM PDT 24 Jun 06 01:38:00 PM PDT 24 97292287 ps
T1035 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3832979872 Jun 06 01:37:19 PM PDT 24 Jun 06 01:37:21 PM PDT 24 68336737 ps
T1036 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.4064163575 Jun 06 01:37:38 PM PDT 24 Jun 06 01:37:40 PM PDT 24 16149089 ps
T1037 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1151268912 Jun 06 01:37:15 PM PDT 24 Jun 06 01:37:17 PM PDT 24 23563009 ps
T1038 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2637270205 Jun 06 01:37:01 PM PDT 24 Jun 06 01:37:03 PM PDT 24 12008225 ps
T1039 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1982203035 Jun 06 01:37:50 PM PDT 24 Jun 06 01:37:54 PM PDT 24 140899089 ps
T1040 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2505403746 Jun 06 01:37:59 PM PDT 24 Jun 06 01:38:02 PM PDT 24 13467203 ps
T1041 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1142191025 Jun 06 01:37:38 PM PDT 24 Jun 06 01:37:41 PM PDT 24 68618956 ps
T1042 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.997275504 Jun 06 01:37:46 PM PDT 24 Jun 06 01:37:53 PM PDT 24 489498672 ps
T1043 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4275431737 Jun 06 01:37:18 PM PDT 24 Jun 06 01:37:22 PM PDT 24 58613693 ps
T1044 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4206183824 Jun 06 01:37:13 PM PDT 24 Jun 06 01:37:17 PM PDT 24 55975163 ps
T1045 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3112827084 Jun 06 01:37:05 PM PDT 24 Jun 06 01:37:18 PM PDT 24 756099361 ps
T1046 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1941385943 Jun 06 01:38:03 PM PDT 24 Jun 06 01:38:05 PM PDT 24 15880402 ps
T262 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3767439679 Jun 06 01:37:39 PM PDT 24 Jun 06 01:37:46 PM PDT 24 114115530 ps
T1047 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3756822703 Jun 06 01:37:45 PM PDT 24 Jun 06 01:37:51 PM PDT 24 270366489 ps
T1048 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4259947487 Jun 06 01:38:00 PM PDT 24 Jun 06 01:38:02 PM PDT 24 24510163 ps
T1049 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3653754757 Jun 06 01:37:01 PM PDT 24 Jun 06 01:37:05 PM PDT 24 93407768 ps
T1050 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1089639190 Jun 06 01:37:58 PM PDT 24 Jun 06 01:38:03 PM PDT 24 321791339 ps
T1051 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1104914238 Jun 06 01:37:28 PM PDT 24 Jun 06 01:37:29 PM PDT 24 34629930 ps
T1052 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3974228671 Jun 06 01:37:35 PM PDT 24 Jun 06 01:37:37 PM PDT 24 13826862 ps
T1053 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4234547270 Jun 06 01:37:56 PM PDT 24 Jun 06 01:37:58 PM PDT 24 22221780 ps
T1054 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3482874480 Jun 06 01:37:48 PM PDT 24 Jun 06 01:37:50 PM PDT 24 692359054 ps
T1055 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.280963729 Jun 06 01:38:02 PM PDT 24 Jun 06 01:38:07 PM PDT 24 126527985 ps
T1056 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.933507442 Jun 06 01:37:58 PM PDT 24 Jun 06 01:38:01 PM PDT 24 21307372 ps
T1057 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1725375503 Jun 06 01:37:08 PM PDT 24 Jun 06 01:37:11 PM PDT 24 58265998 ps
T1058 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2434607502 Jun 06 01:37:46 PM PDT 24 Jun 06 01:37:51 PM PDT 24 65519830 ps
T1059 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3326741354 Jun 06 01:37:59 PM PDT 24 Jun 06 01:38:04 PM PDT 24 43866652 ps
T1060 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1083848171 Jun 06 01:37:59 PM PDT 24 Jun 06 01:38:02 PM PDT 24 21781420 ps
T1061 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1023899434 Jun 06 01:37:18 PM PDT 24 Jun 06 01:37:23 PM PDT 24 127682951 ps
T1062 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3794722156 Jun 06 01:38:00 PM PDT 24 Jun 06 01:38:03 PM PDT 24 23459848 ps
T1063 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3085329257 Jun 06 01:37:17 PM PDT 24 Jun 06 01:37:19 PM PDT 24 19079481 ps
T1064 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1976706252 Jun 06 01:37:57 PM PDT 24 Jun 06 01:37:59 PM PDT 24 29291228 ps
T259 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3543782005 Jun 06 01:37:46 PM PDT 24 Jun 06 01:37:54 PM PDT 24 2294211406 ps
T1065 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3308444374 Jun 06 01:37:58 PM PDT 24 Jun 06 01:38:03 PM PDT 24 156221292 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1208967296 Jun 06 01:37:15 PM PDT 24 Jun 06 01:37:23 PM PDT 24 214621991 ps
T1067 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2048925362 Jun 06 01:37:46 PM PDT 24 Jun 06 01:37:49 PM PDT 24 52038329 ps
T1068 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2858699223 Jun 06 01:37:58 PM PDT 24 Jun 06 01:38:00 PM PDT 24 51601782 ps
T1069 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3836370751 Jun 06 01:37:46 PM PDT 24 Jun 06 01:37:49 PM PDT 24 119749355 ps
T1070 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1991985156 Jun 06 01:37:27 PM PDT 24 Jun 06 01:37:31 PM PDT 24 126542961 ps
T1071 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2313885816 Jun 06 01:37:57 PM PDT 24 Jun 06 01:37:58 PM PDT 24 14494105 ps
T1072 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2534880258 Jun 06 01:37:39 PM PDT 24 Jun 06 01:37:48 PM PDT 24 2881295008 ps
T1073 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2866709723 Jun 06 01:37:45 PM PDT 24 Jun 06 01:37:48 PM PDT 24 200419683 ps
T260 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3604026412 Jun 06 01:37:05 PM PDT 24 Jun 06 01:37:30 PM PDT 24 2066313796 ps
T1074 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2679938484 Jun 06 01:37:15 PM PDT 24 Jun 06 01:37:28 PM PDT 24 793968751 ps
T1075 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2918952997 Jun 06 01:37:09 PM PDT 24 Jun 06 01:37:12 PM PDT 24 45109156 ps
T1076 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2106448699 Jun 06 01:37:47 PM PDT 24 Jun 06 01:37:51 PM PDT 24 199386281 ps
T258 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3780390152 Jun 06 01:37:46 PM PDT 24 Jun 06 01:38:11 PM PDT 24 1132061564 ps
T1077 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3336885962 Jun 06 01:37:56 PM PDT 24 Jun 06 01:38:18 PM PDT 24 938105548 ps
T1078 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.658218636 Jun 06 01:37:15 PM PDT 24 Jun 06 01:37:19 PM PDT 24 174161662 ps
T1079 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2707210317 Jun 06 01:37:44 PM PDT 24 Jun 06 01:37:47 PM PDT 24 114903458 ps
T1080 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.987644896 Jun 06 01:37:19 PM PDT 24 Jun 06 01:37:54 PM PDT 24 2168915298 ps
T1081 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2030090624 Jun 06 01:37:19 PM PDT 24 Jun 06 01:37:21 PM PDT 24 11466022 ps
T1082 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1273431615 Jun 06 01:37:46 PM PDT 24 Jun 06 01:37:49 PM PDT 24 143921504 ps
T1083 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3309012516 Jun 06 01:37:46 PM PDT 24 Jun 06 01:37:48 PM PDT 24 15618413 ps
T1084 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.368351086 Jun 06 01:38:00 PM PDT 24 Jun 06 01:38:03 PM PDT 24 26414312 ps
T1085 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.89533708 Jun 06 01:37:44 PM PDT 24 Jun 06 01:37:48 PM PDT 24 478501628 ps
T1086 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2468735130 Jun 06 01:37:18 PM PDT 24 Jun 06 01:37:21 PM PDT 24 1167213469 ps
T1087 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.189102994 Jun 06 01:37:08 PM PDT 24 Jun 06 01:37:10 PM PDT 24 13931993 ps
T1088 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2203165611 Jun 06 01:37:16 PM PDT 24 Jun 06 01:37:52 PM PDT 24 22545049949 ps
T1089 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4159048425 Jun 06 01:38:03 PM PDT 24 Jun 06 01:38:07 PM PDT 24 65413266 ps
T1090 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.951670079 Jun 06 01:37:16 PM PDT 24 Jun 06 01:37:21 PM PDT 24 114478733 ps
T1091 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1886404264 Jun 06 01:37:46 PM PDT 24 Jun 06 01:37:48 PM PDT 24 105885106 ps
T1092 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4223847509 Jun 06 01:37:56 PM PDT 24 Jun 06 01:37:58 PM PDT 24 47368777 ps
T1093 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2698038941 Jun 06 01:37:14 PM PDT 24 Jun 06 01:37:17 PM PDT 24 70765247 ps
T1094 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3233886341 Jun 06 01:37:04 PM PDT 24 Jun 06 01:37:07 PM PDT 24 116460193 ps
T1095 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1280285885 Jun 06 01:37:27 PM PDT 24 Jun 06 01:37:31 PM PDT 24 96738733 ps
T1096 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4181596529 Jun 06 01:37:24 PM PDT 24 Jun 06 01:37:28 PM PDT 24 754472384 ps
T1097 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1862700851 Jun 06 01:37:08 PM PDT 24 Jun 06 01:37:10 PM PDT 24 35734592 ps
T1098 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.449313807 Jun 06 01:37:46 PM PDT 24 Jun 06 01:38:09 PM PDT 24 3445477101 ps
T1099 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2941981054 Jun 06 01:37:57 PM PDT 24 Jun 06 01:38:00 PM PDT 24 55950592 ps
T1100 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1942519961 Jun 06 01:37:56 PM PDT 24 Jun 06 01:38:02 PM PDT 24 894959736 ps
T1101 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3142350452 Jun 06 01:37:19 PM PDT 24 Jun 06 01:37:22 PM PDT 24 56488798 ps

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1201017270
Short name T2
Test name
Test status
Simulation time 18225541297 ps
CPU time 197.45 seconds
Started Jun 06 02:41:58 PM PDT 24
Finished Jun 06 02:45:19 PM PDT 24
Peak memory 265656 kb
Host smart-29a0d20d-2dba-40d4-9f3d-3990e6106aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201017270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1201017270
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2700800552
Short name T10
Test name
Test status
Simulation time 56301604057 ps
CPU time 200.07 seconds
Started Jun 06 02:42:09 PM PDT 24
Finished Jun 06 02:45:32 PM PDT 24
Peak memory 249652 kb
Host smart-6e52e911-d075-4722-9298-316133fea98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700800552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2700800552
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2977352929
Short name T147
Test name
Test status
Simulation time 50223943670 ps
CPU time 484.03 seconds
Started Jun 06 02:44:11 PM PDT 24
Finished Jun 06 02:52:18 PM PDT 24
Peak memory 255836 kb
Host smart-9d55205a-1d3f-4371-8f86-7f08ed4ffb18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977352929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2977352929
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.360334859
Short name T90
Test name
Test status
Simulation time 4827189046 ps
CPU time 20.15 seconds
Started Jun 06 01:37:06 PM PDT 24
Finished Jun 06 01:37:26 PM PDT 24
Peak memory 216176 kb
Host smart-5bc00dd3-70f1-483d-99ea-f884f3745b2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360334859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.360334859
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2282820346
Short name T26
Test name
Test status
Simulation time 5009643993 ps
CPU time 113.72 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:44:03 PM PDT 24
Peak memory 265824 kb
Host smart-6436a07e-43a3-415d-8eb5-09250a5f7492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282820346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2282820346
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4149983786
Short name T8
Test name
Test status
Simulation time 6576164269 ps
CPU time 76.94 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:43:27 PM PDT 24
Peak memory 249608 kb
Host smart-1492e239-a7b3-4616-b727-e35addc5839a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149983786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4149983786
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2889213600
Short name T193
Test name
Test status
Simulation time 69921021730 ps
CPU time 795.62 seconds
Started Jun 06 02:42:10 PM PDT 24
Finished Jun 06 02:55:28 PM PDT 24
Peak memory 282540 kb
Host smart-84049b43-1572-4b8f-931e-107c2d0a3974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889213600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2889213600
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3285614565
Short name T56
Test name
Test status
Simulation time 36676951 ps
CPU time 0.72 seconds
Started Jun 06 02:41:51 PM PDT 24
Finished Jun 06 02:41:55 PM PDT 24
Peak memory 216180 kb
Host smart-b036a80d-8f17-4780-aeb3-5109655688c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285614565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3285614565
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3062734614
Short name T24
Test name
Test status
Simulation time 62798024923 ps
CPU time 601.06 seconds
Started Jun 06 02:42:50 PM PDT 24
Finished Jun 06 02:52:53 PM PDT 24
Peak memory 273508 kb
Host smart-d6f4ab6b-7206-419b-99c2-0ec7fca120cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062734614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3062734614
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3963994942
Short name T129
Test name
Test status
Simulation time 22790210008 ps
CPU time 188.19 seconds
Started Jun 06 02:43:07 PM PDT 24
Finished Jun 06 02:46:17 PM PDT 24
Peak memory 267056 kb
Host smart-08fbcea2-f6ce-44b2-a378-5d2b8a43f62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963994942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3963994942
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2831154566
Short name T229
Test name
Test status
Simulation time 530484063544 ps
CPU time 1303.17 seconds
Started Jun 06 02:42:25 PM PDT 24
Finished Jun 06 03:04:10 PM PDT 24
Peak memory 265732 kb
Host smart-6a600002-dfd4-4967-803f-e7533c2194d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831154566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2831154566
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1672107488
Short name T54
Test name
Test status
Simulation time 296138384 ps
CPU time 0.96 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:42:12 PM PDT 24
Peak memory 234976 kb
Host smart-29ee44e4-f178-40a2-abcf-fe469f8f3c5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672107488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1672107488
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1192567405
Short name T105
Test name
Test status
Simulation time 4021930486 ps
CPU time 20.22 seconds
Started Jun 06 02:44:12 PM PDT 24
Finished Jun 06 02:44:34 PM PDT 24
Peak memory 235136 kb
Host smart-0b29dab9-d8c0-4f2b-9141-bddfe3768dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192567405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1192567405
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4052650971
Short name T97
Test name
Test status
Simulation time 141016599 ps
CPU time 3.33 seconds
Started Jun 06 01:37:18 PM PDT 24
Finished Jun 06 01:37:22 PM PDT 24
Peak memory 215844 kb
Host smart-8b0f11d3-ce48-4885-94c7-0950a84f0a66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052650971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4
052650971
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.557908296
Short name T18
Test name
Test status
Simulation time 32148644361 ps
CPU time 224.17 seconds
Started Jun 06 02:43:42 PM PDT 24
Finished Jun 06 02:47:28 PM PDT 24
Peak memory 257504 kb
Host smart-80853153-2aa2-472b-ac47-6265b4a43e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557908296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.557908296
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4198985154
Short name T38
Test name
Test status
Simulation time 487019530781 ps
CPU time 1173.28 seconds
Started Jun 06 02:43:53 PM PDT 24
Finished Jun 06 03:03:30 PM PDT 24
Peak memory 268392 kb
Host smart-08abb405-e834-4951-ba59-176b64cd84b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198985154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4198985154
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2162546184
Short name T106
Test name
Test status
Simulation time 313878267 ps
CPU time 21.66 seconds
Started Jun 06 01:37:04 PM PDT 24
Finished Jun 06 01:37:26 PM PDT 24
Peak memory 215728 kb
Host smart-25296a6f-54f1-4431-8a2a-66bb3593c72b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162546184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2162546184
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2051911038
Short name T161
Test name
Test status
Simulation time 9249883730 ps
CPU time 135.39 seconds
Started Jun 06 02:42:30 PM PDT 24
Finished Jun 06 02:44:48 PM PDT 24
Peak memory 249112 kb
Host smart-bcb65719-d392-45e2-a8ee-3d80ada89b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051911038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2051911038
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.188902272
Short name T62
Test name
Test status
Simulation time 37489217069 ps
CPU time 81.52 seconds
Started Jun 06 02:42:33 PM PDT 24
Finished Jun 06 02:43:58 PM PDT 24
Peak memory 241156 kb
Host smart-76d21c0f-419e-4287-9545-dd738a5328e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188902272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.188902272
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3577918524
Short name T19
Test name
Test status
Simulation time 16566671 ps
CPU time 1.01 seconds
Started Jun 06 02:42:18 PM PDT 24
Finished Jun 06 02:42:22 PM PDT 24
Peak memory 217736 kb
Host smart-72207e2d-9fa6-419c-a315-bb9144d9e024
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577918524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3577918524
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2050271438
Short name T120
Test name
Test status
Simulation time 19830053782 ps
CPU time 124.37 seconds
Started Jun 06 02:43:13 PM PDT 24
Finished Jun 06 02:45:20 PM PDT 24
Peak memory 251360 kb
Host smart-c8b25b68-e0db-4fc7-8a2f-cffccf1abb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050271438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2050271438
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1314238849
Short name T233
Test name
Test status
Simulation time 25730106436 ps
CPU time 216.1 seconds
Started Jun 06 02:41:55 PM PDT 24
Finished Jun 06 02:45:35 PM PDT 24
Peak memory 273084 kb
Host smart-92a8f56e-f985-4ceb-a564-99e3357b3719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314238849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1314238849
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2650138660
Short name T27
Test name
Test status
Simulation time 39852665533 ps
CPU time 144.37 seconds
Started Jun 06 02:42:58 PM PDT 24
Finished Jun 06 02:45:24 PM PDT 24
Peak memory 249248 kb
Host smart-c4361c05-0177-4f7d-b8b9-93d1d118eab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650138660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2650138660
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1322544200
Short name T55
Test name
Test status
Simulation time 5886182957 ps
CPU time 48.45 seconds
Started Jun 06 02:42:59 PM PDT 24
Finished Jun 06 02:43:49 PM PDT 24
Peak memory 240400 kb
Host smart-ee4af85f-1e54-4770-aaee-883bb57d810d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322544200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1322544200
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3604026412
Short name T260
Test name
Test status
Simulation time 2066313796 ps
CPU time 23.74 seconds
Started Jun 06 01:37:05 PM PDT 24
Finished Jun 06 01:37:30 PM PDT 24
Peak memory 215940 kb
Host smart-88ed705b-5134-4a5e-a725-e760dfead482
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604026412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3604026412
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4147921010
Short name T148
Test name
Test status
Simulation time 35654892955 ps
CPU time 360.11 seconds
Started Jun 06 02:43:14 PM PDT 24
Finished Jun 06 02:49:17 PM PDT 24
Peak memory 273860 kb
Host smart-8dbab694-2f39-4cb5-84a0-b0028f476184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147921010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4147921010
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1084188660
Short name T52
Test name
Test status
Simulation time 15245274 ps
CPU time 0.72 seconds
Started Jun 06 02:42:22 PM PDT 24
Finished Jun 06 02:42:24 PM PDT 24
Peak memory 205212 kb
Host smart-edb1e4fb-5192-4a8a-a20e-6caebb2ff585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084188660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1084188660
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3126054103
Short name T220
Test name
Test status
Simulation time 181353353653 ps
CPU time 342.17 seconds
Started Jun 06 02:44:14 PM PDT 24
Finished Jun 06 02:49:58 PM PDT 24
Peak memory 249444 kb
Host smart-75bf9187-3904-4a9f-86db-70e5e486db7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126054103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3126054103
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2112638230
Short name T182
Test name
Test status
Simulation time 55222372147 ps
CPU time 444.47 seconds
Started Jun 06 02:42:29 PM PDT 24
Finished Jun 06 02:49:55 PM PDT 24
Peak memory 250376 kb
Host smart-46fb67a9-3b83-4bae-88eb-bde0c7b9d165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112638230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2112638230
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.932197507
Short name T31
Test name
Test status
Simulation time 3168297561 ps
CPU time 77.59 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:43:28 PM PDT 24
Peak memory 264816 kb
Host smart-5e4c0d78-2598-433f-aece-0df3561d3089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932197507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.932197507
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1786149542
Short name T76
Test name
Test status
Simulation time 2947685228 ps
CPU time 11.24 seconds
Started Jun 06 02:43:13 PM PDT 24
Finished Jun 06 02:43:27 PM PDT 24
Peak memory 216332 kb
Host smart-0a1545c7-a0d2-41b5-b2d4-fbf59d92f34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786149542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1786149542
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3900428668
Short name T570
Test name
Test status
Simulation time 5365264416 ps
CPU time 22.32 seconds
Started Jun 06 02:42:43 PM PDT 24
Finished Jun 06 02:43:08 PM PDT 24
Peak memory 234716 kb
Host smart-bf9b91e9-8be2-46c5-a7d7-23521cd26d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900428668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3900428668
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1504193873
Short name T189
Test name
Test status
Simulation time 57319366583 ps
CPU time 498.93 seconds
Started Jun 06 02:42:43 PM PDT 24
Finished Jun 06 02:51:04 PM PDT 24
Peak memory 268008 kb
Host smart-a73a4007-74f5-4869-9963-228d56c648ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504193873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1504193873
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2057287397
Short name T185
Test name
Test status
Simulation time 236591902078 ps
CPU time 458.16 seconds
Started Jun 06 02:43:43 PM PDT 24
Finished Jun 06 02:51:24 PM PDT 24
Peak memory 249172 kb
Host smart-33e31933-5b94-4a81-84e2-b841136d4b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057287397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2057287397
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1789701562
Short name T84
Test name
Test status
Simulation time 8081850222 ps
CPU time 12.78 seconds
Started Jun 06 02:41:48 PM PDT 24
Finished Jun 06 02:42:05 PM PDT 24
Peak memory 232800 kb
Host smart-c9319698-0b6d-42ac-b982-184f0cdc3e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789701562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1789701562
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2328259878
Short name T101
Test name
Test status
Simulation time 453348468 ps
CPU time 4.34 seconds
Started Jun 06 01:37:04 PM PDT 24
Finished Jun 06 01:37:09 PM PDT 24
Peak memory 216064 kb
Host smart-2ba9475a-b210-43fd-9480-a61ae1317f0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328259878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
328259878
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1684141183
Short name T265
Test name
Test status
Simulation time 64379398213 ps
CPU time 168.31 seconds
Started Jun 06 02:42:46 PM PDT 24
Finished Jun 06 02:45:37 PM PDT 24
Peak memory 255180 kb
Host smart-d4315c80-d8e9-4c32-ac1f-a1d17d5cc5b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684141183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1684141183
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2112365453
Short name T232
Test name
Test status
Simulation time 225108209607 ps
CPU time 289.31 seconds
Started Jun 06 02:43:07 PM PDT 24
Finished Jun 06 02:47:59 PM PDT 24
Peak memory 269080 kb
Host smart-992cb6d2-7916-4d95-af36-72b6d0fb0fd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112365453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2112365453
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3481142241
Short name T235
Test name
Test status
Simulation time 24135041473 ps
CPU time 102.53 seconds
Started Jun 06 02:43:23 PM PDT 24
Finished Jun 06 02:45:07 PM PDT 24
Peak memory 264200 kb
Host smart-733d6c5e-c9ec-4486-8661-f17834b5c96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481142241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3481142241
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1882945906
Short name T594
Test name
Test status
Simulation time 221921105 ps
CPU time 2.76 seconds
Started Jun 06 02:41:53 PM PDT 24
Finished Jun 06 02:42:00 PM PDT 24
Peak memory 232716 kb
Host smart-c8e3d359-b9bb-497b-b6b2-7e1d6870cc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882945906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1882945906
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3780390152
Short name T258
Test name
Test status
Simulation time 1132061564 ps
CPU time 23.47 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:38:11 PM PDT 24
Peak memory 217132 kb
Host smart-fb998c80-ab14-4580-9f36-1529dce7a3d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780390152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3780390152
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_intercept.300250429
Short name T202
Test name
Test status
Simulation time 1069711894 ps
CPU time 6.16 seconds
Started Jun 06 02:41:56 PM PDT 24
Finished Jun 06 02:42:05 PM PDT 24
Peak memory 232752 kb
Host smart-6d36f668-4bfd-4bb9-88f7-d91ee52494d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300250429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.300250429
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1561352459
Short name T446
Test name
Test status
Simulation time 130036505484 ps
CPU time 143.7 seconds
Started Jun 06 02:42:25 PM PDT 24
Finished Jun 06 02:44:50 PM PDT 24
Peak memory 250180 kb
Host smart-9f75ac50-6e28-464e-b0f8-5eaf303576b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561352459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1561352459
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3174208754
Short name T794
Test name
Test status
Simulation time 124877893319 ps
CPU time 292.04 seconds
Started Jun 06 02:42:38 PM PDT 24
Finished Jun 06 02:47:32 PM PDT 24
Peak memory 253284 kb
Host smart-e08aeb08-8be2-40e6-b08a-bbb44369f508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174208754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3174208754
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3338876644
Short name T252
Test name
Test status
Simulation time 9469188485 ps
CPU time 19.08 seconds
Started Jun 06 02:42:33 PM PDT 24
Finished Jun 06 02:42:56 PM PDT 24
Peak memory 240352 kb
Host smart-ef484fc8-e47b-4392-84a8-a0bad6620123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338876644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3338876644
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3113471550
Short name T812
Test name
Test status
Simulation time 7548334393 ps
CPU time 26.8 seconds
Started Jun 06 02:42:22 PM PDT 24
Finished Jun 06 02:42:50 PM PDT 24
Peak memory 224588 kb
Host smart-ec493c26-fe5a-4775-925a-8a4bf9ff1d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113471550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3113471550
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2345021129
Short name T311
Test name
Test status
Simulation time 1341921147 ps
CPU time 17.57 seconds
Started Jun 06 02:42:43 PM PDT 24
Finished Jun 06 02:43:04 PM PDT 24
Peak memory 249840 kb
Host smart-41c3ede4-5709-4074-ba98-b1e4cedaf0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345021129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2345021129
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3624732513
Short name T225
Test name
Test status
Simulation time 80653587489 ps
CPU time 198.22 seconds
Started Jun 06 02:42:04 PM PDT 24
Finished Jun 06 02:45:25 PM PDT 24
Peak memory 268380 kb
Host smart-1e662642-709f-49a8-a923-4e5445bbf163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624732513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3624732513
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1476880276
Short name T176
Test name
Test status
Simulation time 22636385461 ps
CPU time 215.59 seconds
Started Jun 06 02:42:45 PM PDT 24
Finished Jun 06 02:46:23 PM PDT 24
Peak memory 255896 kb
Host smart-d4698114-fd9c-46a2-a083-e26d6cb12e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476880276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1476880276
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3791555447
Short name T331
Test name
Test status
Simulation time 8351869328 ps
CPU time 27.08 seconds
Started Jun 06 02:42:57 PM PDT 24
Finished Jun 06 02:43:26 PM PDT 24
Peak memory 216416 kb
Host smart-20181b39-530f-42d3-93ad-6a7856afd98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791555447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3791555447
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.608651692
Short name T241
Test name
Test status
Simulation time 99407124033 ps
CPU time 968.71 seconds
Started Jun 06 02:42:59 PM PDT 24
Finished Jun 06 02:59:10 PM PDT 24
Peak memory 266540 kb
Host smart-cf0543d4-4de6-4d76-a8f5-0c87e49ddd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608651692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.608651692
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.768642001
Short name T133
Test name
Test status
Simulation time 171909469622 ps
CPU time 259.57 seconds
Started Jun 06 02:42:59 PM PDT 24
Finished Jun 06 02:47:20 PM PDT 24
Peak memory 257504 kb
Host smart-c35f3723-108a-4440-a9a8-5b7af6ea627f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768642001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.768642001
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2616088176
Short name T226
Test name
Test status
Simulation time 11625259465 ps
CPU time 177.63 seconds
Started Jun 06 02:43:14 PM PDT 24
Finished Jun 06 02:46:15 PM PDT 24
Peak memory 251948 kb
Host smart-8de60eeb-98b6-463b-bdc4-29ba835a90fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616088176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2616088176
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3068591858
Short name T218
Test name
Test status
Simulation time 259196001228 ps
CPU time 646.26 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:54:34 PM PDT 24
Peak memory 257588 kb
Host smart-683490e6-761f-45ca-a5dc-e9d2d4baf23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068591858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3068591858
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3726402714
Short name T72
Test name
Test status
Simulation time 151738666 ps
CPU time 1.38 seconds
Started Jun 06 01:37:03 PM PDT 24
Finished Jun 06 01:37:07 PM PDT 24
Peak memory 207500 kb
Host smart-827856aa-d5c5-406a-aa4d-5f55b320d294
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726402714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3726402714
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3747883299
Short name T91
Test name
Test status
Simulation time 146524552 ps
CPU time 3.08 seconds
Started Jun 06 01:37:04 PM PDT 24
Finished Jun 06 01:37:08 PM PDT 24
Peak memory 215948 kb
Host smart-7e99ad24-9114-41c9-8315-ee54e6a7a044
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747883299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
747883299
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4237000305
Short name T118
Test name
Test status
Simulation time 972521052 ps
CPU time 35.14 seconds
Started Jun 06 01:37:08 PM PDT 24
Finished Jun 06 01:37:44 PM PDT 24
Peak memory 207572 kb
Host smart-780e78a5-7021-4b21-9bf9-86a52af3978a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237000305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4237000305
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2254110939
Short name T86
Test name
Test status
Simulation time 46870009 ps
CPU time 1.67 seconds
Started Jun 06 01:37:03 PM PDT 24
Finished Jun 06 01:37:06 PM PDT 24
Peak memory 215768 kb
Host smart-881fe655-dfd6-4cc8-8072-691039d41ef9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254110939 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2254110939
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3233886341
Short name T1094
Test name
Test status
Simulation time 116460193 ps
CPU time 2.64 seconds
Started Jun 06 01:37:04 PM PDT 24
Finished Jun 06 01:37:07 PM PDT 24
Peak memory 215732 kb
Host smart-e0f3e398-029d-47ca-8dea-e7807e641efb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233886341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
233886341
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2637270205
Short name T1038
Test name
Test status
Simulation time 12008225 ps
CPU time 0.7 seconds
Started Jun 06 01:37:01 PM PDT 24
Finished Jun 06 01:37:03 PM PDT 24
Peak memory 204352 kb
Host smart-db14b9a1-ee74-44ff-985b-2ffae772266a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637270205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
637270205
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3653754757
Short name T1049
Test name
Test status
Simulation time 93407768 ps
CPU time 1.84 seconds
Started Jun 06 01:37:01 PM PDT 24
Finished Jun 06 01:37:05 PM PDT 24
Peak memory 215864 kb
Host smart-a46056ca-14f5-40bc-b352-ccf7e130d769
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653754757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3653754757
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3820537017
Short name T982
Test name
Test status
Simulation time 11599963 ps
CPU time 0.66 seconds
Started Jun 06 01:37:00 PM PDT 24
Finished Jun 06 01:37:01 PM PDT 24
Peak memory 204320 kb
Host smart-5d4dcb25-f089-4ca5-8d66-2b0c7801537c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820537017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3820537017
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2918952997
Short name T1075
Test name
Test status
Simulation time 45109156 ps
CPU time 2.61 seconds
Started Jun 06 01:37:09 PM PDT 24
Finished Jun 06 01:37:12 PM PDT 24
Peak memory 216132 kb
Host smart-900d498d-111d-42cf-97b8-1858bdf2bdbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918952997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2918952997
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3971501253
Short name T983
Test name
Test status
Simulation time 219136544 ps
CPU time 14.42 seconds
Started Jun 06 01:37:06 PM PDT 24
Finished Jun 06 01:37:21 PM PDT 24
Peak memory 215776 kb
Host smart-024512f2-7230-44eb-824a-6f078997acd6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971501253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3971501253
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3112827084
Short name T1045
Test name
Test status
Simulation time 756099361 ps
CPU time 12.39 seconds
Started Jun 06 01:37:05 PM PDT 24
Finished Jun 06 01:37:18 PM PDT 24
Peak memory 207500 kb
Host smart-0d1e5674-928f-4de3-82af-80806cba2911
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112827084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3112827084
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2546614252
Short name T75
Test name
Test status
Simulation time 25494658 ps
CPU time 1.34 seconds
Started Jun 06 01:37:07 PM PDT 24
Finished Jun 06 01:37:09 PM PDT 24
Peak memory 207480 kb
Host smart-09264d88-82ad-4838-b815-1360c34c4168
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546614252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2546614252
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1232320290
Short name T87
Test name
Test status
Simulation time 238279443 ps
CPU time 2.9 seconds
Started Jun 06 01:37:08 PM PDT 24
Finished Jun 06 01:37:12 PM PDT 24
Peak memory 217356 kb
Host smart-e50044dc-675f-4f80-a946-736562fb9ff4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232320290 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1232320290
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2791069509
Short name T117
Test name
Test status
Simulation time 481706867 ps
CPU time 2.24 seconds
Started Jun 06 01:37:07 PM PDT 24
Finished Jun 06 01:37:10 PM PDT 24
Peak memory 215780 kb
Host smart-0a8dc6d0-6bc8-4830-806e-80e67b0c4f4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791069509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
791069509
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.189102994
Short name T1087
Test name
Test status
Simulation time 13931993 ps
CPU time 0.72 seconds
Started Jun 06 01:37:08 PM PDT 24
Finished Jun 06 01:37:10 PM PDT 24
Peak memory 204036 kb
Host smart-a10bf800-7a19-4ae5-8a55-6992ccd57161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189102994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.189102994
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1862700851
Short name T1097
Test name
Test status
Simulation time 35734592 ps
CPU time 1.27 seconds
Started Jun 06 01:37:08 PM PDT 24
Finished Jun 06 01:37:10 PM PDT 24
Peak memory 215848 kb
Host smart-6effc195-a0b2-44b3-addb-46c067484c3d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862700851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1862700851
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.219248481
Short name T994
Test name
Test status
Simulation time 38909696 ps
CPU time 0.65 seconds
Started Jun 06 01:37:18 PM PDT 24
Finished Jun 06 01:37:19 PM PDT 24
Peak memory 203976 kb
Host smart-ab00f9ac-edef-4713-bca7-fb5301949213
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219248481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.219248481
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2082794711
Short name T154
Test name
Test status
Simulation time 227749464 ps
CPU time 4.68 seconds
Started Jun 06 01:37:12 PM PDT 24
Finished Jun 06 01:37:17 PM PDT 24
Peak memory 215636 kb
Host smart-1ca48cc0-525e-4d55-8a9d-e4599cf39002
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082794711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2082794711
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4065672527
Short name T1010
Test name
Test status
Simulation time 90541547 ps
CPU time 2.96 seconds
Started Jun 06 01:37:38 PM PDT 24
Finished Jun 06 01:37:41 PM PDT 24
Peak memory 217044 kb
Host smart-ae724e05-5b39-4f5f-bacd-4a512ba720cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065672527 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.4065672527
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2106448699
Short name T1076
Test name
Test status
Simulation time 199386281 ps
CPU time 2.44 seconds
Started Jun 06 01:37:47 PM PDT 24
Finished Jun 06 01:37:51 PM PDT 24
Peak memory 215748 kb
Host smart-4d5ab5e6-9984-452e-862d-7b983dbf57a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106448699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2106448699
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.4064163575
Short name T1036
Test name
Test status
Simulation time 16149089 ps
CPU time 0.7 seconds
Started Jun 06 01:37:38 PM PDT 24
Finished Jun 06 01:37:40 PM PDT 24
Peak memory 204304 kb
Host smart-ead55313-1394-4381-8c96-fa799298d17d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064163575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
4064163575
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2048925362
Short name T1067
Test name
Test status
Simulation time 52038329 ps
CPU time 1.76 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:49 PM PDT 24
Peak memory 215740 kb
Host smart-be98f210-d182-49a3-9b4c-d01636021559
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048925362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2048925362
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3102333204
Short name T98
Test name
Test status
Simulation time 494932018 ps
CPU time 4.47 seconds
Started Jun 06 01:37:55 PM PDT 24
Finished Jun 06 01:38:00 PM PDT 24
Peak memory 215952 kb
Host smart-e300e2ee-1fcd-4797-a805-8047b604273f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102333204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3102333204
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2534880258
Short name T1072
Test name
Test status
Simulation time 2881295008 ps
CPU time 7.35 seconds
Started Jun 06 01:37:39 PM PDT 24
Finished Jun 06 01:37:48 PM PDT 24
Peak memory 215876 kb
Host smart-1f5237a7-e8bc-4b30-802b-6190bb9bfa66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534880258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2534880258
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.511871895
Short name T1025
Test name
Test status
Simulation time 89070476 ps
CPU time 1.58 seconds
Started Jun 06 01:37:45 PM PDT 24
Finished Jun 06 01:37:48 PM PDT 24
Peak memory 215856 kb
Host smart-481a7025-8b30-4303-8ddb-6f81f99cd6fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511871895 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.511871895
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1517609380
Short name T109
Test name
Test status
Simulation time 469498569 ps
CPU time 2.77 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:49 PM PDT 24
Peak memory 207212 kb
Host smart-3f433431-d346-41c5-a14e-ab3e3589ea69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517609380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1517609380
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3974228671
Short name T1052
Test name
Test status
Simulation time 13826862 ps
CPU time 0.69 seconds
Started Jun 06 01:37:35 PM PDT 24
Finished Jun 06 01:37:37 PM PDT 24
Peak memory 204040 kb
Host smart-1c72b7c5-8a03-48a3-9fa8-4680b12a0c3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974228671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3974228671
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1707916370
Short name T1024
Test name
Test status
Simulation time 60574331 ps
CPU time 3.84 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:50 PM PDT 24
Peak memory 215196 kb
Host smart-12d9094d-1058-46c0-b3fd-78442397efbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707916370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1707916370
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.529717624
Short name T99
Test name
Test status
Simulation time 274747572 ps
CPU time 3.99 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:52 PM PDT 24
Peak memory 215972 kb
Host smart-6ce5a846-ba0f-475c-9f03-196c11e4828d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529717624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.529717624
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2014711913
Short name T104
Test name
Test status
Simulation time 1870949284 ps
CPU time 21.77 seconds
Started Jun 06 01:37:36 PM PDT 24
Finished Jun 06 01:37:58 PM PDT 24
Peak memory 216076 kb
Host smart-c70b0b08-ceba-411b-8e68-22d626d169b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014711913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2014711913
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1982203035
Short name T1039
Test name
Test status
Simulation time 140899089 ps
CPU time 3.44 seconds
Started Jun 06 01:37:50 PM PDT 24
Finished Jun 06 01:37:54 PM PDT 24
Peak memory 217432 kb
Host smart-b59f7dce-cc9f-4bb2-abba-4685b857309f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982203035 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1982203035
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.89533708
Short name T1085
Test name
Test status
Simulation time 478501628 ps
CPU time 2.88 seconds
Started Jun 06 01:37:44 PM PDT 24
Finished Jun 06 01:37:48 PM PDT 24
Peak memory 215728 kb
Host smart-2dade530-c4fa-4f1e-8d3c-20b5e17965f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89533708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.89533708
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3309012516
Short name T1083
Test name
Test status
Simulation time 15618413 ps
CPU time 0.69 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:48 PM PDT 24
Peak memory 203976 kb
Host smart-842c2cc3-3eae-4f6d-a9f3-1c2427be622c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309012516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3309012516
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1968466012
Short name T1028
Test name
Test status
Simulation time 150006223 ps
CPU time 2.13 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:50 PM PDT 24
Peak memory 215668 kb
Host smart-7166d44d-89a5-47e6-89b9-f8a6a4682004
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968466012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1968466012
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3756822703
Short name T1047
Test name
Test status
Simulation time 270366489 ps
CPU time 4.88 seconds
Started Jun 06 01:37:45 PM PDT 24
Finished Jun 06 01:37:51 PM PDT 24
Peak memory 215892 kb
Host smart-b5ad844d-45ba-4ac2-ba55-98239aa81ef8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756822703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3756822703
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.830678090
Short name T143
Test name
Test status
Simulation time 7112331638 ps
CPU time 13.1 seconds
Started Jun 06 01:37:45 PM PDT 24
Finished Jun 06 01:37:59 PM PDT 24
Peak memory 215800 kb
Host smart-df42464b-64e7-4012-b424-15cfecf1c18b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830678090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.830678090
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.645540883
Short name T103
Test name
Test status
Simulation time 28626655 ps
CPU time 2.01 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:49 PM PDT 24
Peak memory 215836 kb
Host smart-fc3d9fa8-ae5a-4a3d-ad77-5e2ba39d52ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645540883 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.645540883
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3482874480
Short name T1054
Test name
Test status
Simulation time 692359054 ps
CPU time 1.3 seconds
Started Jun 06 01:37:48 PM PDT 24
Finished Jun 06 01:37:50 PM PDT 24
Peak memory 207596 kb
Host smart-ee382743-9a68-4b49-9da0-2749dd7012d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482874480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3482874480
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1934146423
Short name T998
Test name
Test status
Simulation time 52613248 ps
CPU time 0.72 seconds
Started Jun 06 01:37:48 PM PDT 24
Finished Jun 06 01:37:50 PM PDT 24
Peak memory 204352 kb
Host smart-ace8a288-cacd-4670-b9d4-fb57110eae67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934146423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1934146423
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2434607502
Short name T1058
Test name
Test status
Simulation time 65519830 ps
CPU time 3.85 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:51 PM PDT 24
Peak memory 215680 kb
Host smart-31169e53-63e5-472d-bd78-5b768d9f0ff0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434607502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2434607502
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1273431615
Short name T1082
Test name
Test status
Simulation time 143921504 ps
CPU time 2.09 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:49 PM PDT 24
Peak memory 215580 kb
Host smart-a970a787-a156-4774-b22d-989a122d86c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273431615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1273431615
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4070900050
Short name T1000
Test name
Test status
Simulation time 284571149 ps
CPU time 2.81 seconds
Started Jun 06 01:37:44 PM PDT 24
Finished Jun 06 01:37:49 PM PDT 24
Peak memory 217108 kb
Host smart-5c59c3d7-19bb-47a5-9ca3-3a909158e8dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070900050 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4070900050
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.122578124
Short name T980
Test name
Test status
Simulation time 95225681 ps
CPU time 1.82 seconds
Started Jun 06 01:37:47 PM PDT 24
Finished Jun 06 01:37:50 PM PDT 24
Peak memory 215776 kb
Host smart-101de31e-d7d6-401a-a819-3a48632d617b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122578124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.122578124
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1886404264
Short name T1091
Test name
Test status
Simulation time 105885106 ps
CPU time 0.71 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:48 PM PDT 24
Peak memory 204040 kb
Host smart-ed7fe6e1-dd47-46d0-bfde-a2644f3f8044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886404264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1886404264
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1295395391
Short name T137
Test name
Test status
Simulation time 109421797 ps
CPU time 3.57 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:51 PM PDT 24
Peak memory 215404 kb
Host smart-ab8a1c7e-d518-4a2b-a305-6834bfba3792
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295395391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1295395391
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2866709723
Short name T1073
Test name
Test status
Simulation time 200419683 ps
CPU time 1.64 seconds
Started Jun 06 01:37:45 PM PDT 24
Finished Jun 06 01:37:48 PM PDT 24
Peak memory 216772 kb
Host smart-f230ca4b-1345-4879-94a5-93e30f3ed546
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866709723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2866709723
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3543782005
Short name T259
Test name
Test status
Simulation time 2294211406 ps
CPU time 7.86 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:54 PM PDT 24
Peak memory 215760 kb
Host smart-689525e0-533d-4b46-8f83-91bfd829fd6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543782005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3543782005
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2707210317
Short name T1079
Test name
Test status
Simulation time 114903458 ps
CPU time 1.7 seconds
Started Jun 06 01:37:44 PM PDT 24
Finished Jun 06 01:37:47 PM PDT 24
Peak memory 216800 kb
Host smart-384379a6-07b0-4df2-b745-0a873fb07407
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707210317 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2707210317
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3836370751
Short name T1069
Test name
Test status
Simulation time 119749355 ps
CPU time 1.98 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:49 PM PDT 24
Peak memory 215748 kb
Host smart-18ed09a7-36e7-4a2a-8f01-3f627ca1695d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836370751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3836370751
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1677780209
Short name T1026
Test name
Test status
Simulation time 14465725 ps
CPU time 0.7 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:48 PM PDT 24
Peak memory 204004 kb
Host smart-e08249f7-26f6-4f55-b0d1-bdc32e0e2998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677780209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1677780209
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1158752608
Short name T145
Test name
Test status
Simulation time 143876295 ps
CPU time 3.27 seconds
Started Jun 06 01:37:47 PM PDT 24
Finished Jun 06 01:37:51 PM PDT 24
Peak memory 215772 kb
Host smart-f0e8eb10-3867-4e99-bd69-9419c6b537c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158752608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1158752608
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.997275504
Short name T1042
Test name
Test status
Simulation time 489498672 ps
CPU time 5.04 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:53 PM PDT 24
Peak memory 220048 kb
Host smart-246dbb27-6337-4f53-86ef-1d4d82cd1a37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997275504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.997275504
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.449313807
Short name T1098
Test name
Test status
Simulation time 3445477101 ps
CPU time 21.66 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:38:09 PM PDT 24
Peak memory 215840 kb
Host smart-c2fad053-bef4-491e-a6e8-54e30dee262d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449313807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.449313807
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.433016655
Short name T1020
Test name
Test status
Simulation time 52230936 ps
CPU time 3.3 seconds
Started Jun 06 01:38:02 PM PDT 24
Finished Jun 06 01:38:06 PM PDT 24
Peak memory 218336 kb
Host smart-bc90519f-7625-4b3c-ba7c-ceb8e385aac1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433016655 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.433016655
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2465578600
Short name T1027
Test name
Test status
Simulation time 122516314 ps
CPU time 1.87 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:37:49 PM PDT 24
Peak memory 215744 kb
Host smart-4a270b64-d945-4974-a493-2f49a9f9712d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465578600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2465578600
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1107880934
Short name T1033
Test name
Test status
Simulation time 89762719 ps
CPU time 0.7 seconds
Started Jun 06 01:37:47 PM PDT 24
Finished Jun 06 01:37:49 PM PDT 24
Peak memory 204004 kb
Host smart-e095baae-5580-4e7d-8021-16ed680bc0ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107880934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1107880934
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1805909259
Short name T986
Test name
Test status
Simulation time 65944257 ps
CPU time 2 seconds
Started Jun 06 01:38:00 PM PDT 24
Finished Jun 06 01:38:03 PM PDT 24
Peak memory 215712 kb
Host smart-6a48ec33-92a8-4b97-a121-4dd0ecedac98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805909259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1805909259
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.102109064
Short name T95
Test name
Test status
Simulation time 163763004 ps
CPU time 4.07 seconds
Started Jun 06 01:37:47 PM PDT 24
Finished Jun 06 01:37:52 PM PDT 24
Peak memory 215832 kb
Host smart-286433fc-ed3c-4437-8d1d-a7b9c58d1cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102109064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.102109064
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2783188477
Short name T261
Test name
Test status
Simulation time 1736605074 ps
CPU time 21.51 seconds
Started Jun 06 01:37:46 PM PDT 24
Finished Jun 06 01:38:08 PM PDT 24
Peak memory 215940 kb
Host smart-2a53589e-5701-4b54-b85b-bf8b72729e71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783188477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2783188477
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3308444374
Short name T1065
Test name
Test status
Simulation time 156221292 ps
CPU time 3.12 seconds
Started Jun 06 01:37:58 PM PDT 24
Finished Jun 06 01:38:03 PM PDT 24
Peak memory 216852 kb
Host smart-267deef9-bcaa-4b62-bf3b-c4bf4b405051
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308444374 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3308444374
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1025918844
Short name T1018
Test name
Test status
Simulation time 158459564 ps
CPU time 1.24 seconds
Started Jun 06 01:37:57 PM PDT 24
Finished Jun 06 01:38:00 PM PDT 24
Peak memory 215844 kb
Host smart-d1b6ed61-2e3a-48f5-9296-5e0ee80c4909
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025918844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1025918844
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4259947487
Short name T1048
Test name
Test status
Simulation time 24510163 ps
CPU time 0.72 seconds
Started Jun 06 01:38:00 PM PDT 24
Finished Jun 06 01:38:02 PM PDT 24
Peak memory 204000 kb
Host smart-689dbf1d-59e2-4ffa-93c7-a460dea710b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259947487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
4259947487
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3844858028
Short name T995
Test name
Test status
Simulation time 25789302 ps
CPU time 1.83 seconds
Started Jun 06 01:38:00 PM PDT 24
Finished Jun 06 01:38:04 PM PDT 24
Peak memory 215676 kb
Host smart-033a4c18-8e44-4934-8b8d-eb5235ab5776
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844858028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3844858028
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3939971243
Short name T1034
Test name
Test status
Simulation time 97292287 ps
CPU time 1.87 seconds
Started Jun 06 01:37:57 PM PDT 24
Finished Jun 06 01:38:00 PM PDT 24
Peak memory 215612 kb
Host smart-5637d62b-caae-497a-ad8a-dcd113e2cf42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939971243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3939971243
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3458015412
Short name T92
Test name
Test status
Simulation time 673354727 ps
CPU time 15.94 seconds
Started Jun 06 01:37:56 PM PDT 24
Finished Jun 06 01:38:13 PM PDT 24
Peak memory 216224 kb
Host smart-dd041dcc-a7af-4463-bc12-61e0c79b8be6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458015412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3458015412
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1089639190
Short name T1050
Test name
Test status
Simulation time 321791339 ps
CPU time 2.89 seconds
Started Jun 06 01:37:58 PM PDT 24
Finished Jun 06 01:38:03 PM PDT 24
Peak memory 218056 kb
Host smart-dcee6ed2-dd59-4ac4-8cac-357b7a177a63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089639190 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1089639190
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4159048425
Short name T1089
Test name
Test status
Simulation time 65413266 ps
CPU time 2.43 seconds
Started Jun 06 01:38:03 PM PDT 24
Finished Jun 06 01:38:07 PM PDT 24
Peak memory 207604 kb
Host smart-8dc9533d-23a0-4c8c-93a8-2a756a4070b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159048425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4159048425
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1821541151
Short name T1001
Test name
Test status
Simulation time 18872729 ps
CPU time 0.75 seconds
Started Jun 06 01:37:55 PM PDT 24
Finished Jun 06 01:37:57 PM PDT 24
Peak memory 204016 kb
Host smart-48d62ce8-02b4-4e81-8a77-2440f06ec9b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821541151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1821541151
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3326741354
Short name T1059
Test name
Test status
Simulation time 43866652 ps
CPU time 2.75 seconds
Started Jun 06 01:37:59 PM PDT 24
Finished Jun 06 01:38:04 PM PDT 24
Peak memory 207496 kb
Host smart-a3a734c9-64b3-4c27-8c59-06529ddcb4ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326741354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3326741354
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1942519961
Short name T1100
Test name
Test status
Simulation time 894959736 ps
CPU time 5.46 seconds
Started Jun 06 01:37:56 PM PDT 24
Finished Jun 06 01:38:02 PM PDT 24
Peak memory 215872 kb
Host smart-988e1826-6263-45cc-b1dc-4a7a3fdae6a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942519961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1942519961
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3336885962
Short name T1077
Test name
Test status
Simulation time 938105548 ps
CPU time 20.85 seconds
Started Jun 06 01:37:56 PM PDT 24
Finished Jun 06 01:38:18 PM PDT 24
Peak memory 215964 kb
Host smart-4188ed2f-0d63-4769-a585-1bc01bb44998
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336885962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3336885962
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2634527502
Short name T999
Test name
Test status
Simulation time 256292375 ps
CPU time 3.7 seconds
Started Jun 06 01:38:00 PM PDT 24
Finished Jun 06 01:38:06 PM PDT 24
Peak memory 216764 kb
Host smart-0ae327fd-8c0d-4b22-be51-b30bfe83a772
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634527502 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2634527502
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1284595042
Short name T115
Test name
Test status
Simulation time 264148934 ps
CPU time 1.95 seconds
Started Jun 06 01:37:56 PM PDT 24
Finished Jun 06 01:37:59 PM PDT 24
Peak memory 215628 kb
Host smart-d430fa12-7afd-4868-beaa-b1fd8cd5ba52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284595042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1284595042
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.704086500
Short name T988
Test name
Test status
Simulation time 15290459 ps
CPU time 0.74 seconds
Started Jun 06 01:37:56 PM PDT 24
Finished Jun 06 01:37:58 PM PDT 24
Peak memory 204360 kb
Host smart-3a32964c-dbcc-4a19-8353-fde2d010680b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704086500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.704086500
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3612991368
Short name T142
Test name
Test status
Simulation time 577249114 ps
CPU time 3.06 seconds
Started Jun 06 01:37:57 PM PDT 24
Finished Jun 06 01:38:02 PM PDT 24
Peak memory 215668 kb
Host smart-3ab679b1-caec-49e9-b3db-1e5a0dca2905
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612991368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3612991368
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.280963729
Short name T1055
Test name
Test status
Simulation time 126527985 ps
CPU time 3.56 seconds
Started Jun 06 01:38:02 PM PDT 24
Finished Jun 06 01:38:07 PM PDT 24
Peak memory 216024 kb
Host smart-edeab49e-cc3c-4605-96b5-9294721973a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280963729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.280963729
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4086281015
Short name T1002
Test name
Test status
Simulation time 112054089 ps
CPU time 6.71 seconds
Started Jun 06 01:38:01 PM PDT 24
Finished Jun 06 01:38:10 PM PDT 24
Peak memory 215708 kb
Host smart-8f1a9d19-40c5-482d-b358-69c5c049d7e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086281015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.4086281015
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1505342511
Short name T108
Test name
Test status
Simulation time 689163454 ps
CPU time 7.78 seconds
Started Jun 06 01:37:16 PM PDT 24
Finished Jun 06 01:37:24 PM PDT 24
Peak memory 207564 kb
Host smart-eefc37d0-cbe0-44dd-8d6b-e3e4f033a93c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505342511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1505342511
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2203165611
Short name T1088
Test name
Test status
Simulation time 22545049949 ps
CPU time 35.01 seconds
Started Jun 06 01:37:16 PM PDT 24
Finished Jun 06 01:37:52 PM PDT 24
Peak memory 207516 kb
Host smart-ebcf09ec-5405-4eaf-b539-511fad65af41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203165611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2203165611
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.855184335
Short name T73
Test name
Test status
Simulation time 260307148 ps
CPU time 0.92 seconds
Started Jun 06 01:37:09 PM PDT 24
Finished Jun 06 01:37:11 PM PDT 24
Peak memory 207152 kb
Host smart-91cf291d-6160-4e0f-ada2-faf027274d1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855184335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.855184335
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4206183824
Short name T1044
Test name
Test status
Simulation time 55975163 ps
CPU time 3.48 seconds
Started Jun 06 01:37:13 PM PDT 24
Finished Jun 06 01:37:17 PM PDT 24
Peak memory 218752 kb
Host smart-cc07f7d6-def9-40bf-b9c2-5416a5703aa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206183824 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.4206183824
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3730549995
Short name T112
Test name
Test status
Simulation time 269043440 ps
CPU time 1.95 seconds
Started Jun 06 01:37:09 PM PDT 24
Finished Jun 06 01:37:12 PM PDT 24
Peak memory 215604 kb
Host smart-de10e955-ebe4-4fc2-987f-817cdc745c1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730549995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
730549995
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.13847207
Short name T997
Test name
Test status
Simulation time 30387124 ps
CPU time 0.75 seconds
Started Jun 06 01:37:18 PM PDT 24
Finished Jun 06 01:37:20 PM PDT 24
Peak memory 204332 kb
Host smart-e0c3b607-411a-48e7-a99d-90cfc9ea2569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13847207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.13847207
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1007392530
Short name T1012
Test name
Test status
Simulation time 443499208 ps
CPU time 1.32 seconds
Started Jun 06 01:37:12 PM PDT 24
Finished Jun 06 01:37:13 PM PDT 24
Peak memory 215728 kb
Host smart-65a495c3-0435-43a5-9ef6-faf8c9130c77
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007392530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1007392530
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.221358604
Short name T1032
Test name
Test status
Simulation time 111243220 ps
CPU time 0.63 seconds
Started Jun 06 01:37:07 PM PDT 24
Finished Jun 06 01:37:09 PM PDT 24
Peak memory 204332 kb
Host smart-1f06e092-fde2-4efa-950c-218b621433eb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221358604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.221358604
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1725375503
Short name T1057
Test name
Test status
Simulation time 58265998 ps
CPU time 1.75 seconds
Started Jun 06 01:37:08 PM PDT 24
Finished Jun 06 01:37:11 PM PDT 24
Peak memory 207480 kb
Host smart-6755e9fe-8715-405e-bd57-cc485264aff0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725375503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1725375503
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.658218636
Short name T1078
Test name
Test status
Simulation time 174161662 ps
CPU time 3.03 seconds
Started Jun 06 01:37:15 PM PDT 24
Finished Jun 06 01:37:19 PM PDT 24
Peak memory 215984 kb
Host smart-8b3e3e58-6fd8-4ea3-b296-b1c8f86ff4b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658218636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.658218636
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1208967296
Short name T1066
Test name
Test status
Simulation time 214621991 ps
CPU time 6.9 seconds
Started Jun 06 01:37:15 PM PDT 24
Finished Jun 06 01:37:23 PM PDT 24
Peak memory 215748 kb
Host smart-3278fb43-9cf0-4297-b7f0-a02fb6bdb8e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208967296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1208967296
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2313885816
Short name T1071
Test name
Test status
Simulation time 14494105 ps
CPU time 0.74 seconds
Started Jun 06 01:37:57 PM PDT 24
Finished Jun 06 01:37:58 PM PDT 24
Peak memory 204004 kb
Host smart-73de2ba7-4980-4965-8518-c14c93d2c583
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313885816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2313885816
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.618071181
Short name T984
Test name
Test status
Simulation time 23797667 ps
CPU time 0.68 seconds
Started Jun 06 01:37:56 PM PDT 24
Finished Jun 06 01:37:58 PM PDT 24
Peak memory 204336 kb
Host smart-d8a6fe4f-21b1-438f-94f5-37c166bae6ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618071181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.618071181
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3794722156
Short name T1062
Test name
Test status
Simulation time 23459848 ps
CPU time 0.73 seconds
Started Jun 06 01:38:00 PM PDT 24
Finished Jun 06 01:38:03 PM PDT 24
Peak memory 204024 kb
Host smart-f0868c5c-8e93-4c71-86a4-7f3a72b9b9a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794722156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3794722156
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2123722671
Short name T1009
Test name
Test status
Simulation time 13768198 ps
CPU time 0.69 seconds
Started Jun 06 01:38:04 PM PDT 24
Finished Jun 06 01:38:06 PM PDT 24
Peak memory 203996 kb
Host smart-eef37ba8-f20d-4a23-852d-c3e52e9688d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123722671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2123722671
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3894925814
Short name T1029
Test name
Test status
Simulation time 12779519 ps
CPU time 0.83 seconds
Started Jun 06 01:38:00 PM PDT 24
Finished Jun 06 01:38:02 PM PDT 24
Peak memory 204356 kb
Host smart-bcc7c45a-22b7-4c15-8c9e-49b2f85fb2bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894925814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3894925814
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3407691801
Short name T1007
Test name
Test status
Simulation time 28397326 ps
CPU time 0.73 seconds
Started Jun 06 01:38:00 PM PDT 24
Finished Jun 06 01:38:02 PM PDT 24
Peak memory 204352 kb
Host smart-34e813a6-5c4a-4b8d-a446-0cfc45761b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407691801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3407691801
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2505403746
Short name T1040
Test name
Test status
Simulation time 13467203 ps
CPU time 0.71 seconds
Started Jun 06 01:37:59 PM PDT 24
Finished Jun 06 01:38:02 PM PDT 24
Peak memory 204012 kb
Host smart-03974f32-8f63-4586-834f-f716305c4d2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505403746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2505403746
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2619003858
Short name T981
Test name
Test status
Simulation time 27843709 ps
CPU time 0.69 seconds
Started Jun 06 01:37:57 PM PDT 24
Finished Jun 06 01:37:59 PM PDT 24
Peak memory 204068 kb
Host smart-d83c77f4-2409-483e-b61d-00963fc5cd46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619003858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2619003858
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1267036017
Short name T1031
Test name
Test status
Simulation time 13460242 ps
CPU time 0.7 seconds
Started Jun 06 01:37:58 PM PDT 24
Finished Jun 06 01:38:01 PM PDT 24
Peak memory 204020 kb
Host smart-08227cc6-5011-42de-adbb-9f55c4c90e57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267036017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1267036017
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1941385943
Short name T1046
Test name
Test status
Simulation time 15880402 ps
CPU time 0.71 seconds
Started Jun 06 01:38:03 PM PDT 24
Finished Jun 06 01:38:05 PM PDT 24
Peak memory 204300 kb
Host smart-fb558a8c-0500-4f24-960d-bc948d48d950
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941385943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1941385943
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1220832630
Short name T111
Test name
Test status
Simulation time 1471022405 ps
CPU time 14.77 seconds
Started Jun 06 01:37:15 PM PDT 24
Finished Jun 06 01:37:31 PM PDT 24
Peak memory 215728 kb
Host smart-5680e31a-cd09-462b-b340-221b7787b9d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220832630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1220832630
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.987644896
Short name T1080
Test name
Test status
Simulation time 2168915298 ps
CPU time 34.36 seconds
Started Jun 06 01:37:19 PM PDT 24
Finished Jun 06 01:37:54 PM PDT 24
Peak memory 215560 kb
Host smart-4071c482-9ab1-4a4a-af4b-0a687a2ebd68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987644896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.987644896
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1151268912
Short name T1037
Test name
Test status
Simulation time 23563009 ps
CPU time 1.34 seconds
Started Jun 06 01:37:15 PM PDT 24
Finished Jun 06 01:37:17 PM PDT 24
Peak memory 216668 kb
Host smart-e4c15de6-631e-41ac-a430-a2910959a4e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151268912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1151268912
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1023899434
Short name T1061
Test name
Test status
Simulation time 127682951 ps
CPU time 3.44 seconds
Started Jun 06 01:37:18 PM PDT 24
Finished Jun 06 01:37:23 PM PDT 24
Peak memory 217584 kb
Host smart-7ddcb64a-fd5f-4c32-88ad-7bcbb1c1995c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023899434 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1023899434
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3832979872
Short name T1035
Test name
Test status
Simulation time 68336737 ps
CPU time 1.33 seconds
Started Jun 06 01:37:19 PM PDT 24
Finished Jun 06 01:37:21 PM PDT 24
Peak memory 215596 kb
Host smart-f9367248-c25d-4173-9194-5364286547b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832979872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
832979872
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.276675993
Short name T1004
Test name
Test status
Simulation time 11920362 ps
CPU time 0.73 seconds
Started Jun 06 01:37:16 PM PDT 24
Finished Jun 06 01:37:17 PM PDT 24
Peak memory 204044 kb
Host smart-b3357b65-42d9-44c9-9e98-61a7a2e029bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276675993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.276675993
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2418847221
Short name T116
Test name
Test status
Simulation time 57606585 ps
CPU time 1.8 seconds
Started Jun 06 01:37:16 PM PDT 24
Finished Jun 06 01:37:19 PM PDT 24
Peak memory 215852 kb
Host smart-14d6cb18-625b-4181-9814-b3bbce3efba5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418847221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2418847221
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2030090624
Short name T1081
Test name
Test status
Simulation time 11466022 ps
CPU time 0.67 seconds
Started Jun 06 01:37:19 PM PDT 24
Finished Jun 06 01:37:21 PM PDT 24
Peak memory 203984 kb
Host smart-79299126-9a8a-4784-97ad-5ef776b94475
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030090624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2030090624
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.850157591
Short name T1030
Test name
Test status
Simulation time 1310604491 ps
CPU time 4.31 seconds
Started Jun 06 01:37:16 PM PDT 24
Finished Jun 06 01:37:21 PM PDT 24
Peak memory 215764 kb
Host smart-70c06370-b076-413c-a9b5-09104ee8b0b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850157591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.850157591
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3142350452
Short name T1101
Test name
Test status
Simulation time 56488798 ps
CPU time 2 seconds
Started Jun 06 01:37:19 PM PDT 24
Finished Jun 06 01:37:22 PM PDT 24
Peak memory 215892 kb
Host smart-d3445a9c-845a-406d-8da2-c4b0e1f2dfb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142350452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
142350452
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.580718956
Short name T93
Test name
Test status
Simulation time 430816655 ps
CPU time 6.83 seconds
Started Jun 06 01:37:17 PM PDT 24
Finished Jun 06 01:37:25 PM PDT 24
Peak memory 216516 kb
Host smart-910807eb-48a6-49d0-a781-37c19d15f80d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580718956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.580718956
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2858699223
Short name T1068
Test name
Test status
Simulation time 51601782 ps
CPU time 0.71 seconds
Started Jun 06 01:37:58 PM PDT 24
Finished Jun 06 01:38:00 PM PDT 24
Peak memory 204080 kb
Host smart-255400a4-bbe2-4c4c-8e7a-74490325d0f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858699223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2858699223
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4223847509
Short name T1092
Test name
Test status
Simulation time 47368777 ps
CPU time 0.67 seconds
Started Jun 06 01:37:56 PM PDT 24
Finished Jun 06 01:37:58 PM PDT 24
Peak memory 204020 kb
Host smart-e2ecb45f-af95-4ea6-adcf-202cf143e228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223847509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4223847509
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2403317990
Short name T1017
Test name
Test status
Simulation time 15159592 ps
CPU time 0.78 seconds
Started Jun 06 01:38:00 PM PDT 24
Finished Jun 06 01:38:02 PM PDT 24
Peak memory 204032 kb
Host smart-215af4fe-0019-4de3-b7ba-8ddef27081d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403317990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2403317990
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1840489274
Short name T1006
Test name
Test status
Simulation time 126914739 ps
CPU time 0.78 seconds
Started Jun 06 01:38:03 PM PDT 24
Finished Jun 06 01:38:05 PM PDT 24
Peak memory 204008 kb
Host smart-88fa393c-4ea6-4d1f-a43f-ca26ccc08631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840489274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1840489274
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4234547270
Short name T1053
Test name
Test status
Simulation time 22221780 ps
CPU time 0.72 seconds
Started Jun 06 01:37:56 PM PDT 24
Finished Jun 06 01:37:58 PM PDT 24
Peak memory 204060 kb
Host smart-7c0a9d26-b246-4232-93dc-afaa1ef4c626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234547270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4234547270
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3815639426
Short name T1005
Test name
Test status
Simulation time 21972078 ps
CPU time 0.76 seconds
Started Jun 06 01:38:02 PM PDT 24
Finished Jun 06 01:38:04 PM PDT 24
Peak memory 204032 kb
Host smart-07b9747e-1c8c-417b-b4b9-f68ef7e9f6a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815639426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3815639426
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1083848171
Short name T1060
Test name
Test status
Simulation time 21781420 ps
CPU time 0.68 seconds
Started Jun 06 01:37:59 PM PDT 24
Finished Jun 06 01:38:02 PM PDT 24
Peak memory 204344 kb
Host smart-0285a38d-b7ec-4a50-aa77-e8b60e161fb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083848171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1083848171
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1124691256
Short name T1003
Test name
Test status
Simulation time 81800624 ps
CPU time 0.75 seconds
Started Jun 06 01:37:59 PM PDT 24
Finished Jun 06 01:38:02 PM PDT 24
Peak memory 204340 kb
Host smart-ec0a55bd-28ce-4c44-bcb4-b05a3255e272
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124691256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1124691256
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3999878594
Short name T979
Test name
Test status
Simulation time 18621296 ps
CPU time 0.76 seconds
Started Jun 06 01:38:03 PM PDT 24
Finished Jun 06 01:38:05 PM PDT 24
Peak memory 204048 kb
Host smart-3dd99b44-0224-4a65-af72-90f9d8a1e778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999878594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3999878594
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4220548238
Short name T992
Test name
Test status
Simulation time 17093320 ps
CPU time 0.76 seconds
Started Jun 06 01:37:58 PM PDT 24
Finished Jun 06 01:38:01 PM PDT 24
Peak memory 204048 kb
Host smart-8e7a5d58-b0d8-4220-bf41-0fe740cc26ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220548238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
4220548238
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2131589771
Short name T114
Test name
Test status
Simulation time 4495106844 ps
CPU time 24.92 seconds
Started Jun 06 01:37:15 PM PDT 24
Finished Jun 06 01:37:40 PM PDT 24
Peak memory 215792 kb
Host smart-871d3178-88b7-49e0-9823-a72288a4f915
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131589771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2131589771
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2501269157
Short name T110
Test name
Test status
Simulation time 6442626851 ps
CPU time 26.68 seconds
Started Jun 06 01:37:16 PM PDT 24
Finished Jun 06 01:37:44 PM PDT 24
Peak memory 215780 kb
Host smart-1817a200-e2f2-4aaa-b3b2-f33753691688
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501269157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2501269157
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4282192912
Short name T74
Test name
Test status
Simulation time 79436498 ps
CPU time 1.02 seconds
Started Jun 06 01:37:24 PM PDT 24
Finished Jun 06 01:37:25 PM PDT 24
Peak memory 207104 kb
Host smart-8e023a72-5078-47b5-aeb4-f952e514727d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282192912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.4282192912
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4181596529
Short name T1096
Test name
Test status
Simulation time 754472384 ps
CPU time 3.45 seconds
Started Jun 06 01:37:24 PM PDT 24
Finished Jun 06 01:37:28 PM PDT 24
Peak memory 217144 kb
Host smart-c0c2ada5-e739-43b6-9305-6f3d0b86c1e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181596529 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4181596529
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3392590797
Short name T119
Test name
Test status
Simulation time 1660559832 ps
CPU time 2.6 seconds
Started Jun 06 01:37:19 PM PDT 24
Finished Jun 06 01:37:22 PM PDT 24
Peak memory 215584 kb
Host smart-986e457d-5abf-4a64-9384-fd79e2b520e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392590797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
392590797
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1258048778
Short name T1011
Test name
Test status
Simulation time 13959543 ps
CPU time 0.72 seconds
Started Jun 06 01:37:16 PM PDT 24
Finished Jun 06 01:37:17 PM PDT 24
Peak memory 204016 kb
Host smart-da7deaed-00bc-4469-9506-8427900d6530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258048778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
258048778
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1055517762
Short name T107
Test name
Test status
Simulation time 334062860 ps
CPU time 2.18 seconds
Started Jun 06 01:37:18 PM PDT 24
Finished Jun 06 01:37:22 PM PDT 24
Peak memory 215840 kb
Host smart-148c3083-306a-4d98-ac38-5b3accbe190f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055517762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1055517762
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4103461628
Short name T1019
Test name
Test status
Simulation time 42338790 ps
CPU time 0.62 seconds
Started Jun 06 01:37:14 PM PDT 24
Finished Jun 06 01:37:15 PM PDT 24
Peak memory 203968 kb
Host smart-8c26e77c-0a6a-461a-96a0-9bcd5431bbc6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103461628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4103461628
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2468735130
Short name T1086
Test name
Test status
Simulation time 1167213469 ps
CPU time 1.98 seconds
Started Jun 06 01:37:18 PM PDT 24
Finished Jun 06 01:37:21 PM PDT 24
Peak memory 215708 kb
Host smart-dd5a67c3-0513-4453-b683-920dedaee538
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468735130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2468735130
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1210599770
Short name T1015
Test name
Test status
Simulation time 310259908 ps
CPU time 19.5 seconds
Started Jun 06 01:37:19 PM PDT 24
Finished Jun 06 01:37:39 PM PDT 24
Peak memory 215768 kb
Host smart-798ac357-479a-4c7d-9356-8d3700154819
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210599770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1210599770
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3511617699
Short name T978
Test name
Test status
Simulation time 101676952 ps
CPU time 0.82 seconds
Started Jun 06 01:38:01 PM PDT 24
Finished Jun 06 01:38:04 PM PDT 24
Peak memory 204056 kb
Host smart-e1b5cf50-00d9-4ec8-a73a-dcbdf18038b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511617699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3511617699
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3096977024
Short name T1023
Test name
Test status
Simulation time 17702489 ps
CPU time 0.76 seconds
Started Jun 06 01:37:57 PM PDT 24
Finished Jun 06 01:37:59 PM PDT 24
Peak memory 204092 kb
Host smart-3d023c2b-8433-4a50-9584-809ad8dd4c71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096977024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3096977024
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4278803657
Short name T1022
Test name
Test status
Simulation time 191495076 ps
CPU time 0.75 seconds
Started Jun 06 01:37:58 PM PDT 24
Finished Jun 06 01:38:00 PM PDT 24
Peak memory 204024 kb
Host smart-a74f37d1-01b4-4c0b-b310-eb2a544dafad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278803657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4278803657
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.150088550
Short name T1016
Test name
Test status
Simulation time 18303779 ps
CPU time 0.73 seconds
Started Jun 06 01:38:02 PM PDT 24
Finished Jun 06 01:38:04 PM PDT 24
Peak memory 204008 kb
Host smart-d6504055-37c7-4d54-a23e-b959ec705153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150088550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.150088550
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1976706252
Short name T1064
Test name
Test status
Simulation time 29291228 ps
CPU time 0.71 seconds
Started Jun 06 01:37:57 PM PDT 24
Finished Jun 06 01:37:59 PM PDT 24
Peak memory 204332 kb
Host smart-f2367df1-23f0-4c06-a9ad-1a5a0b4c766e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976706252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1976706252
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.179652672
Short name T989
Test name
Test status
Simulation time 17519468 ps
CPU time 0.71 seconds
Started Jun 06 01:38:03 PM PDT 24
Finished Jun 06 01:38:05 PM PDT 24
Peak memory 204000 kb
Host smart-9bd13f18-e108-4ab4-9018-cbf0c89d503c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179652672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.179652672
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2941981054
Short name T1099
Test name
Test status
Simulation time 55950592 ps
CPU time 0.68 seconds
Started Jun 06 01:37:57 PM PDT 24
Finished Jun 06 01:38:00 PM PDT 24
Peak memory 204016 kb
Host smart-d0d30634-5d01-44e9-9cfc-1023722ff568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941981054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2941981054
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.933507442
Short name T1056
Test name
Test status
Simulation time 21307372 ps
CPU time 0.68 seconds
Started Jun 06 01:37:58 PM PDT 24
Finished Jun 06 01:38:01 PM PDT 24
Peak memory 204040 kb
Host smart-f33fac9c-ae5c-47d4-a957-8545bcdcbf41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933507442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.933507442
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.368351086
Short name T1084
Test name
Test status
Simulation time 26414312 ps
CPU time 0.74 seconds
Started Jun 06 01:38:00 PM PDT 24
Finished Jun 06 01:38:03 PM PDT 24
Peak memory 204060 kb
Host smart-4b1fe7c0-e90c-4f2d-9b7c-9f8143c1b3ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368351086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.368351086
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.818951683
Short name T991
Test name
Test status
Simulation time 19307108 ps
CPU time 0.78 seconds
Started Jun 06 01:37:58 PM PDT 24
Finished Jun 06 01:38:00 PM PDT 24
Peak memory 204016 kb
Host smart-d291c83c-7ddd-4fd0-ab44-613f58cb358f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818951683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.818951683
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2698038941
Short name T1093
Test name
Test status
Simulation time 70765247 ps
CPU time 2.06 seconds
Started Jun 06 01:37:14 PM PDT 24
Finished Jun 06 01:37:17 PM PDT 24
Peak memory 216892 kb
Host smart-76d17ea2-ef1a-442d-8d4e-d33c62c7c1a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698038941 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2698038941
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1281417032
Short name T113
Test name
Test status
Simulation time 29790750 ps
CPU time 1.98 seconds
Started Jun 06 01:37:14 PM PDT 24
Finished Jun 06 01:37:16 PM PDT 24
Peak memory 215796 kb
Host smart-91838e1a-cfa5-47a7-afb3-3d867650df6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281417032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
281417032
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2889440781
Short name T1014
Test name
Test status
Simulation time 59309327 ps
CPU time 0.75 seconds
Started Jun 06 01:37:20 PM PDT 24
Finished Jun 06 01:37:22 PM PDT 24
Peak memory 203976 kb
Host smart-98cbc423-9dd0-445a-835f-02d09c043c7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889440781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
889440781
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.452066631
Short name T141
Test name
Test status
Simulation time 653599512 ps
CPU time 3.98 seconds
Started Jun 06 01:37:27 PM PDT 24
Finished Jun 06 01:37:31 PM PDT 24
Peak memory 215760 kb
Host smart-6db7d752-d1f7-4e24-b4ff-049a888e1fb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452066631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.452066631
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3019824304
Short name T96
Test name
Test status
Simulation time 54652216 ps
CPU time 1.83 seconds
Started Jun 06 01:37:15 PM PDT 24
Finished Jun 06 01:37:18 PM PDT 24
Peak memory 215988 kb
Host smart-3a12f799-1118-453a-a881-5af1f73bea62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019824304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
019824304
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2679938484
Short name T1074
Test name
Test status
Simulation time 793968751 ps
CPU time 12.07 seconds
Started Jun 06 01:37:15 PM PDT 24
Finished Jun 06 01:37:28 PM PDT 24
Peak memory 215828 kb
Host smart-f3c7e917-2f1d-4881-bb5c-8b33a6982e06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679938484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2679938484
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1682908293
Short name T996
Test name
Test status
Simulation time 194821415 ps
CPU time 1.69 seconds
Started Jun 06 01:37:27 PM PDT 24
Finished Jun 06 01:37:29 PM PDT 24
Peak memory 216004 kb
Host smart-dfefffe4-7f88-4a37-a94b-031aee6decd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682908293 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1682908293
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1345691916
Short name T1013
Test name
Test status
Simulation time 494800590 ps
CPU time 1.97 seconds
Started Jun 06 01:37:13 PM PDT 24
Finished Jun 06 01:37:16 PM PDT 24
Peak memory 215696 kb
Host smart-49d5fdba-188d-4b28-88ed-ee834eb40794
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345691916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
345691916
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3085329257
Short name T1063
Test name
Test status
Simulation time 19079481 ps
CPU time 0.73 seconds
Started Jun 06 01:37:17 PM PDT 24
Finished Jun 06 01:37:19 PM PDT 24
Peak memory 203924 kb
Host smart-9523c0b6-0976-4041-ab8d-aa93340593f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085329257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
085329257
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.951670079
Short name T1090
Test name
Test status
Simulation time 114478733 ps
CPU time 3.9 seconds
Started Jun 06 01:37:16 PM PDT 24
Finished Jun 06 01:37:21 PM PDT 24
Peak memory 215704 kb
Host smart-633944c8-1e59-467b-9ef7-104e048d1f1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951670079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.951670079
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4275431737
Short name T1043
Test name
Test status
Simulation time 58613693 ps
CPU time 2.51 seconds
Started Jun 06 01:37:18 PM PDT 24
Finished Jun 06 01:37:22 PM PDT 24
Peak memory 215764 kb
Host smart-e6231588-d909-4884-9171-8a0024f9a1fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275431737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
275431737
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1980503848
Short name T257
Test name
Test status
Simulation time 1098391203 ps
CPU time 13.4 seconds
Started Jun 06 01:37:16 PM PDT 24
Finished Jun 06 01:37:31 PM PDT 24
Peak memory 215600 kb
Host smart-029c40ee-243b-49d6-a652-d5c3516ae8e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980503848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1980503848
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2132828164
Short name T89
Test name
Test status
Simulation time 73222216 ps
CPU time 2.59 seconds
Started Jun 06 01:37:45 PM PDT 24
Finished Jun 06 01:37:48 PM PDT 24
Peak memory 218224 kb
Host smart-1c8d57de-72db-478e-8472-7fec33b9e1eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132828164 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2132828164
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2752794246
Short name T990
Test name
Test status
Simulation time 36379555 ps
CPU time 1.33 seconds
Started Jun 06 01:37:26 PM PDT 24
Finished Jun 06 01:37:27 PM PDT 24
Peak memory 207564 kb
Host smart-e6125ee2-f4ee-4f4f-a9fd-095e02aa2bcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752794246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
752794246
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1104914238
Short name T1051
Test name
Test status
Simulation time 34629930 ps
CPU time 0.72 seconds
Started Jun 06 01:37:28 PM PDT 24
Finished Jun 06 01:37:29 PM PDT 24
Peak memory 204020 kb
Host smart-bf94b77b-7dc8-4911-ac83-3c3e1810c751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104914238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
104914238
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1991985156
Short name T1070
Test name
Test status
Simulation time 126542961 ps
CPU time 4.44 seconds
Started Jun 06 01:37:27 PM PDT 24
Finished Jun 06 01:37:31 PM PDT 24
Peak memory 215712 kb
Host smart-3d61cdc4-7143-4abe-93a4-ed002979e261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991985156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1991985156
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1280285885
Short name T1095
Test name
Test status
Simulation time 96738733 ps
CPU time 3.77 seconds
Started Jun 06 01:37:27 PM PDT 24
Finished Jun 06 01:37:31 PM PDT 24
Peak memory 216004 kb
Host smart-9a7664f7-1aea-4811-ba05-e7081f1acff5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280285885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
280285885
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.500769986
Short name T256
Test name
Test status
Simulation time 560184084 ps
CPU time 8.59 seconds
Started Jun 06 01:37:27 PM PDT 24
Finished Jun 06 01:37:36 PM PDT 24
Peak memory 215792 kb
Host smart-aeb87e42-2c44-4b85-bb44-c31bba6638bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500769986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.500769986
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3500179894
Short name T100
Test name
Test status
Simulation time 421226017 ps
CPU time 3.87 seconds
Started Jun 06 01:37:28 PM PDT 24
Finished Jun 06 01:37:33 PM PDT 24
Peak memory 217624 kb
Host smart-e3693666-ad4b-48f7-af97-f60adba34839
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500179894 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3500179894
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2480292513
Short name T144
Test name
Test status
Simulation time 173884722 ps
CPU time 1.42 seconds
Started Jun 06 01:37:26 PM PDT 24
Finished Jun 06 01:37:28 PM PDT 24
Peak memory 215692 kb
Host smart-4290182f-1271-4c71-a679-1b27897bc3e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480292513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
480292513
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.70177257
Short name T987
Test name
Test status
Simulation time 12965050 ps
CPU time 0.72 seconds
Started Jun 06 01:37:30 PM PDT 24
Finished Jun 06 01:37:31 PM PDT 24
Peak memory 204016 kb
Host smart-75a5b7b4-f408-4715-86c6-5ed43632801d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70177257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.70177257
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4102704853
Short name T985
Test name
Test status
Simulation time 124499086 ps
CPU time 1.69 seconds
Started Jun 06 01:37:28 PM PDT 24
Finished Jun 06 01:37:31 PM PDT 24
Peak memory 215752 kb
Host smart-5947184e-d727-4f6f-ab11-5def49a311c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102704853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.4102704853
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2312348309
Short name T88
Test name
Test status
Simulation time 106346253 ps
CPU time 2.25 seconds
Started Jun 06 01:37:29 PM PDT 24
Finished Jun 06 01:37:32 PM PDT 24
Peak memory 215896 kb
Host smart-d0b1410d-22bc-42d9-ac1d-c64c235aa365
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312348309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
312348309
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.326052945
Short name T1021
Test name
Test status
Simulation time 369278876 ps
CPU time 18.48 seconds
Started Jun 06 01:37:28 PM PDT 24
Finished Jun 06 01:37:47 PM PDT 24
Peak memory 215932 kb
Host smart-5fe62d71-8950-4a22-9f55-5402c2b5397d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326052945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.326052945
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.464928519
Short name T94
Test name
Test status
Simulation time 333845043 ps
CPU time 2.76 seconds
Started Jun 06 01:37:37 PM PDT 24
Finished Jun 06 01:37:40 PM PDT 24
Peak memory 216728 kb
Host smart-0a9ed9ee-1cc0-44bf-8445-b7e8cae15708
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464928519 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.464928519
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1142191025
Short name T1041
Test name
Test status
Simulation time 68618956 ps
CPU time 1.92 seconds
Started Jun 06 01:37:38 PM PDT 24
Finished Jun 06 01:37:41 PM PDT 24
Peak memory 207580 kb
Host smart-8ec4a469-7ce3-4e87-989c-4a302e9a1dda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142191025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
142191025
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3545948035
Short name T1008
Test name
Test status
Simulation time 37403302 ps
CPU time 0.76 seconds
Started Jun 06 01:37:37 PM PDT 24
Finished Jun 06 01:37:39 PM PDT 24
Peak memory 204356 kb
Host smart-d79091fa-ebf7-4fc8-be8c-eece7fd967d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545948035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
545948035
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2816922797
Short name T993
Test name
Test status
Simulation time 120465023 ps
CPU time 3.84 seconds
Started Jun 06 01:37:35 PM PDT 24
Finished Jun 06 01:37:39 PM PDT 24
Peak memory 215848 kb
Host smart-838402e0-687e-4730-8e27-2f8fa57bc105
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816922797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2816922797
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3580550806
Short name T102
Test name
Test status
Simulation time 254126451 ps
CPU time 4.47 seconds
Started Jun 06 01:37:26 PM PDT 24
Finished Jun 06 01:37:31 PM PDT 24
Peak memory 215908 kb
Host smart-18983622-f5ee-4a82-bd55-91dab27c7e8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580550806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
580550806
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3767439679
Short name T262
Test name
Test status
Simulation time 114115530 ps
CPU time 6.6 seconds
Started Jun 06 01:37:39 PM PDT 24
Finished Jun 06 01:37:46 PM PDT 24
Peak memory 216196 kb
Host smart-cd57e577-8556-4e48-9ef2-4ebccd6dde84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767439679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3767439679
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3622147751
Short name T438
Test name
Test status
Simulation time 22250500 ps
CPU time 0.74 seconds
Started Jun 06 02:41:59 PM PDT 24
Finished Jun 06 02:42:03 PM PDT 24
Peak memory 205556 kb
Host smart-ca4dc248-3e47-4e5e-a64f-aa8a83178bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622147751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
622147751
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.510318202
Short name T51
Test name
Test status
Simulation time 58576092 ps
CPU time 0.87 seconds
Started Jun 06 02:41:49 PM PDT 24
Finished Jun 06 02:41:54 PM PDT 24
Peak memory 206752 kb
Host smart-3fa8bd3b-6f63-4dca-ba36-538d383ae19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510318202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.510318202
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3988528562
Short name T834
Test name
Test status
Simulation time 2934768823 ps
CPU time 62.79 seconds
Started Jun 06 02:41:48 PM PDT 24
Finished Jun 06 02:42:55 PM PDT 24
Peak memory 253700 kb
Host smart-0d9a7cb8-b49b-4950-963e-776941c02ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988528562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3988528562
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2015061525
Short name T325
Test name
Test status
Simulation time 5163557494 ps
CPU time 26.22 seconds
Started Jun 06 02:41:46 PM PDT 24
Finished Jun 06 02:42:16 PM PDT 24
Peak memory 217624 kb
Host smart-5fe0b9ff-ba91-42cd-853e-613f12367f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015061525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2015061525
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.884219658
Short name T603
Test name
Test status
Simulation time 254420860902 ps
CPU time 313.54 seconds
Started Jun 06 02:42:03 PM PDT 24
Finished Jun 06 02:47:18 PM PDT 24
Peak memory 251868 kb
Host smart-b6206e22-dc39-408d-a765-ba13adaee6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884219658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
884219658
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1707464221
Short name T928
Test name
Test status
Simulation time 217433636 ps
CPU time 3.16 seconds
Started Jun 06 02:41:49 PM PDT 24
Finished Jun 06 02:41:56 PM PDT 24
Peak memory 234048 kb
Host smart-e5f27f9f-42ca-404e-913e-caee2bfc4152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707464221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1707464221
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3577162422
Short name T433
Test name
Test status
Simulation time 343301061 ps
CPU time 2.34 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:42:03 PM PDT 24
Peak memory 222872 kb
Host smart-2a205dcf-dc59-41fc-98d2-6bba9a15abcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577162422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3577162422
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3832942279
Short name T886
Test name
Test status
Simulation time 16355222264 ps
CPU time 72.52 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:43:13 PM PDT 24
Peak memory 231584 kb
Host smart-a8f28ab8-bc2f-4030-b898-961113796e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832942279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3832942279
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2627411014
Short name T676
Test name
Test status
Simulation time 358074232 ps
CPU time 1.14 seconds
Started Jun 06 02:41:54 PM PDT 24
Finished Jun 06 02:41:59 PM PDT 24
Peak memory 216544 kb
Host smart-3300d8f7-68ea-4697-b0c8-d9d1659d6abd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627411014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2627411014
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1882958453
Short name T934
Test name
Test status
Simulation time 2309535627 ps
CPU time 3.83 seconds
Started Jun 06 02:41:52 PM PDT 24
Finished Jun 06 02:42:00 PM PDT 24
Peak memory 232824 kb
Host smart-11ffcbf8-f3b3-4e50-b72e-335ef303fc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882958453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1882958453
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1672086023
Short name T203
Test name
Test status
Simulation time 5393597989 ps
CPU time 16.05 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:42:17 PM PDT 24
Peak memory 240848 kb
Host smart-3338ba61-253f-4ad9-a0d1-0d63b8bb7c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672086023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1672086023
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3747077738
Short name T472
Test name
Test status
Simulation time 308441734 ps
CPU time 4.52 seconds
Started Jun 06 02:41:59 PM PDT 24
Finished Jun 06 02:42:06 PM PDT 24
Peak memory 220156 kb
Host smart-e08ec9d0-1fbe-4a97-a014-78fbdeec75fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3747077738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3747077738
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2114887667
Short name T57
Test name
Test status
Simulation time 197972251 ps
CPU time 1.02 seconds
Started Jun 06 02:42:00 PM PDT 24
Finished Jun 06 02:42:03 PM PDT 24
Peak memory 234924 kb
Host smart-29652765-b7f7-43ef-aaa8-0d6a39442f7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114887667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2114887667
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2780394397
Short name T428
Test name
Test status
Simulation time 896033375 ps
CPU time 8.08 seconds
Started Jun 06 02:41:51 PM PDT 24
Finished Jun 06 02:42:04 PM PDT 24
Peak memory 216552 kb
Host smart-44105e66-a63e-4cc3-b92b-7a710bd1d7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780394397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2780394397
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3351194604
Short name T744
Test name
Test status
Simulation time 3304212741 ps
CPU time 8.7 seconds
Started Jun 06 02:41:50 PM PDT 24
Finished Jun 06 02:42:03 PM PDT 24
Peak memory 216288 kb
Host smart-458f4427-3462-4109-853e-bb1def554174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351194604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3351194604
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2490278600
Short name T913
Test name
Test status
Simulation time 141227365 ps
CPU time 2.17 seconds
Started Jun 06 02:41:51 PM PDT 24
Finished Jun 06 02:41:57 PM PDT 24
Peak memory 217556 kb
Host smart-8d713ee3-e955-41c3-bf95-912badcc262b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490278600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2490278600
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3558651209
Short name T692
Test name
Test status
Simulation time 23241380 ps
CPU time 0.68 seconds
Started Jun 06 02:41:50 PM PDT 24
Finished Jun 06 02:41:55 PM PDT 24
Peak memory 205432 kb
Host smart-ed349840-1747-424a-8ac0-400cd25b414f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558651209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3558651209
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1092892546
Short name T180
Test name
Test status
Simulation time 504948703 ps
CPU time 4.96 seconds
Started Jun 06 02:41:51 PM PDT 24
Finished Jun 06 02:42:01 PM PDT 24
Peak memory 232768 kb
Host smart-3af962f3-1f51-4203-9fe6-c1eabeed9367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092892546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1092892546
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.294001710
Short name T401
Test name
Test status
Simulation time 27119601 ps
CPU time 0.72 seconds
Started Jun 06 02:41:58 PM PDT 24
Finished Jun 06 02:42:02 PM PDT 24
Peak memory 204572 kb
Host smart-302ba035-611c-44d4-9354-e30e30a6af28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294001710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.294001710
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3494114510
Short name T196
Test name
Test status
Simulation time 246021074 ps
CPU time 2.18 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:42:03 PM PDT 24
Peak memory 223016 kb
Host smart-b648e983-0cf6-4cc6-af13-bee22c5c2391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494114510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3494114510
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2195233395
Short name T688
Test name
Test status
Simulation time 14596215 ps
CPU time 0.79 seconds
Started Jun 06 02:41:48 PM PDT 24
Finished Jun 06 02:41:52 PM PDT 24
Peak memory 206480 kb
Host smart-5f00c1a6-7aca-4d68-aac8-b25647dc8ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195233395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2195233395
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2232966088
Short name T919
Test name
Test status
Simulation time 18658605961 ps
CPU time 138.02 seconds
Started Jun 06 02:41:48 PM PDT 24
Finished Jun 06 02:44:11 PM PDT 24
Peak memory 253416 kb
Host smart-ec84ee1f-0701-4d33-b64e-5053eba166b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232966088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2232966088
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3909847696
Short name T695
Test name
Test status
Simulation time 11111113447 ps
CPU time 74.28 seconds
Started Jun 06 02:41:55 PM PDT 24
Finished Jun 06 02:43:13 PM PDT 24
Peak memory 257524 kb
Host smart-6cd25df3-48fd-44e5-a207-5de972b0befc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909847696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3909847696
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2391695848
Short name T621
Test name
Test status
Simulation time 36540073599 ps
CPU time 284.28 seconds
Started Jun 06 02:41:46 PM PDT 24
Finished Jun 06 02:46:34 PM PDT 24
Peak memory 265452 kb
Host smart-71db6d39-9a73-40a0-bd48-3453dfa0aec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391695848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2391695848
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3820946012
Short name T34
Test name
Test status
Simulation time 648370391 ps
CPU time 13.15 seconds
Started Jun 06 02:41:51 PM PDT 24
Finished Jun 06 02:42:08 PM PDT 24
Peak memory 234040 kb
Host smart-a4838c26-1671-4cfb-afc0-c93c017dc910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820946012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3820946012
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1602641864
Short name T813
Test name
Test status
Simulation time 26092975694 ps
CPU time 74.48 seconds
Started Jun 06 02:41:47 PM PDT 24
Finished Jun 06 02:43:05 PM PDT 24
Peak memory 228132 kb
Host smart-012e5f29-b7ec-4ea1-931b-ad0655eb015d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602641864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1602641864
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3895994670
Short name T843
Test name
Test status
Simulation time 53026085 ps
CPU time 0.98 seconds
Started Jun 06 02:41:53 PM PDT 24
Finished Jun 06 02:41:58 PM PDT 24
Peak memory 217784 kb
Host smart-e204920b-7bf1-4980-8b67-68b1d53ae87c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895994670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3895994670
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2458425914
Short name T792
Test name
Test status
Simulation time 142011382 ps
CPU time 3.86 seconds
Started Jun 06 02:41:51 PM PDT 24
Finished Jun 06 02:41:59 PM PDT 24
Peak memory 232788 kb
Host smart-9a6da267-9804-4f7a-acea-dd0e4a1ab428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458425914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2458425914
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3734243843
Short name T694
Test name
Test status
Simulation time 1763140571 ps
CPU time 6.59 seconds
Started Jun 06 02:41:54 PM PDT 24
Finished Jun 06 02:42:05 PM PDT 24
Peak memory 218680 kb
Host smart-920c48d8-1916-47fc-9d9c-ea7152e69086
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3734243843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3734243843
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1272470905
Short name T60
Test name
Test status
Simulation time 250804537 ps
CPU time 1.08 seconds
Started Jun 06 02:41:52 PM PDT 24
Finished Jun 06 02:41:57 PM PDT 24
Peak memory 234960 kb
Host smart-1886bbc1-81a9-4872-87ba-dbddfcbd6de5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272470905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1272470905
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3195049561
Short name T788
Test name
Test status
Simulation time 9473101303 ps
CPU time 210.59 seconds
Started Jun 06 02:41:58 PM PDT 24
Finished Jun 06 02:45:32 PM PDT 24
Peak memory 273856 kb
Host smart-a94aa95f-987c-466d-aab7-75aebb6fe68b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195049561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3195049561
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1287666150
Short name T722
Test name
Test status
Simulation time 9442821588 ps
CPU time 45.25 seconds
Started Jun 06 02:41:49 PM PDT 24
Finished Jun 06 02:42:38 PM PDT 24
Peak memory 216432 kb
Host smart-f4a91ed8-65b1-45b4-885b-d71e77d4579e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287666150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1287666150
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1705022440
Short name T437
Test name
Test status
Simulation time 3727182894 ps
CPU time 12.41 seconds
Started Jun 06 02:41:55 PM PDT 24
Finished Jun 06 02:42:11 PM PDT 24
Peak memory 216408 kb
Host smart-1e0262a3-5f17-47f7-8fc1-3fc79f68cb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705022440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1705022440
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2510779574
Short name T874
Test name
Test status
Simulation time 40549212 ps
CPU time 0.82 seconds
Started Jun 06 02:41:59 PM PDT 24
Finished Jun 06 02:42:03 PM PDT 24
Peak memory 206364 kb
Host smart-2234f60f-584e-4f92-8812-c56f460ed5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510779574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2510779574
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2396681555
Short name T520
Test name
Test status
Simulation time 13795210 ps
CPU time 0.69 seconds
Started Jun 06 02:41:47 PM PDT 24
Finished Jun 06 02:41:52 PM PDT 24
Peak memory 205456 kb
Host smart-6129a06a-1e47-4879-8656-93837646bbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396681555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2396681555
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.849854916
Short name T264
Test name
Test status
Simulation time 14628347445 ps
CPU time 11.01 seconds
Started Jun 06 02:41:48 PM PDT 24
Finished Jun 06 02:42:03 PM PDT 24
Peak memory 224572 kb
Host smart-f2b3d867-2323-4e69-9a87-bb5258820f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849854916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.849854916
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.786939012
Short name T855
Test name
Test status
Simulation time 36760355 ps
CPU time 0.73 seconds
Started Jun 06 02:42:38 PM PDT 24
Finished Jun 06 02:42:41 PM PDT 24
Peak memory 204544 kb
Host smart-3c62ba55-03ee-454c-bff7-e78552f504fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786939012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.786939012
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1325863138
Short name T298
Test name
Test status
Simulation time 310147410 ps
CPU time 5.32 seconds
Started Jun 06 02:42:19 PM PDT 24
Finished Jun 06 02:42:26 PM PDT 24
Peak memory 224512 kb
Host smart-555b6ce5-6a66-4130-90c0-5fd46b9d5171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325863138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1325863138
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4178572210
Short name T699
Test name
Test status
Simulation time 28685268 ps
CPU time 0.78 seconds
Started Jun 06 02:42:14 PM PDT 24
Finished Jun 06 02:42:16 PM PDT 24
Peak memory 206812 kb
Host smart-de0df1b4-5af5-4591-8244-7a5234f278dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178572210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4178572210
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1397693674
Short name T69
Test name
Test status
Simulation time 17662650937 ps
CPU time 59.91 seconds
Started Jun 06 02:42:27 PM PDT 24
Finished Jun 06 02:43:29 PM PDT 24
Peak memory 257332 kb
Host smart-93d9906a-42d8-405c-be18-8921faf38f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397693674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1397693674
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.318233145
Short name T475
Test name
Test status
Simulation time 8836057786 ps
CPU time 69.91 seconds
Started Jun 06 02:42:30 PM PDT 24
Finished Jun 06 02:43:41 PM PDT 24
Peak memory 240428 kb
Host smart-253f77d6-6294-4643-83a7-5b41dee0790d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318233145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.318233145
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1515220872
Short name T605
Test name
Test status
Simulation time 311777758 ps
CPU time 3.94 seconds
Started Jun 06 02:42:19 PM PDT 24
Finished Jun 06 02:42:25 PM PDT 24
Peak memory 232780 kb
Host smart-33926756-51e1-4198-8694-7ea4ae3de75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515220872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1515220872
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1028355007
Short name T354
Test name
Test status
Simulation time 36910466 ps
CPU time 2.53 seconds
Started Jun 06 02:42:25 PM PDT 24
Finished Jun 06 02:42:29 PM PDT 24
Peak memory 232492 kb
Host smart-b1426056-d4f1-4044-996e-97c0e24e3f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028355007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1028355007
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3623289276
Short name T866
Test name
Test status
Simulation time 13531139607 ps
CPU time 54.76 seconds
Started Jun 06 02:42:20 PM PDT 24
Finished Jun 06 02:43:17 PM PDT 24
Peak memory 232776 kb
Host smart-c8a22a7c-8384-4085-99d3-bb4934b01121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623289276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3623289276
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.4158166903
Short name T64
Test name
Test status
Simulation time 1634121663 ps
CPU time 4.47 seconds
Started Jun 06 02:42:21 PM PDT 24
Finished Jun 06 02:42:27 PM PDT 24
Peak memory 232764 kb
Host smart-21d8b70b-3508-49dd-801d-e0e2b1e58ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158166903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.4158166903
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1484024866
Short name T875
Test name
Test status
Simulation time 5120116893 ps
CPU time 14.01 seconds
Started Jun 06 02:42:20 PM PDT 24
Finished Jun 06 02:42:36 PM PDT 24
Peak memory 232716 kb
Host smart-839b1dce-0904-4c40-91b7-6a66de15a969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484024866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1484024866
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.23627344
Short name T768
Test name
Test status
Simulation time 2358438456 ps
CPU time 14.12 seconds
Started Jun 06 02:42:17 PM PDT 24
Finished Jun 06 02:42:34 PM PDT 24
Peak memory 222056 kb
Host smart-572e09c9-6bf5-4135-9774-66dc2370763c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=23627344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direc
t.23627344
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.497930520
Short name T599
Test name
Test status
Simulation time 15923409667 ps
CPU time 16.17 seconds
Started Jun 06 02:42:17 PM PDT 24
Finished Jun 06 02:42:35 PM PDT 24
Peak memory 220516 kb
Host smart-b8c63da5-9b59-4ff3-92b8-2b73f83a80a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497930520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.497930520
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2996569009
Short name T689
Test name
Test status
Simulation time 1387282631 ps
CPU time 5.01 seconds
Started Jun 06 02:42:19 PM PDT 24
Finished Jun 06 02:42:26 PM PDT 24
Peak memory 216196 kb
Host smart-cf01ad39-9ece-48fd-8ce7-f45cf81ed47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996569009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2996569009
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2420374497
Short name T425
Test name
Test status
Simulation time 80349820 ps
CPU time 2.05 seconds
Started Jun 06 02:42:18 PM PDT 24
Finished Jun 06 02:42:23 PM PDT 24
Peak memory 216396 kb
Host smart-2e0fcfe9-a63b-4922-bdde-19828445ccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420374497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2420374497
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1634488377
Short name T413
Test name
Test status
Simulation time 31138144 ps
CPU time 0.78 seconds
Started Jun 06 02:42:22 PM PDT 24
Finished Jun 06 02:42:24 PM PDT 24
Peak memory 205808 kb
Host smart-e55aa05e-2fa8-4afb-9bde-cc0404db6a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634488377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1634488377
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3944985723
Short name T761
Test name
Test status
Simulation time 179404748 ps
CPU time 3.61 seconds
Started Jun 06 02:42:18 PM PDT 24
Finished Jun 06 02:42:24 PM PDT 24
Peak memory 224536 kb
Host smart-a9f361c5-3e3b-433e-8f35-045e7eb39387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944985723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3944985723
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.961106997
Short name T496
Test name
Test status
Simulation time 15499009 ps
CPU time 0.71 seconds
Started Jun 06 02:42:28 PM PDT 24
Finished Jun 06 02:42:30 PM PDT 24
Peak memory 204508 kb
Host smart-2fa27fd4-1519-48d3-bc89-833aeffca61b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961106997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.961106997
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.642315805
Short name T954
Test name
Test status
Simulation time 94113813 ps
CPU time 2.9 seconds
Started Jun 06 02:42:39 PM PDT 24
Finished Jun 06 02:42:44 PM PDT 24
Peak memory 227872 kb
Host smart-1849a804-082d-4386-9c72-78be91b55a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642315805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.642315805
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1703211197
Short name T514
Test name
Test status
Simulation time 24099304 ps
CPU time 0.75 seconds
Started Jun 06 02:42:17 PM PDT 24
Finished Jun 06 02:42:20 PM PDT 24
Peak memory 206496 kb
Host smart-2f273a1e-fb86-41ec-95c8-cec2ef4f30da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703211197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1703211197
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1658192894
Short name T270
Test name
Test status
Simulation time 16040169517 ps
CPU time 150.51 seconds
Started Jun 06 02:42:38 PM PDT 24
Finished Jun 06 02:45:11 PM PDT 24
Peak memory 249184 kb
Host smart-e7255895-375b-4bb5-b495-191b4680ab06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658192894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1658192894
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2721868311
Short name T917
Test name
Test status
Simulation time 7287784023 ps
CPU time 50.94 seconds
Started Jun 06 02:42:30 PM PDT 24
Finished Jun 06 02:43:23 PM PDT 24
Peak memory 237852 kb
Host smart-b9af8b52-91c8-4c8f-8da5-a43a1f26a403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721868311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2721868311
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1787968510
Short name T136
Test name
Test status
Simulation time 11035351166 ps
CPU time 108.15 seconds
Started Jun 06 02:42:32 PM PDT 24
Finished Jun 06 02:44:23 PM PDT 24
Peak memory 257444 kb
Host smart-2cf89ec5-5b87-49b7-8f41-c3fe237791c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787968510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1787968510
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2980441277
Short name T310
Test name
Test status
Simulation time 2204379799 ps
CPU time 14.21 seconds
Started Jun 06 02:42:42 PM PDT 24
Finished Jun 06 02:42:59 PM PDT 24
Peak memory 232760 kb
Host smart-975e31e1-e482-4ebf-871f-c2440a03b145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980441277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2980441277
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3362915306
Short name T965
Test name
Test status
Simulation time 245236867 ps
CPU time 5.14 seconds
Started Jun 06 02:42:30 PM PDT 24
Finished Jun 06 02:42:37 PM PDT 24
Peak memory 224444 kb
Host smart-f9ef721f-cce6-4651-bad0-ab30dcd6c48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362915306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3362915306
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.201722749
Short name T309
Test name
Test status
Simulation time 2287376886 ps
CPU time 15.49 seconds
Started Jun 06 02:42:19 PM PDT 24
Finished Jun 06 02:42:37 PM PDT 24
Peak memory 232844 kb
Host smart-d5162992-d40b-40d8-bbbc-49e3fa217260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201722749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.201722749
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1732630916
Short name T21
Test name
Test status
Simulation time 26806052 ps
CPU time 1 seconds
Started Jun 06 02:42:17 PM PDT 24
Finished Jun 06 02:42:20 PM PDT 24
Peak memory 217776 kb
Host smart-1e518c13-7cb9-42bc-be0b-f8f2893ee8da
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732630916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1732630916
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.114587334
Short name T760
Test name
Test status
Simulation time 2100191698 ps
CPU time 3.87 seconds
Started Jun 06 02:42:20 PM PDT 24
Finished Jun 06 02:42:26 PM PDT 24
Peak memory 232760 kb
Host smart-5d0584a6-da9f-48a3-bc95-28c8bfb9afcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114587334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.114587334
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.29400136
Short name T191
Test name
Test status
Simulation time 705108521 ps
CPU time 2.22 seconds
Started Jun 06 02:42:30 PM PDT 24
Finished Jun 06 02:42:35 PM PDT 24
Peak memory 224492 kb
Host smart-3b98371d-e603-4225-9343-07a43cbcd8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29400136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.29400136
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2310964791
Short name T680
Test name
Test status
Simulation time 1215683173 ps
CPU time 15.63 seconds
Started Jun 06 02:42:23 PM PDT 24
Finished Jun 06 02:42:40 PM PDT 24
Peak memory 218716 kb
Host smart-93b8761f-732e-4b96-a862-eea2e67da578
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2310964791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2310964791
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2176794319
Short name T944
Test name
Test status
Simulation time 56959396 ps
CPU time 1.01 seconds
Started Jun 06 02:42:22 PM PDT 24
Finished Jun 06 02:42:25 PM PDT 24
Peak memory 206448 kb
Host smart-abca8ab5-06ea-4e57-8d10-7b5ec5c847e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176794319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2176794319
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1221860763
Short name T462
Test name
Test status
Simulation time 306536384 ps
CPU time 4.49 seconds
Started Jun 06 02:42:28 PM PDT 24
Finished Jun 06 02:42:34 PM PDT 24
Peak memory 217992 kb
Host smart-103aafd2-44a9-44d3-9865-1741cb9d0636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221860763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1221860763
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1572579724
Short name T348
Test name
Test status
Simulation time 931586306 ps
CPU time 6.13 seconds
Started Jun 06 02:42:22 PM PDT 24
Finished Jun 06 02:42:30 PM PDT 24
Peak memory 216232 kb
Host smart-03a83870-21b9-4117-a654-c01c114b9dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572579724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1572579724
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3089857108
Short name T255
Test name
Test status
Simulation time 13718016 ps
CPU time 0.78 seconds
Started Jun 06 02:42:18 PM PDT 24
Finished Jun 06 02:42:21 PM PDT 24
Peak memory 206496 kb
Host smart-342cf5ac-5ca7-406f-a59b-6d920fbc9139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089857108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3089857108
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3901039156
Short name T452
Test name
Test status
Simulation time 459215436 ps
CPU time 0.82 seconds
Started Jun 06 02:42:16 PM PDT 24
Finished Jun 06 02:42:18 PM PDT 24
Peak memory 205760 kb
Host smart-73862487-19de-4628-a157-e2dbdf9a526c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901039156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3901039156
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3124802665
Short name T720
Test name
Test status
Simulation time 6416810749 ps
CPU time 8.57 seconds
Started Jun 06 02:42:34 PM PDT 24
Finished Jun 06 02:42:46 PM PDT 24
Peak memory 224584 kb
Host smart-38151866-f1ff-4ab2-9948-aef2707de9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124802665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3124802665
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2864374402
Short name T366
Test name
Test status
Simulation time 140799547 ps
CPU time 3.23 seconds
Started Jun 06 02:42:28 PM PDT 24
Finished Jun 06 02:42:33 PM PDT 24
Peak memory 232716 kb
Host smart-283aa7f4-8a98-4894-8ca0-491a1c7c5a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864374402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2864374402
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.42270013
Short name T826
Test name
Test status
Simulation time 19687509 ps
CPU time 0.8 seconds
Started Jun 06 02:42:37 PM PDT 24
Finished Jun 06 02:42:41 PM PDT 24
Peak memory 206872 kb
Host smart-ee3ab0d9-e425-4c31-9b5e-0f62ffabb672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42270013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.42270013
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.32198769
Short name T294
Test name
Test status
Simulation time 13162895222 ps
CPU time 109.1 seconds
Started Jun 06 02:42:28 PM PDT 24
Finished Jun 06 02:44:18 PM PDT 24
Peak memory 240104 kb
Host smart-f04fecb7-5d4d-4ab7-bc1e-c1ae4e75af0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32198769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.32198769
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.881621674
Short name T525
Test name
Test status
Simulation time 137055637 ps
CPU time 2.9 seconds
Started Jun 06 02:42:21 PM PDT 24
Finished Jun 06 02:42:26 PM PDT 24
Peak memory 232644 kb
Host smart-b6b9022a-0d37-488f-b737-74e83eddb01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881621674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.881621674
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.665997535
Short name T682
Test name
Test status
Simulation time 1236125546 ps
CPU time 8.83 seconds
Started Jun 06 02:42:20 PM PDT 24
Finished Jun 06 02:42:31 PM PDT 24
Peak memory 224496 kb
Host smart-009cbc51-aaaf-4db5-b856-7677eb640406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665997535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.665997535
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1638602366
Short name T49
Test name
Test status
Simulation time 4489618245 ps
CPU time 31.95 seconds
Started Jun 06 02:42:26 PM PDT 24
Finished Jun 06 02:42:59 PM PDT 24
Peak memory 249188 kb
Host smart-dc0fd95c-6835-4082-8ad0-64f802252b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638602366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1638602366
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3833539288
Short name T455
Test name
Test status
Simulation time 14561876 ps
CPU time 1.05 seconds
Started Jun 06 02:42:30 PM PDT 24
Finished Jun 06 02:42:34 PM PDT 24
Peak memory 217684 kb
Host smart-f3d537ff-a2f5-4b99-a0dc-1da437dd8a44
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833539288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3833539288
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.427778355
Short name T661
Test name
Test status
Simulation time 9760330607 ps
CPU time 7.64 seconds
Started Jun 06 02:42:32 PM PDT 24
Finished Jun 06 02:42:43 PM PDT 24
Peak memory 224528 kb
Host smart-e5c5a57d-553e-46ed-a9aa-c169cf1e9600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427778355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.427778355
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1040630423
Short name T274
Test name
Test status
Simulation time 35509249497 ps
CPU time 27.23 seconds
Started Jun 06 02:42:24 PM PDT 24
Finished Jun 06 02:42:53 PM PDT 24
Peak memory 249104 kb
Host smart-cffbe8df-6dc7-400b-96e9-1ad951ddd7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040630423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1040630423
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1665500791
Short name T685
Test name
Test status
Simulation time 116139309 ps
CPU time 3.16 seconds
Started Jun 06 02:42:29 PM PDT 24
Finished Jun 06 02:42:33 PM PDT 24
Peak memory 220096 kb
Host smart-0ad2f9c4-3d01-4773-a8bd-f1db7923fb60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1665500791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1665500791
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.776708788
Short name T135
Test name
Test status
Simulation time 6771598099 ps
CPU time 75.3 seconds
Started Jun 06 02:42:23 PM PDT 24
Finished Jun 06 02:43:40 PM PDT 24
Peak memory 250416 kb
Host smart-a4b61204-83af-419c-8ecb-d3265a0d90b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776708788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.776708788
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1060450143
Short name T659
Test name
Test status
Simulation time 21161620719 ps
CPU time 26.61 seconds
Started Jun 06 02:42:25 PM PDT 24
Finished Jun 06 02:42:53 PM PDT 24
Peak memory 216424 kb
Host smart-7fa01f30-314f-43ab-be5f-42db7cddc7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060450143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1060450143
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2997595655
Short name T672
Test name
Test status
Simulation time 2618407502 ps
CPU time 5.33 seconds
Started Jun 06 02:42:30 PM PDT 24
Finished Jun 06 02:42:38 PM PDT 24
Peak memory 216312 kb
Host smart-422cabb3-6960-41e1-8f43-cab3aa932103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997595655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2997595655
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2934141653
Short name T936
Test name
Test status
Simulation time 57169980 ps
CPU time 0.86 seconds
Started Jun 06 02:42:32 PM PDT 24
Finished Jun 06 02:42:36 PM PDT 24
Peak memory 206900 kb
Host smart-276c0664-d725-4b6a-a70e-49eb0bfdd210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934141653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2934141653
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.4170348976
Short name T364
Test name
Test status
Simulation time 57364552 ps
CPU time 0.96 seconds
Started Jun 06 02:42:31 PM PDT 24
Finished Jun 06 02:42:35 PM PDT 24
Peak memory 205764 kb
Host smart-ec5a50ec-6c3d-41a7-aac4-c77afcb3e3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170348976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.4170348976
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2251581777
Short name T789
Test name
Test status
Simulation time 8097102771 ps
CPU time 9.06 seconds
Started Jun 06 02:42:29 PM PDT 24
Finished Jun 06 02:42:40 PM PDT 24
Peak memory 232776 kb
Host smart-63710e69-342b-4230-b54b-420e7d393280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251581777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2251581777
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.537160763
Short name T597
Test name
Test status
Simulation time 15550465 ps
CPU time 0.7 seconds
Started Jun 06 02:42:29 PM PDT 24
Finished Jun 06 02:42:32 PM PDT 24
Peak memory 205592 kb
Host smart-3f1361d0-082e-4757-89ca-6a58d9df8c95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537160763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.537160763
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.19837679
Short name T821
Test name
Test status
Simulation time 740912987 ps
CPU time 9.56 seconds
Started Jun 06 02:42:38 PM PDT 24
Finished Jun 06 02:42:50 PM PDT 24
Peak memory 232652 kb
Host smart-57f92e53-3699-421d-af95-c2769ff0d3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19837679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.19837679
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.930505980
Short name T43
Test name
Test status
Simulation time 21744762 ps
CPU time 0.78 seconds
Started Jun 06 02:42:29 PM PDT 24
Finished Jun 06 02:42:32 PM PDT 24
Peak memory 206524 kb
Host smart-1e946735-6da4-4cb8-afa6-d306909e0fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930505980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.930505980
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4230537846
Short name T240
Test name
Test status
Simulation time 40919700291 ps
CPU time 264.7 seconds
Started Jun 06 02:42:24 PM PDT 24
Finished Jun 06 02:46:50 PM PDT 24
Peak memory 249172 kb
Host smart-d9378f15-4fdd-4472-a32d-d0fca1fc2f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230537846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4230537846
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.972210663
Short name T755
Test name
Test status
Simulation time 1608095261 ps
CPU time 6.49 seconds
Started Jun 06 02:42:34 PM PDT 24
Finished Jun 06 02:42:44 PM PDT 24
Peak memory 232736 kb
Host smart-188c897e-0ce0-439b-b360-160361dd5aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972210663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.972210663
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1439095738
Short name T706
Test name
Test status
Simulation time 252633659 ps
CPU time 3.14 seconds
Started Jun 06 02:42:26 PM PDT 24
Finished Jun 06 02:42:30 PM PDT 24
Peak memory 232780 kb
Host smart-150934de-2e71-4a86-8397-e2f3cbc9dbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439095738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1439095738
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2273576827
Short name T697
Test name
Test status
Simulation time 7862560294 ps
CPU time 57.69 seconds
Started Jun 06 02:42:27 PM PDT 24
Finished Jun 06 02:43:26 PM PDT 24
Peak memory 240572 kb
Host smart-3dbdc776-ff7c-404d-bddc-7d3771f1012b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273576827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2273576827
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1503562632
Short name T365
Test name
Test status
Simulation time 29431767 ps
CPU time 1.03 seconds
Started Jun 06 02:42:26 PM PDT 24
Finished Jun 06 02:42:28 PM PDT 24
Peak memory 217768 kb
Host smart-d98df53d-bae1-48ae-b2bc-03667c7c1d51
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503562632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1503562632
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2650892556
Short name T905
Test name
Test status
Simulation time 3243061470 ps
CPU time 10.09 seconds
Started Jun 06 02:42:27 PM PDT 24
Finished Jun 06 02:42:39 PM PDT 24
Peak memory 224540 kb
Host smart-97a7f277-3567-49ce-8031-ab87c9a7e564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650892556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2650892556
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.993221258
Short name T523
Test name
Test status
Simulation time 897151321 ps
CPU time 10.79 seconds
Started Jun 06 02:42:24 PM PDT 24
Finished Jun 06 02:42:36 PM PDT 24
Peak memory 219028 kb
Host smart-2367b5f9-a521-40b9-a0a6-d6b8cafbae3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=993221258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.993221258
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1015739157
Short name T756
Test name
Test status
Simulation time 23590606676 ps
CPU time 55.88 seconds
Started Jun 06 02:42:37 PM PDT 24
Finished Jun 06 02:43:36 PM PDT 24
Peak memory 239484 kb
Host smart-883e8d59-efb3-48d8-9cc4-9f5933a02a8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015739157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1015739157
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1286555893
Short name T610
Test name
Test status
Simulation time 29576532375 ps
CPU time 17.14 seconds
Started Jun 06 02:42:32 PM PDT 24
Finished Jun 06 02:42:53 PM PDT 24
Peak memory 216408 kb
Host smart-4b7cbf50-6c35-4428-9e49-bcf7e85662ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286555893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1286555893
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.4086499584
Short name T899
Test name
Test status
Simulation time 1243902997 ps
CPU time 3.1 seconds
Started Jun 06 02:42:37 PM PDT 24
Finished Jun 06 02:42:42 PM PDT 24
Peak memory 216252 kb
Host smart-76032c64-cf6a-4b93-8d61-f69a7c3a28fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086499584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.4086499584
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1839478302
Short name T340
Test name
Test status
Simulation time 45975800 ps
CPU time 0.9 seconds
Started Jun 06 02:42:23 PM PDT 24
Finished Jun 06 02:42:26 PM PDT 24
Peak memory 206984 kb
Host smart-e104d465-d035-4035-9887-5150d77b0729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839478302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1839478302
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2257623199
Short name T668
Test name
Test status
Simulation time 165984101 ps
CPU time 1.23 seconds
Started Jun 06 02:42:28 PM PDT 24
Finished Jun 06 02:42:31 PM PDT 24
Peak memory 206796 kb
Host smart-fae4c419-ef06-4e27-a4e7-6f44bfdeeb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257623199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2257623199
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.4208711985
Short name T892
Test name
Test status
Simulation time 239558445 ps
CPU time 2.81 seconds
Started Jun 06 02:42:34 PM PDT 24
Finished Jun 06 02:42:40 PM PDT 24
Peak memory 224500 kb
Host smart-0728654b-b693-46e8-bb5d-ea7c7b65636c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208711985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4208711985
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3692330369
Short name T361
Test name
Test status
Simulation time 32035514 ps
CPU time 0.69 seconds
Started Jun 06 02:42:33 PM PDT 24
Finished Jun 06 02:42:37 PM PDT 24
Peak memory 205152 kb
Host smart-2256e233-04df-4aab-9c18-b5eb203238c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692330369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3692330369
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3553650323
Short name T422
Test name
Test status
Simulation time 1080865214 ps
CPU time 4.47 seconds
Started Jun 06 02:42:44 PM PDT 24
Finished Jun 06 02:42:51 PM PDT 24
Peak memory 224460 kb
Host smart-01861f69-0576-40db-af52-ba7130a77016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553650323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3553650323
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.4136720704
Short name T540
Test name
Test status
Simulation time 21940239 ps
CPU time 0.76 seconds
Started Jun 06 02:42:33 PM PDT 24
Finished Jun 06 02:42:38 PM PDT 24
Peak memory 205516 kb
Host smart-a8106edb-b7fa-42e8-bd7d-847535aba826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136720704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4136720704
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3729832052
Short name T194
Test name
Test status
Simulation time 35051926503 ps
CPU time 99.68 seconds
Started Jun 06 02:42:45 PM PDT 24
Finished Jun 06 02:44:27 PM PDT 24
Peak memory 268728 kb
Host smart-033299e9-7e3f-42ad-ad8b-90c5b72bbab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729832052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3729832052
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3493414352
Short name T248
Test name
Test status
Simulation time 68471418603 ps
CPU time 113.89 seconds
Started Jun 06 02:42:25 PM PDT 24
Finished Jun 06 02:44:20 PM PDT 24
Peak memory 240956 kb
Host smart-3471f678-1749-464a-b75d-b06ee744b525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493414352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3493414352
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3029310328
Short name T165
Test name
Test status
Simulation time 22232010521 ps
CPU time 126.58 seconds
Started Jun 06 02:42:30 PM PDT 24
Finished Jun 06 02:44:39 PM PDT 24
Peak memory 255960 kb
Host smart-98a5b6d5-a5fc-4388-a415-a8ec539ee1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029310328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3029310328
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1676184217
Short name T881
Test name
Test status
Simulation time 127977463 ps
CPU time 2.24 seconds
Started Jun 06 02:42:42 PM PDT 24
Finished Jun 06 02:42:48 PM PDT 24
Peak memory 218576 kb
Host smart-35dbaeac-7a23-4e76-89af-d91ca8012422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676184217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1676184217
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3197332075
Short name T908
Test name
Test status
Simulation time 4116995935 ps
CPU time 16.75 seconds
Started Jun 06 02:42:28 PM PDT 24
Finished Jun 06 02:42:46 PM PDT 24
Peak memory 236240 kb
Host smart-c4b711bb-8ea5-4d4e-a1e7-6676323ad77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197332075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3197332075
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3817169925
Short name T454
Test name
Test status
Simulation time 16716490 ps
CPU time 1.03 seconds
Started Jun 06 02:42:45 PM PDT 24
Finished Jun 06 02:42:49 PM PDT 24
Peak memory 216456 kb
Host smart-a3128ca5-77fc-4d71-932c-d92f611341cf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817169925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3817169925
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.393108658
Short name T216
Test name
Test status
Simulation time 1015881066 ps
CPU time 6.97 seconds
Started Jun 06 02:42:24 PM PDT 24
Finished Jun 06 02:42:32 PM PDT 24
Peak memory 232696 kb
Host smart-e39d7cb4-4776-4795-9cc2-df77a1d45ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393108658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.393108658
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2053227583
Short name T518
Test name
Test status
Simulation time 8879721933 ps
CPU time 12.4 seconds
Started Jun 06 02:42:43 PM PDT 24
Finished Jun 06 02:42:58 PM PDT 24
Peak memory 248548 kb
Host smart-956e6078-dfc4-4adb-bfa0-a18cb89d9a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053227583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2053227583
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.336922615
Short name T70
Test name
Test status
Simulation time 631786060 ps
CPU time 3.57 seconds
Started Jun 06 02:42:42 PM PDT 24
Finished Jun 06 02:42:49 PM PDT 24
Peak memory 221792 kb
Host smart-e5a30d4f-03de-425f-866d-144f2b6b1e8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=336922615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.336922615
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1738475486
Short name T155
Test name
Test status
Simulation time 191517998 ps
CPU time 1.06 seconds
Started Jun 06 02:42:31 PM PDT 24
Finished Jun 06 02:42:34 PM PDT 24
Peak memory 207212 kb
Host smart-62c62213-7405-4d05-92e2-9fba528a497c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738475486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1738475486
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4241900249
Short name T890
Test name
Test status
Simulation time 15743990673 ps
CPU time 17.79 seconds
Started Jun 06 02:42:26 PM PDT 24
Finished Jun 06 02:42:46 PM PDT 24
Peak memory 216468 kb
Host smart-a6fb170c-6df6-4b8d-a95f-77d451164aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241900249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4241900249
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2982810205
Short name T362
Test name
Test status
Simulation time 963534080 ps
CPU time 4.35 seconds
Started Jun 06 02:42:29 PM PDT 24
Finished Jun 06 02:42:36 PM PDT 24
Peak memory 216268 kb
Host smart-89708915-1e36-4090-806b-830cab3aabb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982810205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2982810205
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.4006503716
Short name T818
Test name
Test status
Simulation time 74836276 ps
CPU time 1.06 seconds
Started Jun 06 02:42:28 PM PDT 24
Finished Jun 06 02:42:30 PM PDT 24
Peak memory 207020 kb
Host smart-4b1aee60-4e88-482f-b09f-7e569557d4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006503716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4006503716
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2141345492
Short name T687
Test name
Test status
Simulation time 50216440 ps
CPU time 0.7 seconds
Started Jun 06 02:42:29 PM PDT 24
Finished Jun 06 02:42:32 PM PDT 24
Peak memory 205796 kb
Host smart-d813fa4d-0755-4211-998b-8ebde91e2fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141345492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2141345492
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1821579269
Short name T927
Test name
Test status
Simulation time 10153224089 ps
CPU time 16.56 seconds
Started Jun 06 02:42:35 PM PDT 24
Finished Jun 06 02:42:55 PM PDT 24
Peak memory 224584 kb
Host smart-54b9ee74-abe1-4972-9701-c0e9ad439481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821579269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1821579269
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2966025337
Short name T827
Test name
Test status
Simulation time 11595736 ps
CPU time 0.7 seconds
Started Jun 06 02:42:42 PM PDT 24
Finished Jun 06 02:42:45 PM PDT 24
Peak memory 204652 kb
Host smart-a576f20a-5531-4b16-afd1-af03af3a4c3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966025337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2966025337
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3457669525
Short name T486
Test name
Test status
Simulation time 318357598 ps
CPU time 3.09 seconds
Started Jun 06 02:42:32 PM PDT 24
Finished Jun 06 02:42:38 PM PDT 24
Peak memory 232796 kb
Host smart-8e5e60de-e44e-491f-9739-03694eb75450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457669525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3457669525
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1017818541
Short name T686
Test name
Test status
Simulation time 38565037 ps
CPU time 0.76 seconds
Started Jun 06 02:42:42 PM PDT 24
Finished Jun 06 02:42:46 PM PDT 24
Peak memory 205492 kb
Host smart-c89b6ab4-35ef-4ac1-b186-89253df2309f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017818541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1017818541
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1889245893
Short name T268
Test name
Test status
Simulation time 8230219949 ps
CPU time 59.74 seconds
Started Jun 06 02:42:33 PM PDT 24
Finished Jun 06 02:43:36 PM PDT 24
Peak memory 239428 kb
Host smart-78248c2b-986e-4fd1-b033-09f4bbaf0cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889245893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1889245893
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.332479156
Short name T387
Test name
Test status
Simulation time 7716710850 ps
CPU time 109.94 seconds
Started Jun 06 02:42:32 PM PDT 24
Finished Jun 06 02:44:25 PM PDT 24
Peak memory 256012 kb
Host smart-d1810570-ce65-4b12-bcd8-58d1b07bfd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332479156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.332479156
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2604027273
Short name T280
Test name
Test status
Simulation time 114174114679 ps
CPU time 448.81 seconds
Started Jun 06 02:42:34 PM PDT 24
Finished Jun 06 02:50:06 PM PDT 24
Peak memory 257500 kb
Host smart-3cab3edc-0d22-436c-9f4e-2de6c5d32605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604027273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2604027273
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_intercept.616366423
Short name T628
Test name
Test status
Simulation time 1872528066 ps
CPU time 10.26 seconds
Started Jun 06 02:42:31 PM PDT 24
Finished Jun 06 02:42:45 PM PDT 24
Peak memory 224576 kb
Host smart-8b2fc05d-42a3-4106-8e0b-da9880d93028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616366423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.616366423
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.956482761
Short name T282
Test name
Test status
Simulation time 270062818 ps
CPU time 2.98 seconds
Started Jun 06 02:42:40 PM PDT 24
Finished Jun 06 02:42:45 PM PDT 24
Peak memory 224440 kb
Host smart-ba371b7b-5bb4-49f0-aba3-9a092818b19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956482761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.956482761
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1289430821
Short name T20
Test name
Test status
Simulation time 31004963 ps
CPU time 1.13 seconds
Started Jun 06 02:42:47 PM PDT 24
Finished Jun 06 02:42:50 PM PDT 24
Peak memory 216516 kb
Host smart-8efcd875-ac56-45f1-9861-a054175f1d65
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289430821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1289430821
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2142167697
Short name T724
Test name
Test status
Simulation time 864242896 ps
CPU time 4.42 seconds
Started Jun 06 02:42:42 PM PDT 24
Finished Jun 06 02:42:49 PM PDT 24
Peak memory 232732 kb
Host smart-07db34f0-2c37-4fe2-8856-6a1c777fd9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142167697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2142167697
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3051204048
Short name T933
Test name
Test status
Simulation time 2836629026 ps
CPU time 4.14 seconds
Started Jun 06 02:42:33 PM PDT 24
Finished Jun 06 02:42:40 PM PDT 24
Peak memory 224552 kb
Host smart-3fbd6626-0e9c-4528-8cde-09a62cd0b61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051204048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3051204048
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.358259699
Short name T796
Test name
Test status
Simulation time 3941671758 ps
CPU time 9.14 seconds
Started Jun 06 02:42:44 PM PDT 24
Finished Jun 06 02:42:56 PM PDT 24
Peak memory 220396 kb
Host smart-54449ccd-648d-4fba-93f5-74b3ba96d2ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=358259699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.358259699
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2868068404
Short name T243
Test name
Test status
Simulation time 7791695751 ps
CPU time 61.33 seconds
Started Jun 06 02:42:36 PM PDT 24
Finished Jun 06 02:43:40 PM PDT 24
Peak memory 253976 kb
Host smart-61bd0120-060e-45d8-993a-80ac8394f439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868068404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2868068404
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.599135692
Short name T652
Test name
Test status
Simulation time 768938055 ps
CPU time 5.68 seconds
Started Jun 06 02:42:37 PM PDT 24
Finished Jun 06 02:42:45 PM PDT 24
Peak memory 216284 kb
Host smart-a017cf29-744b-4a23-b7f7-665976e2ab8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599135692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.599135692
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1629321862
Short name T395
Test name
Test status
Simulation time 36629037061 ps
CPU time 13.7 seconds
Started Jun 06 02:42:32 PM PDT 24
Finished Jun 06 02:42:49 PM PDT 24
Peak memory 217324 kb
Host smart-4c22a5ac-1718-438c-b039-768131108103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629321862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1629321862
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.4107877006
Short name T341
Test name
Test status
Simulation time 62054906 ps
CPU time 1.48 seconds
Started Jun 06 02:42:45 PM PDT 24
Finished Jun 06 02:42:50 PM PDT 24
Peak memory 216308 kb
Host smart-d0b21562-8841-4afa-9421-13dbdbab2436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107877006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.4107877006
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1545062183
Short name T655
Test name
Test status
Simulation time 33203816 ps
CPU time 0.74 seconds
Started Jun 06 02:42:34 PM PDT 24
Finished Jun 06 02:42:38 PM PDT 24
Peak memory 205812 kb
Host smart-1cff7d3d-fe06-4516-b3cb-5f3a9ad513c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545062183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1545062183
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1490223420
Short name T798
Test name
Test status
Simulation time 32572101168 ps
CPU time 24.8 seconds
Started Jun 06 02:42:38 PM PDT 24
Finished Jun 06 02:43:05 PM PDT 24
Peak memory 232788 kb
Host smart-06e811a5-ede7-4a81-b2dd-07a10218dea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490223420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1490223420
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3787528365
Short name T461
Test name
Test status
Simulation time 36250164 ps
CPU time 0.71 seconds
Started Jun 06 02:42:31 PM PDT 24
Finished Jun 06 02:42:34 PM PDT 24
Peak memory 205512 kb
Host smart-5bfb4959-a8a2-41c6-b9f3-feb0094bd751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787528365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3787528365
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.732118492
Short name T122
Test name
Test status
Simulation time 3405718517 ps
CPU time 7.69 seconds
Started Jun 06 02:42:38 PM PDT 24
Finished Jun 06 02:42:48 PM PDT 24
Peak memory 224644 kb
Host smart-754ec6df-b2dd-4939-b357-b4e596e06ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732118492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.732118492
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2671519347
Short name T563
Test name
Test status
Simulation time 77195848 ps
CPU time 0.78 seconds
Started Jun 06 02:42:44 PM PDT 24
Finished Jun 06 02:42:48 PM PDT 24
Peak memory 206488 kb
Host smart-919e6169-4677-45f2-9b33-24c2512e2abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671519347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2671519347
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2898863176
Short name T749
Test name
Test status
Simulation time 32311322724 ps
CPU time 95.57 seconds
Started Jun 06 02:42:37 PM PDT 24
Finished Jun 06 02:44:15 PM PDT 24
Peak memory 238988 kb
Host smart-b3812cdb-c5b1-4b62-8c77-f73d8c84b385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898863176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2898863176
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2361481035
Short name T42
Test name
Test status
Simulation time 132740600116 ps
CPU time 258.91 seconds
Started Jun 06 02:42:42 PM PDT 24
Finished Jun 06 02:47:04 PM PDT 24
Peak memory 250372 kb
Host smart-4125fd2b-58e1-4bd0-a573-813846a7ef0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361481035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2361481035
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.280773712
Short name T831
Test name
Test status
Simulation time 13366270321 ps
CPU time 148.86 seconds
Started Jun 06 02:42:41 PM PDT 24
Finished Jun 06 02:45:13 PM PDT 24
Peak memory 257512 kb
Host smart-8242ce5b-e64d-467e-b952-3a45a444cb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280773712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.280773712
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.504199903
Short name T78
Test name
Test status
Simulation time 1082393676 ps
CPU time 12.38 seconds
Started Jun 06 02:42:33 PM PDT 24
Finished Jun 06 02:42:49 PM PDT 24
Peak memory 232740 kb
Host smart-191dc1dc-44d1-4673-acf6-9d14bd56035d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504199903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.504199903
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1878051227
Short name T898
Test name
Test status
Simulation time 196409557 ps
CPU time 4.58 seconds
Started Jun 06 02:42:45 PM PDT 24
Finished Jun 06 02:42:52 PM PDT 24
Peak memory 224472 kb
Host smart-17ea8ea1-9e52-4b70-9b3a-113ac2ff48e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878051227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1878051227
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3748992484
Short name T921
Test name
Test status
Simulation time 3280367456 ps
CPU time 12.95 seconds
Started Jun 06 02:42:46 PM PDT 24
Finished Jun 06 02:43:02 PM PDT 24
Peak memory 234856 kb
Host smart-2224ec3c-ac40-4681-90f4-0f281cc8cd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748992484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3748992484
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3575757738
Short name T678
Test name
Test status
Simulation time 90008333 ps
CPU time 1.06 seconds
Started Jun 06 02:42:37 PM PDT 24
Finished Jun 06 02:42:40 PM PDT 24
Peak memory 216532 kb
Host smart-6385ae58-ac89-4391-9e13-85e17c635270
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575757738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3575757738
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2684058223
Short name T266
Test name
Test status
Simulation time 211528244 ps
CPU time 3.16 seconds
Started Jun 06 02:42:36 PM PDT 24
Finished Jun 06 02:42:42 PM PDT 24
Peak memory 232744 kb
Host smart-26e1ef1f-0231-4872-be0b-688f385f5df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684058223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2684058223
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.308019523
Short name T160
Test name
Test status
Simulation time 2731908771 ps
CPU time 5.62 seconds
Started Jun 06 02:42:36 PM PDT 24
Finished Jun 06 02:42:45 PM PDT 24
Peak memory 232788 kb
Host smart-1f40bd56-f5dd-4f0e-9cc9-84eb20af265b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308019523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.308019523
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.96575072
Short name T852
Test name
Test status
Simulation time 1891423358 ps
CPU time 14.68 seconds
Started Jun 06 02:42:32 PM PDT 24
Finished Jun 06 02:42:50 PM PDT 24
Peak memory 222836 kb
Host smart-455e77e7-e0be-4d49-9b00-19de1b3176f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=96575072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direc
t.96575072
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.368595506
Short name T578
Test name
Test status
Simulation time 385731407639 ps
CPU time 629.31 seconds
Started Jun 06 02:42:49 PM PDT 24
Finished Jun 06 02:53:21 PM PDT 24
Peak memory 261580 kb
Host smart-acb96e91-9051-459d-ae11-5e1778d3f722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368595506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.368595506
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.303580674
Short name T471
Test name
Test status
Simulation time 11948539513 ps
CPU time 59.18 seconds
Started Jun 06 02:42:42 PM PDT 24
Finished Jun 06 02:43:44 PM PDT 24
Peak memory 216380 kb
Host smart-c1ea88dc-51f5-4e2b-8bc9-9a14d31c3c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303580674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.303580674
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3774954069
Short name T389
Test name
Test status
Simulation time 19799802701 ps
CPU time 7.76 seconds
Started Jun 06 02:42:31 PM PDT 24
Finished Jun 06 02:42:41 PM PDT 24
Peak memory 216296 kb
Host smart-c1b9152b-b96c-44f9-bbed-b95b9686d192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774954069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3774954069
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.410997125
Short name T532
Test name
Test status
Simulation time 38326225 ps
CPU time 1.14 seconds
Started Jun 06 02:42:33 PM PDT 24
Finished Jun 06 02:42:38 PM PDT 24
Peak memory 216328 kb
Host smart-2a16a355-cb6b-45b3-9cdc-a182be48ecb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410997125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.410997125
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4191173601
Short name T420
Test name
Test status
Simulation time 103166576 ps
CPU time 0.78 seconds
Started Jun 06 02:42:31 PM PDT 24
Finished Jun 06 02:42:35 PM PDT 24
Peak memory 205776 kb
Host smart-03680812-37cb-4195-b9b3-b56ea2c2e685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191173601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4191173601
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1511588258
Short name T488
Test name
Test status
Simulation time 121750911 ps
CPU time 2.23 seconds
Started Jun 06 02:42:44 PM PDT 24
Finished Jun 06 02:42:49 PM PDT 24
Peak memory 223816 kb
Host smart-ac168e7c-d71d-4d1a-aa30-ac9a03ed746b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511588258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1511588258
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.175734022
Short name T935
Test name
Test status
Simulation time 185169119 ps
CPU time 0.74 seconds
Started Jun 06 02:42:41 PM PDT 24
Finished Jun 06 02:42:44 PM PDT 24
Peak memory 205196 kb
Host smart-aa6d6064-b8ea-47e1-b3a0-a8f8074be8be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175734022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.175734022
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2024258370
Short name T726
Test name
Test status
Simulation time 274010984 ps
CPU time 4.95 seconds
Started Jun 06 02:42:40 PM PDT 24
Finished Jun 06 02:42:48 PM PDT 24
Peak memory 224556 kb
Host smart-e5d56bdf-80b6-4630-832f-f08ce4ea429f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024258370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2024258370
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2821494961
Short name T841
Test name
Test status
Simulation time 17634791 ps
CPU time 0.79 seconds
Started Jun 06 02:42:35 PM PDT 24
Finished Jun 06 02:42:39 PM PDT 24
Peak memory 206476 kb
Host smart-18f51a1c-f9d0-4e11-8dca-a2655f51940d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821494961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2821494961
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.242730402
Short name T883
Test name
Test status
Simulation time 2613892389 ps
CPU time 17.43 seconds
Started Jun 06 02:42:42 PM PDT 24
Finished Jun 06 02:43:03 PM PDT 24
Peak memory 233736 kb
Host smart-91acc8b5-8623-480c-b8ca-b2924bbc0032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242730402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.242730402
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2134742553
Short name T625
Test name
Test status
Simulation time 67591231543 ps
CPU time 129.3 seconds
Started Jun 06 02:42:49 PM PDT 24
Finished Jun 06 02:45:01 PM PDT 24
Peak memory 249300 kb
Host smart-59c58543-cf5f-4702-9d68-50721ca9aa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134742553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2134742553
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1949751871
Short name T690
Test name
Test status
Simulation time 1615861093 ps
CPU time 17.34 seconds
Started Jun 06 02:42:44 PM PDT 24
Finished Jun 06 02:43:04 PM PDT 24
Peak memory 232784 kb
Host smart-b4369ab5-1cc7-40e2-a48a-483160c4f9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949751871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1949751871
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3757752351
Short name T961
Test name
Test status
Simulation time 1532109086 ps
CPU time 16.6 seconds
Started Jun 06 02:42:43 PM PDT 24
Finished Jun 06 02:43:02 PM PDT 24
Peak memory 232756 kb
Host smart-ce676b1b-4cb2-48a4-a6e6-e1cc36a5cfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757752351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3757752351
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2888414078
Short name T206
Test name
Test status
Simulation time 1357811174 ps
CPU time 20.12 seconds
Started Jun 06 02:42:44 PM PDT 24
Finished Jun 06 02:43:07 PM PDT 24
Peak memory 240412 kb
Host smart-dd53c935-687f-4992-b5f5-7c64e7521bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888414078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2888414078
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1940239393
Short name T393
Test name
Test status
Simulation time 230834831 ps
CPU time 1.08 seconds
Started Jun 06 02:42:36 PM PDT 24
Finished Jun 06 02:42:40 PM PDT 24
Peak memory 216528 kb
Host smart-88cd1f83-d1c1-4a5a-8cb3-ac9ae38f1a41
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940239393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1940239393
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.954133778
Short name T589
Test name
Test status
Simulation time 675515815 ps
CPU time 5.54 seconds
Started Jun 06 02:42:40 PM PDT 24
Finished Jun 06 02:42:48 PM PDT 24
Peak memory 224532 kb
Host smart-40608506-d7ba-4f34-b66f-a1a27f021b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954133778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.954133778
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.322647798
Short name T85
Test name
Test status
Simulation time 2279542649 ps
CPU time 10.85 seconds
Started Jun 06 02:42:41 PM PDT 24
Finished Jun 06 02:42:54 PM PDT 24
Peak memory 224524 kb
Host smart-a1eba125-4eac-4b56-9d28-d7c1a6ffa474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322647798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.322647798
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3196495226
Short name T916
Test name
Test status
Simulation time 854472025 ps
CPU time 8.07 seconds
Started Jun 06 02:42:46 PM PDT 24
Finished Jun 06 02:42:57 PM PDT 24
Peak memory 222252 kb
Host smart-b405c3ba-4518-4bf9-b942-d5c9ed4e2883
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3196495226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3196495226
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3069840976
Short name T337
Test name
Test status
Simulation time 2056633605 ps
CPU time 10.53 seconds
Started Jun 06 02:42:41 PM PDT 24
Finished Jun 06 02:42:54 PM PDT 24
Peak memory 216380 kb
Host smart-b57792b2-1961-4e21-b7ab-340454014566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069840976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3069840976
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.920032528
Short name T856
Test name
Test status
Simulation time 7180435587 ps
CPU time 8.24 seconds
Started Jun 06 02:42:32 PM PDT 24
Finished Jun 06 02:42:43 PM PDT 24
Peak memory 216320 kb
Host smart-79de0961-8db1-4923-8d72-2d291c96f1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920032528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.920032528
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3060799340
Short name T824
Test name
Test status
Simulation time 2151341731 ps
CPU time 1.97 seconds
Started Jun 06 02:42:40 PM PDT 24
Finished Jun 06 02:42:45 PM PDT 24
Peak memory 216384 kb
Host smart-7b946d83-a866-4062-abfe-8214ea16b950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060799340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3060799340
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3771080858
Short name T735
Test name
Test status
Simulation time 387773676 ps
CPU time 0.85 seconds
Started Jun 06 02:42:40 PM PDT 24
Finished Jun 06 02:42:43 PM PDT 24
Peak memory 205736 kb
Host smart-db0a2edd-de8a-44aa-8360-875768a94816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771080858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3771080858
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.4226108074
Short name T213
Test name
Test status
Simulation time 1124186259 ps
CPU time 7.57 seconds
Started Jun 06 02:42:46 PM PDT 24
Finished Jun 06 02:42:56 PM PDT 24
Peak memory 232728 kb
Host smart-75bc4c2c-4926-47e0-8ef0-5219fdb77781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226108074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4226108074
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1660540780
Short name T404
Test name
Test status
Simulation time 55961834 ps
CPU time 0.72 seconds
Started Jun 06 02:42:49 PM PDT 24
Finished Jun 06 02:42:53 PM PDT 24
Peak memory 204568 kb
Host smart-0f406feb-11ba-4aeb-8c3c-a19b208a0aa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660540780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1660540780
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1697231178
Short name T297
Test name
Test status
Simulation time 236388268 ps
CPU time 2.49 seconds
Started Jun 06 02:42:45 PM PDT 24
Finished Jun 06 02:42:51 PM PDT 24
Peak memory 224416 kb
Host smart-10fe6a99-5335-4f64-8c3b-b0eec17a64d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697231178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1697231178
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.271312018
Short name T634
Test name
Test status
Simulation time 17491031 ps
CPU time 0.75 seconds
Started Jun 06 02:42:45 PM PDT 24
Finished Jun 06 02:42:49 PM PDT 24
Peak memory 205472 kb
Host smart-79df9bf9-6cfc-4ef0-83fc-a72306afc4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271312018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.271312018
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2743236763
Short name T291
Test name
Test status
Simulation time 122316365646 ps
CPU time 226.78 seconds
Started Jun 06 02:42:42 PM PDT 24
Finished Jun 06 02:46:31 PM PDT 24
Peak memory 252716 kb
Host smart-84e00b42-680d-4315-a3d2-9e890c55b9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743236763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2743236763
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4111829032
Short name T247
Test name
Test status
Simulation time 77033639281 ps
CPU time 167.03 seconds
Started Jun 06 02:42:41 PM PDT 24
Finished Jun 06 02:45:30 PM PDT 24
Peak memory 256200 kb
Host smart-5dee6a22-7644-4a11-8524-6f44ceb28bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111829032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4111829032
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3734009321
Short name T725
Test name
Test status
Simulation time 5004616716 ps
CPU time 69.44 seconds
Started Jun 06 02:42:49 PM PDT 24
Finished Jun 06 02:44:01 PM PDT 24
Peak memory 239552 kb
Host smart-352c00e6-22a3-460b-baed-772984b46abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734009321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3734009321
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1324436110
Short name T627
Test name
Test status
Simulation time 149042461 ps
CPU time 4.79 seconds
Started Jun 06 02:42:47 PM PDT 24
Finished Jun 06 02:42:54 PM PDT 24
Peak memory 224532 kb
Host smart-12eb880e-e494-419f-91c3-24d1f906c655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324436110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1324436110
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2277324285
Short name T272
Test name
Test status
Simulation time 8127252694 ps
CPU time 17.54 seconds
Started Jun 06 02:43:05 PM PDT 24
Finished Jun 06 02:43:25 PM PDT 24
Peak memory 224568 kb
Host smart-d6516969-59c0-4b9c-8504-b8b743a71d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277324285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2277324285
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.694671307
Short name T188
Test name
Test status
Simulation time 7611389489 ps
CPU time 63.05 seconds
Started Jun 06 02:42:49 PM PDT 24
Finished Jun 06 02:43:55 PM PDT 24
Peak memory 232788 kb
Host smart-194a5a91-247b-46cd-b2f9-d2cd1a7fd065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694671307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.694671307
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3646587328
Short name T733
Test name
Test status
Simulation time 17033648 ps
CPU time 1.01 seconds
Started Jun 06 02:42:40 PM PDT 24
Finished Jun 06 02:42:44 PM PDT 24
Peak memory 217716 kb
Host smart-020d6cc1-0421-4c35-8740-5f2a2d9f2f76
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646587328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3646587328
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.902705384
Short name T958
Test name
Test status
Simulation time 3971479467 ps
CPU time 9.76 seconds
Started Jun 06 02:42:45 PM PDT 24
Finished Jun 06 02:42:58 PM PDT 24
Peak memory 240620 kb
Host smart-4e5b583b-591f-4e7a-8e88-b3a4077cc187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902705384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.902705384
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.192430453
Short name T629
Test name
Test status
Simulation time 3616390195 ps
CPU time 6.41 seconds
Started Jun 06 02:42:48 PM PDT 24
Finished Jun 06 02:42:57 PM PDT 24
Peak memory 232768 kb
Host smart-aa3ca043-3351-4700-bc54-615e76b938a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192430453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.192430453
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.4087999912
Short name T925
Test name
Test status
Simulation time 1000666534 ps
CPU time 6.39 seconds
Started Jun 06 02:42:46 PM PDT 24
Finished Jun 06 02:42:55 PM PDT 24
Peak memory 219232 kb
Host smart-34668b87-14ef-4512-a671-e0dae53d836d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4087999912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.4087999912
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.191326733
Short name T134
Test name
Test status
Simulation time 27879263050 ps
CPU time 239.2 seconds
Started Jun 06 02:42:45 PM PDT 24
Finished Jun 06 02:46:47 PM PDT 24
Peak memory 250712 kb
Host smart-8ab2dc88-9ff4-4c65-b121-46287bc96718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191326733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.191326733
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2179105678
Short name T509
Test name
Test status
Simulation time 22690727775 ps
CPU time 23.99 seconds
Started Jun 06 02:42:41 PM PDT 24
Finished Jun 06 02:43:07 PM PDT 24
Peak memory 216416 kb
Host smart-1520602c-8db2-4fa3-a953-7c3ba5f38573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179105678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2179105678
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3902329173
Short name T753
Test name
Test status
Simulation time 10614459063 ps
CPU time 14.82 seconds
Started Jun 06 02:42:49 PM PDT 24
Finished Jun 06 02:43:06 PM PDT 24
Peak memory 216304 kb
Host smart-12fef6e3-28fa-4b9b-a789-f42e42c3c223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902329173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3902329173
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3230718883
Short name T960
Test name
Test status
Simulation time 147209844 ps
CPU time 0.92 seconds
Started Jun 06 02:42:53 PM PDT 24
Finished Jun 06 02:42:56 PM PDT 24
Peak memory 206704 kb
Host smart-f3f9a7eb-44ac-4789-adf8-de49256f20e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230718883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3230718883
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.652929750
Short name T665
Test name
Test status
Simulation time 18498338 ps
CPU time 0.72 seconds
Started Jun 06 02:42:47 PM PDT 24
Finished Jun 06 02:42:50 PM PDT 24
Peak memory 205792 kb
Host smart-e50ce467-8aad-4c99-a6bf-d169b48d16e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652929750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.652929750
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1232851188
Short name T664
Test name
Test status
Simulation time 2593980792 ps
CPU time 9.1 seconds
Started Jun 06 02:42:42 PM PDT 24
Finished Jun 06 02:42:54 PM PDT 24
Peak memory 224608 kb
Host smart-41b07935-89db-4b79-964c-d1f4c2b1b2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232851188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1232851188
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1038640589
Short name T363
Test name
Test status
Simulation time 93009670 ps
CPU time 0.7 seconds
Started Jun 06 02:42:53 PM PDT 24
Finished Jun 06 02:42:55 PM PDT 24
Peak memory 205160 kb
Host smart-4312f0af-a034-4095-962a-61c59dd287fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038640589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1038640589
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1621653351
Short name T571
Test name
Test status
Simulation time 900321367 ps
CPU time 3.97 seconds
Started Jun 06 02:42:50 PM PDT 24
Finished Jun 06 02:42:57 PM PDT 24
Peak memory 224508 kb
Host smart-6f25b117-1234-4cae-9cef-c984a2d87fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621653351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1621653351
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1456051011
Short name T558
Test name
Test status
Simulation time 22796089 ps
CPU time 0.8 seconds
Started Jun 06 02:42:52 PM PDT 24
Finished Jun 06 02:42:55 PM PDT 24
Peak memory 206484 kb
Host smart-e5d90414-500e-47f0-9717-103292b3865b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456051011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1456051011
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1806270994
Short name T717
Test name
Test status
Simulation time 103487421553 ps
CPU time 193.69 seconds
Started Jun 06 02:42:49 PM PDT 24
Finished Jun 06 02:46:05 PM PDT 24
Peak memory 249248 kb
Host smart-6dbc87f7-e149-4132-b137-c6c911d4ab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806270994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1806270994
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2402637383
Short name T431
Test name
Test status
Simulation time 6045324578 ps
CPU time 40.66 seconds
Started Jun 06 02:42:48 PM PDT 24
Finished Jun 06 02:43:31 PM PDT 24
Peak memory 224704 kb
Host smart-33fb3ea7-57e5-4a3f-a7ff-d5f7902e2f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402637383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2402637383
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2404055739
Short name T790
Test name
Test status
Simulation time 3365243428 ps
CPU time 33.68 seconds
Started Jun 06 02:42:44 PM PDT 24
Finished Jun 06 02:43:21 PM PDT 24
Peak memory 238724 kb
Host smart-f700e889-0162-4a9d-9aee-fbfeacfbcdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404055739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2404055739
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1599883700
Short name T586
Test name
Test status
Simulation time 758802472 ps
CPU time 6.11 seconds
Started Jun 06 02:42:48 PM PDT 24
Finished Jun 06 02:42:57 PM PDT 24
Peak memory 232688 kb
Host smart-69b935ed-b68d-4de5-9730-27db57c72c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599883700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1599883700
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2328041491
Short name T498
Test name
Test status
Simulation time 4135853690 ps
CPU time 10.92 seconds
Started Jun 06 02:42:53 PM PDT 24
Finished Jun 06 02:43:06 PM PDT 24
Peak memory 232756 kb
Host smart-0500a6ed-1dc0-4399-a8d3-fc259716fd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328041491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2328041491
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3433860057
Short name T357
Test name
Test status
Simulation time 111098664 ps
CPU time 1.1 seconds
Started Jun 06 02:42:40 PM PDT 24
Finished Jun 06 02:42:44 PM PDT 24
Peak memory 217756 kb
Host smart-d52be45d-00aa-4b12-9472-1558aace16e6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433860057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3433860057
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1006837297
Short name T305
Test name
Test status
Simulation time 83255055 ps
CPU time 2.61 seconds
Started Jun 06 02:42:48 PM PDT 24
Finished Jun 06 02:42:53 PM PDT 24
Peak memory 232716 kb
Host smart-ae1f1195-96a6-4bc4-ad94-28a018791e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006837297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1006837297
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.4066015006
Short name T759
Test name
Test status
Simulation time 218451705 ps
CPU time 5.33 seconds
Started Jun 06 02:42:42 PM PDT 24
Finished Jun 06 02:42:51 PM PDT 24
Peak memory 232556 kb
Host smart-69314b92-743a-401b-821e-a9240775c67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066015006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.4066015006
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4049171059
Short name T776
Test name
Test status
Simulation time 1565701637 ps
CPU time 6.05 seconds
Started Jun 06 02:42:49 PM PDT 24
Finished Jun 06 02:42:58 PM PDT 24
Peak memory 218720 kb
Host smart-9378b060-9f3d-438b-af7a-ffbde442954d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4049171059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4049171059
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3641937056
Short name T150
Test name
Test status
Simulation time 356901563910 ps
CPU time 354.56 seconds
Started Jun 06 02:42:48 PM PDT 24
Finished Jun 06 02:48:45 PM PDT 24
Peak memory 263376 kb
Host smart-87a5af3b-dd18-4040-8480-e779cde172a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641937056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3641937056
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1838671111
Short name T707
Test name
Test status
Simulation time 854254515 ps
CPU time 4.92 seconds
Started Jun 06 02:42:47 PM PDT 24
Finished Jun 06 02:42:55 PM PDT 24
Peak memory 216376 kb
Host smart-e14763bd-aace-4a07-94f9-f953d2745637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838671111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1838671111
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.4153216398
Short name T671
Test name
Test status
Simulation time 34606462882 ps
CPU time 21.85 seconds
Started Jun 06 02:42:46 PM PDT 24
Finished Jun 06 02:43:11 PM PDT 24
Peak memory 217504 kb
Host smart-7686dcf9-d2e5-48ac-86b4-5e37b977e1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153216398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4153216398
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.4139538769
Short name T679
Test name
Test status
Simulation time 922091207 ps
CPU time 8.75 seconds
Started Jun 06 02:42:48 PM PDT 24
Finished Jun 06 02:42:59 PM PDT 24
Peak memory 216312 kb
Host smart-736ebfdf-306a-4b96-a336-51c55e23b8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139538769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.4139538769
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2263454781
Short name T494
Test name
Test status
Simulation time 81090664 ps
CPU time 1 seconds
Started Jun 06 02:42:46 PM PDT 24
Finished Jun 06 02:42:49 PM PDT 24
Peak memory 206800 kb
Host smart-0d713101-513b-46b1-b98d-6395747e215b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263454781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2263454781
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.4011024328
Short name T957
Test name
Test status
Simulation time 1916710282 ps
CPU time 6.9 seconds
Started Jun 06 02:42:44 PM PDT 24
Finished Jun 06 02:42:54 PM PDT 24
Peak memory 224568 kb
Host smart-e7eeb96d-0c9c-4d5b-92cf-7bcdb733f116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011024328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.4011024328
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3687599352
Short name T4
Test name
Test status
Simulation time 38526189 ps
CPU time 0.71 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:42:01 PM PDT 24
Peak memory 205152 kb
Host smart-b19a3451-e0bf-4c46-afe8-2c719793cb00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687599352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
687599352
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2534853350
Short name T602
Test name
Test status
Simulation time 3352243502 ps
CPU time 3.02 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:42:04 PM PDT 24
Peak memory 224548 kb
Host smart-23d5f466-7535-4f58-9e34-758d58b3304f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534853350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2534853350
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1061255930
Short name T830
Test name
Test status
Simulation time 55744628 ps
CPU time 0.79 seconds
Started Jun 06 02:41:54 PM PDT 24
Finished Jun 06 02:41:58 PM PDT 24
Peak memory 206500 kb
Host smart-ca0356e0-2965-492d-a0f2-c73bf330e76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061255930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1061255930
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2519758591
Short name T777
Test name
Test status
Simulation time 10309476899 ps
CPU time 78.8 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:43:29 PM PDT 24
Peak memory 236508 kb
Host smart-fce6c16f-a886-4540-b3b4-83fd6ca6cd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519758591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2519758591
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2326195787
Short name T314
Test name
Test status
Simulation time 1069631113 ps
CPU time 17.26 seconds
Started Jun 06 02:42:06 PM PDT 24
Finished Jun 06 02:42:25 PM PDT 24
Peak memory 232960 kb
Host smart-fd99299b-b0d8-4b23-a256-217479c31c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326195787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2326195787
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1742925657
Short name T172
Test name
Test status
Simulation time 1601843826 ps
CPU time 18.87 seconds
Started Jun 06 02:41:56 PM PDT 24
Finished Jun 06 02:42:18 PM PDT 24
Peak memory 224472 kb
Host smart-17641c69-556c-4701-875b-0d66cea56024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742925657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1742925657
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.397394352
Short name T653
Test name
Test status
Simulation time 14421859848 ps
CPU time 39.6 seconds
Started Jun 06 02:42:04 PM PDT 24
Finished Jun 06 02:42:52 PM PDT 24
Peak memory 232744 kb
Host smart-79983dfa-2449-4bf5-8ec3-eeadf26c0d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397394352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.397394352
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3969175279
Short name T823
Test name
Test status
Simulation time 425998006 ps
CPU time 1.08 seconds
Started Jun 06 02:41:56 PM PDT 24
Finished Jun 06 02:42:00 PM PDT 24
Peak memory 216500 kb
Host smart-b943aa74-0374-4a1b-90ac-e1576c6b235b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969175279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3969175279
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3958179418
Short name T956
Test name
Test status
Simulation time 265461244 ps
CPU time 2.41 seconds
Started Jun 06 02:41:47 PM PDT 24
Finished Jun 06 02:41:53 PM PDT 24
Peak memory 224492 kb
Host smart-5b01fff1-5dc5-4161-a1d1-6da2de823d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958179418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3958179418
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1885872474
Short name T187
Test name
Test status
Simulation time 10333367031 ps
CPU time 15.87 seconds
Started Jun 06 02:42:00 PM PDT 24
Finished Jun 06 02:42:18 PM PDT 24
Peak memory 224516 kb
Host smart-87126f1e-25d3-4f15-9184-abb6345c3758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885872474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1885872474
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.472012637
Short name T765
Test name
Test status
Simulation time 1338658673 ps
CPU time 12.72 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:42:22 PM PDT 24
Peak memory 222932 kb
Host smart-f325275d-08f5-4e53-aab8-9e68321a60da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=472012637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.472012637
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3652967091
Short name T59
Test name
Test status
Simulation time 378281451 ps
CPU time 1.16 seconds
Started Jun 06 02:41:56 PM PDT 24
Finished Jun 06 02:42:01 PM PDT 24
Peak memory 235532 kb
Host smart-530ce3ab-df87-4109-9cbf-1b6f52aae4a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652967091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3652967091
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3217613277
Short name T39
Test name
Test status
Simulation time 62641462926 ps
CPU time 186.89 seconds
Started Jun 06 02:41:54 PM PDT 24
Finished Jun 06 02:45:05 PM PDT 24
Peak memory 251292 kb
Host smart-87db2f49-0a60-4bb3-a3ae-480e01115799
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217613277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3217613277
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3243313005
Short name T595
Test name
Test status
Simulation time 153923475 ps
CPU time 2.68 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:42:03 PM PDT 24
Peak memory 218288 kb
Host smart-2fd35d7a-9aa6-4bcd-8e06-968514feb5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243313005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3243313005
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.833670989
Short name T959
Test name
Test status
Simulation time 14520338224 ps
CPU time 18.66 seconds
Started Jun 06 02:41:53 PM PDT 24
Finished Jun 06 02:42:16 PM PDT 24
Peak memory 216412 kb
Host smart-a59fdeaa-a4fd-40a5-a139-78983944101b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833670989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.833670989
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1957269151
Short name T544
Test name
Test status
Simulation time 164742117 ps
CPU time 1.41 seconds
Started Jun 06 02:41:59 PM PDT 24
Finished Jun 06 02:42:03 PM PDT 24
Peak memory 216320 kb
Host smart-c9730f50-2e35-4ee5-aa84-36869477564c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957269151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1957269151
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2518585335
Short name T588
Test name
Test status
Simulation time 151319290 ps
CPU time 0.74 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:42:01 PM PDT 24
Peak memory 205764 kb
Host smart-3cb9c00f-ad3e-48aa-b46b-3681a2ca11e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518585335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2518585335
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3478681869
Short name T750
Test name
Test status
Simulation time 313803919 ps
CPU time 5.33 seconds
Started Jun 06 02:41:55 PM PDT 24
Finished Jun 06 02:42:04 PM PDT 24
Peak memory 232736 kb
Host smart-9268bcec-c5f7-4767-a975-353e70c7edd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478681869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3478681869
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.311470429
Short name T441
Test name
Test status
Simulation time 20655001 ps
CPU time 0.74 seconds
Started Jun 06 02:42:50 PM PDT 24
Finished Jun 06 02:42:53 PM PDT 24
Peak memory 205160 kb
Host smart-ac656997-14f3-40cf-b41f-fd62a1e60984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311470429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.311470429
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.4154396514
Short name T791
Test name
Test status
Simulation time 934068418 ps
CPU time 7.61 seconds
Started Jun 06 02:42:43 PM PDT 24
Finished Jun 06 02:42:53 PM PDT 24
Peak memory 232780 kb
Host smart-d1895e9c-7a34-4ac9-8d14-70a53b627108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154396514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4154396514
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2891179623
Short name T620
Test name
Test status
Simulation time 54480198 ps
CPU time 0.76 seconds
Started Jun 06 02:42:46 PM PDT 24
Finished Jun 06 02:42:50 PM PDT 24
Peak memory 206808 kb
Host smart-7d1cc04a-c3dd-40cc-b9f0-7095cbe95e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891179623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2891179623
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2400434969
Short name T245
Test name
Test status
Simulation time 214274270530 ps
CPU time 353.06 seconds
Started Jun 06 02:42:59 PM PDT 24
Finished Jun 06 02:48:53 PM PDT 24
Peak memory 250912 kb
Host smart-3e4e0a20-f5ba-43c6-bdab-43efb18e17f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400434969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2400434969
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3745379110
Short name T674
Test name
Test status
Simulation time 27128483898 ps
CPU time 265.44 seconds
Started Jun 06 02:42:41 PM PDT 24
Finished Jun 06 02:47:09 PM PDT 24
Peak memory 250600 kb
Host smart-01a19f4e-5982-4620-bec9-57ebd52b3b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745379110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3745379110
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.419220879
Short name T183
Test name
Test status
Simulation time 92327069291 ps
CPU time 262.03 seconds
Started Jun 06 02:42:45 PM PDT 24
Finished Jun 06 02:47:10 PM PDT 24
Peak memory 252292 kb
Host smart-11a161d7-7ab5-4b5d-ad60-da4ecd726f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419220879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.419220879
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.4124732927
Short name T710
Test name
Test status
Simulation time 954576085 ps
CPU time 9.65 seconds
Started Jun 06 02:42:48 PM PDT 24
Finished Jun 06 02:43:00 PM PDT 24
Peak memory 232732 kb
Host smart-da20a40c-904a-46a1-9f07-a08c3cd96a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124732927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.4124732927
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.606274285
Short name T955
Test name
Test status
Simulation time 2779793403 ps
CPU time 7.84 seconds
Started Jun 06 02:42:49 PM PDT 24
Finished Jun 06 02:43:00 PM PDT 24
Peak memory 232744 kb
Host smart-6910d83e-c133-4171-a5bf-3f967a1fdf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606274285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.606274285
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.680532145
Short name T585
Test name
Test status
Simulation time 9027190228 ps
CPU time 12.95 seconds
Started Jun 06 02:42:43 PM PDT 24
Finished Jun 06 02:42:59 PM PDT 24
Peak memory 232796 kb
Host smart-1d1a91aa-e606-428a-8a63-60298d74f002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680532145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.680532145
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.901121576
Short name T882
Test name
Test status
Simulation time 808051124 ps
CPU time 3.13 seconds
Started Jun 06 02:42:45 PM PDT 24
Finished Jun 06 02:42:51 PM PDT 24
Peak memory 224508 kb
Host smart-0dad9d73-de9b-4b2e-b1ac-20fa9e2db354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901121576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.901121576
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.74109831
Short name T554
Test name
Test status
Simulation time 1802741827 ps
CPU time 7.11 seconds
Started Jun 06 02:42:49 PM PDT 24
Finished Jun 06 02:42:59 PM PDT 24
Peak memory 224512 kb
Host smart-98d45342-4956-4a02-b61b-f47828aa07d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74109831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.74109831
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1562077822
Short name T379
Test name
Test status
Simulation time 142917486 ps
CPU time 3.22 seconds
Started Jun 06 02:42:46 PM PDT 24
Finished Jun 06 02:42:52 PM PDT 24
Peak memory 219876 kb
Host smart-fa6d55d0-4e81-4633-bee3-6e7a35778ddd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1562077822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1562077822
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1530776987
Short name T799
Test name
Test status
Simulation time 16805139265 ps
CPU time 43.96 seconds
Started Jun 06 02:42:57 PM PDT 24
Finished Jun 06 02:43:42 PM PDT 24
Peak memory 216364 kb
Host smart-87e8504d-60bc-4112-948a-c713132cc5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530776987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1530776987
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3590462220
Short name T14
Test name
Test status
Simulation time 2284058957 ps
CPU time 7.4 seconds
Started Jun 06 02:42:50 PM PDT 24
Finished Jun 06 02:43:00 PM PDT 24
Peak memory 216292 kb
Host smart-d7b4662f-a402-434c-adb1-66f0cb3086bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590462220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3590462220
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1062867940
Short name T408
Test name
Test status
Simulation time 55918691 ps
CPU time 0.74 seconds
Started Jun 06 02:42:49 PM PDT 24
Finished Jun 06 02:42:52 PM PDT 24
Peak memory 205832 kb
Host smart-3abe7b57-a9ca-4783-8509-9024673bdb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062867940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1062867940
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.880001684
Short name T536
Test name
Test status
Simulation time 894803925 ps
CPU time 0.88 seconds
Started Jun 06 02:42:44 PM PDT 24
Finished Jun 06 02:42:48 PM PDT 24
Peak memory 205800 kb
Host smart-6991b8df-6bc2-4756-a86b-636413ea7dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880001684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.880001684
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.4012662513
Short name T158
Test name
Test status
Simulation time 548919175 ps
CPU time 6.84 seconds
Started Jun 06 02:42:48 PM PDT 24
Finished Jun 06 02:42:57 PM PDT 24
Peak memory 224500 kb
Host smart-f2a8d750-e952-4cc9-9557-4c8b18879bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012662513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4012662513
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3227802251
Short name T383
Test name
Test status
Simulation time 15484401 ps
CPU time 0.69 seconds
Started Jun 06 02:42:54 PM PDT 24
Finished Jun 06 02:42:56 PM PDT 24
Peak memory 204580 kb
Host smart-34de103f-5aa3-4d4b-99b9-a7a516ba0481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227802251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3227802251
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.918948979
Short name T922
Test name
Test status
Simulation time 102943774 ps
CPU time 2.27 seconds
Started Jun 06 02:42:48 PM PDT 24
Finished Jun 06 02:42:53 PM PDT 24
Peak memory 232688 kb
Host smart-1d77c71a-bee7-4bae-87d4-08a7ad6a3cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918948979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.918948979
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1845856941
Short name T764
Test name
Test status
Simulation time 58942706 ps
CPU time 0.8 seconds
Started Jun 06 02:42:56 PM PDT 24
Finished Jun 06 02:42:59 PM PDT 24
Peak memory 206684 kb
Host smart-cfee1cb2-3c90-415a-9c57-c1584715a363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845856941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1845856941
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2944462277
Short name T30
Test name
Test status
Simulation time 64961800890 ps
CPU time 81.22 seconds
Started Jun 06 02:42:59 PM PDT 24
Finished Jun 06 02:44:22 PM PDT 24
Peak memory 257384 kb
Host smart-c71ea23a-41a3-4594-b13c-6518abdae63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944462277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2944462277
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2394883875
Short name T132
Test name
Test status
Simulation time 17525048969 ps
CPU time 225.9 seconds
Started Jun 06 02:42:56 PM PDT 24
Finished Jun 06 02:46:43 PM PDT 24
Peak memory 256088 kb
Host smart-491e20f3-4458-4e0b-b0dc-c23ccaa29958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394883875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2394883875
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3492982684
Short name T642
Test name
Test status
Simulation time 4439198692 ps
CPU time 19.25 seconds
Started Jun 06 02:42:56 PM PDT 24
Finished Jun 06 02:43:17 PM PDT 24
Peak memory 217696 kb
Host smart-96dd2bae-667a-446e-98e0-a977830f2cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492982684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3492982684
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2660801755
Short name T573
Test name
Test status
Simulation time 10139449514 ps
CPU time 30.01 seconds
Started Jun 06 02:42:50 PM PDT 24
Finished Jun 06 02:43:23 PM PDT 24
Peak memory 232824 kb
Host smart-0148ecce-4ca7-4ba7-a41b-cc7ef41f6505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660801755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2660801755
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.851803059
Short name T48
Test name
Test status
Simulation time 132798667 ps
CPU time 3.27 seconds
Started Jun 06 02:42:54 PM PDT 24
Finished Jun 06 02:42:58 PM PDT 24
Peak memory 232728 kb
Host smart-1a04637d-d00d-438b-935c-aa67111128b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851803059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.851803059
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3995529299
Short name T474
Test name
Test status
Simulation time 498138809 ps
CPU time 3.59 seconds
Started Jun 06 02:42:50 PM PDT 24
Finished Jun 06 02:42:56 PM PDT 24
Peak memory 232780 kb
Host smart-f66c47fc-e771-401b-aea8-2962a6c4f57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995529299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3995529299
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.4101780418
Short name T288
Test name
Test status
Simulation time 5501962056 ps
CPU time 7.93 seconds
Started Jun 06 02:42:49 PM PDT 24
Finished Jun 06 02:42:59 PM PDT 24
Peak memory 224592 kb
Host smart-df308791-09ae-4740-8a4a-6b0989c1d62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101780418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.4101780418
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.73934419
Short name T126
Test name
Test status
Simulation time 135673032 ps
CPU time 4.17 seconds
Started Jun 06 02:42:50 PM PDT 24
Finished Jun 06 02:42:57 PM PDT 24
Peak memory 232728 kb
Host smart-d74655c5-126f-45d3-8ae9-7e71a591b002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73934419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.73934419
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3749825188
Short name T731
Test name
Test status
Simulation time 742602108 ps
CPU time 8.94 seconds
Started Jun 06 02:42:55 PM PDT 24
Finished Jun 06 02:43:06 PM PDT 24
Peak memory 222232 kb
Host smart-c4cf5b7a-c7f6-4241-b942-ce06bad699d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3749825188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3749825188
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1805662572
Short name T786
Test name
Test status
Simulation time 90308701 ps
CPU time 1.04 seconds
Started Jun 06 02:42:48 PM PDT 24
Finished Jun 06 02:42:52 PM PDT 24
Peak memory 207152 kb
Host smart-253a2df6-6309-4fb8-940f-3183c10d3a6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805662572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1805662572
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2648190852
Short name T635
Test name
Test status
Simulation time 1305931424 ps
CPU time 3.9 seconds
Started Jun 06 02:42:52 PM PDT 24
Finished Jun 06 02:42:58 PM PDT 24
Peak memory 216208 kb
Host smart-a7354334-dab6-4bf3-9a83-cdea93578456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648190852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2648190852
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3423663389
Short name T853
Test name
Test status
Simulation time 3172995705 ps
CPU time 2.53 seconds
Started Jun 06 02:42:50 PM PDT 24
Finished Jun 06 02:42:55 PM PDT 24
Peak memory 216364 kb
Host smart-ccf80e8f-0675-4163-abd5-50468ab1986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423663389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3423663389
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.799396016
Short name T470
Test name
Test status
Simulation time 142045076 ps
CPU time 0.76 seconds
Started Jun 06 02:42:48 PM PDT 24
Finished Jun 06 02:42:51 PM PDT 24
Peak memory 205820 kb
Host smart-9713921c-faf3-4fc1-8d18-f53ec9c59bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799396016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.799396016
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3154256700
Short name T614
Test name
Test status
Simulation time 67805153 ps
CPU time 0.91 seconds
Started Jun 06 02:42:51 PM PDT 24
Finished Jun 06 02:42:54 PM PDT 24
Peak memory 205772 kb
Host smart-85afd8e3-7e3a-4346-8fa3-d29977d1a5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154256700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3154256700
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2638829721
Short name T207
Test name
Test status
Simulation time 7113531027 ps
CPU time 4.03 seconds
Started Jun 06 02:42:49 PM PDT 24
Finished Jun 06 02:42:56 PM PDT 24
Peak memory 224576 kb
Host smart-ab886d79-704f-44f6-b407-84ee53510458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638829721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2638829721
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3346639768
Short name T453
Test name
Test status
Simulation time 39943798 ps
CPU time 0.71 seconds
Started Jun 06 02:42:55 PM PDT 24
Finished Jun 06 02:42:58 PM PDT 24
Peak memory 204784 kb
Host smart-eabfc7b5-3cb8-4c6b-97ef-355f06283af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346639768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3346639768
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.119644525
Short name T807
Test name
Test status
Simulation time 160468925 ps
CPU time 2.47 seconds
Started Jun 06 02:42:50 PM PDT 24
Finished Jun 06 02:42:55 PM PDT 24
Peak memory 224528 kb
Host smart-f1606dcf-c4b9-445e-b8ad-bf840bde328d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119644525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.119644525
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3200439384
Short name T411
Test name
Test status
Simulation time 111286065 ps
CPU time 0.78 seconds
Started Jun 06 02:42:53 PM PDT 24
Finished Jun 06 02:42:55 PM PDT 24
Peak memory 206424 kb
Host smart-8bba1385-fbd3-42f6-904b-dcb1dbc993d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200439384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3200439384
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2835805148
Short name T238
Test name
Test status
Simulation time 10355378787 ps
CPU time 64.27 seconds
Started Jun 06 02:42:58 PM PDT 24
Finished Jun 06 02:44:04 PM PDT 24
Peak memory 249208 kb
Host smart-a77a7584-e655-4113-ac20-5846e7e5c9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835805148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2835805148
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.139973141
Short name T858
Test name
Test status
Simulation time 13440150562 ps
CPU time 142.79 seconds
Started Jun 06 02:42:59 PM PDT 24
Finished Jun 06 02:45:24 PM PDT 24
Peak memory 261844 kb
Host smart-16a84dbc-4e78-401d-92ff-ada8f98b1571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139973141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.139973141
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3666126769
Short name T313
Test name
Test status
Simulation time 20001617737 ps
CPU time 73.11 seconds
Started Jun 06 02:42:55 PM PDT 24
Finished Jun 06 02:44:10 PM PDT 24
Peak memory 249432 kb
Host smart-4eabc45d-6ac2-45b5-87b5-ec0c6d0cb8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666126769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3666126769
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.4044815691
Short name T197
Test name
Test status
Simulation time 4000501817 ps
CPU time 21.97 seconds
Started Jun 06 02:42:52 PM PDT 24
Finished Jun 06 02:43:16 PM PDT 24
Peak memory 232776 kb
Host smart-b3134b78-4c8d-4530-a9d6-eb6c2772b34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044815691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4044815691
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1544227090
Short name T289
Test name
Test status
Simulation time 9465941612 ps
CPU time 63.25 seconds
Started Jun 06 02:42:59 PM PDT 24
Finished Jun 06 02:44:04 PM PDT 24
Peak memory 228840 kb
Host smart-9b15b80b-685d-420c-afdf-9d9ad372dd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544227090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1544227090
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1673951385
Short name T709
Test name
Test status
Simulation time 2618297329 ps
CPU time 3.82 seconds
Started Jun 06 02:42:53 PM PDT 24
Finished Jun 06 02:42:58 PM PDT 24
Peak memory 232844 kb
Host smart-2da1bc73-e671-456b-a950-fce7d0709927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673951385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1673951385
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2939913940
Short name T351
Test name
Test status
Simulation time 60402495 ps
CPU time 2.38 seconds
Started Jun 06 02:42:59 PM PDT 24
Finished Jun 06 02:43:03 PM PDT 24
Peak memory 226540 kb
Host smart-4b4dc153-6746-4384-a8a7-4288475caed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939913940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2939913940
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1564748367
Short name T906
Test name
Test status
Simulation time 2813200984 ps
CPU time 16.46 seconds
Started Jun 06 02:42:47 PM PDT 24
Finished Jun 06 02:43:06 PM PDT 24
Peak memory 218836 kb
Host smart-bdbb5e65-0a79-4bb3-9fea-660d35a6d541
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1564748367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1564748367
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1687795268
Short name T480
Test name
Test status
Simulation time 5879496614 ps
CPU time 87.93 seconds
Started Jun 06 02:42:52 PM PDT 24
Finished Jun 06 02:44:22 PM PDT 24
Peak memory 256808 kb
Host smart-2e980547-de21-4cca-8f3f-b68865fd4159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687795268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1687795268
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3213958028
Short name T415
Test name
Test status
Simulation time 11644383983 ps
CPU time 31.71 seconds
Started Jun 06 02:42:53 PM PDT 24
Finished Jun 06 02:43:27 PM PDT 24
Peak memory 220612 kb
Host smart-8a6ed9ea-a012-4f04-98b6-124d7fe67f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213958028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3213958028
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.649924659
Short name T825
Test name
Test status
Simulation time 38119234108 ps
CPU time 14.42 seconds
Started Jun 06 02:42:56 PM PDT 24
Finished Jun 06 02:43:12 PM PDT 24
Peak memory 216596 kb
Host smart-d1d14e3d-3f2c-411f-aba8-2e7be5c41f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649924659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.649924659
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.498357936
Short name T409
Test name
Test status
Simulation time 101319245 ps
CPU time 4.04 seconds
Started Jun 06 02:42:53 PM PDT 24
Finished Jun 06 02:42:59 PM PDT 24
Peak memory 216344 kb
Host smart-cdc2303f-dcb0-4b56-9067-b0dd080d7ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498357936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.498357936
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1449901735
Short name T677
Test name
Test status
Simulation time 108656700 ps
CPU time 0.79 seconds
Started Jun 06 02:42:48 PM PDT 24
Finished Jun 06 02:42:51 PM PDT 24
Peak memory 205748 kb
Host smart-3d53eec6-4f71-4862-b7d9-e1060c4440a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449901735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1449901735
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3075261720
Short name T803
Test name
Test status
Simulation time 17859500623 ps
CPU time 13.33 seconds
Started Jun 06 02:42:51 PM PDT 24
Finished Jun 06 02:43:07 PM PDT 24
Peak memory 224636 kb
Host smart-64616a63-595d-441e-b1fd-357b0f09f6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075261720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3075261720
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3516986510
Short name T67
Test name
Test status
Simulation time 15172026 ps
CPU time 0.71 seconds
Started Jun 06 02:43:00 PM PDT 24
Finished Jun 06 02:43:03 PM PDT 24
Peak memory 205192 kb
Host smart-9f85acd1-6710-4f36-82be-96f9f6e86ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516986510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3516986510
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2953471956
Short name T606
Test name
Test status
Simulation time 35818641 ps
CPU time 2.31 seconds
Started Jun 06 02:43:10 PM PDT 24
Finished Jun 06 02:43:15 PM PDT 24
Peak memory 224488 kb
Host smart-ee27d6bd-267f-4933-a448-d32a44bf5f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953471956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2953471956
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.4006454041
Short name T491
Test name
Test status
Simulation time 75285683 ps
CPU time 0.75 seconds
Started Jun 06 02:42:50 PM PDT 24
Finished Jun 06 02:42:53 PM PDT 24
Peak memory 206780 kb
Host smart-0c65b0ae-cb27-4c8e-99b6-390bc22f38e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006454041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.4006454041
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2355652124
Short name T71
Test name
Test status
Simulation time 21175466198 ps
CPU time 110.01 seconds
Started Jun 06 02:43:09 PM PDT 24
Finished Jun 06 02:45:01 PM PDT 24
Peak memory 249208 kb
Host smart-bd835ce1-5c35-4f5e-8052-a703c4c2ab0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355652124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2355652124
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.787661914
Short name T186
Test name
Test status
Simulation time 17818146526 ps
CPU time 230.42 seconds
Started Jun 06 02:43:01 PM PDT 24
Finished Jun 06 02:46:53 PM PDT 24
Peak memory 266640 kb
Host smart-52a32d5f-529b-4030-b5ec-48eeb77ef700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787661914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.787661914
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3351875524
Short name T557
Test name
Test status
Simulation time 7346676989 ps
CPU time 64.08 seconds
Started Jun 06 02:42:59 PM PDT 24
Finished Jun 06 02:44:05 PM PDT 24
Peak memory 249204 kb
Host smart-37e536f4-3f01-4545-b181-09d66eafbba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351875524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3351875524
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3183294745
Short name T926
Test name
Test status
Simulation time 299766576 ps
CPU time 8.17 seconds
Started Jun 06 02:43:02 PM PDT 24
Finished Jun 06 02:43:11 PM PDT 24
Peak memory 240820 kb
Host smart-ae1a01b9-577a-41a8-ae5c-0208cbaf8f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183294745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3183294745
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.981212966
Short name T873
Test name
Test status
Simulation time 654030609 ps
CPU time 3.58 seconds
Started Jun 06 02:43:06 PM PDT 24
Finished Jun 06 02:43:11 PM PDT 24
Peak memory 224524 kb
Host smart-d60fdf52-bae6-4c18-9c26-27e04c849a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981212966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.981212966
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4183865504
Short name T973
Test name
Test status
Simulation time 1174723616 ps
CPU time 7.13 seconds
Started Jun 06 02:43:06 PM PDT 24
Finished Jun 06 02:43:15 PM PDT 24
Peak memory 232720 kb
Host smart-569bb78f-13cb-445a-94e8-c18c40755579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183865504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4183865504
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1220150732
Short name T125
Test name
Test status
Simulation time 450576554 ps
CPU time 2.85 seconds
Started Jun 06 02:42:56 PM PDT 24
Finished Jun 06 02:43:01 PM PDT 24
Peak memory 224476 kb
Host smart-7b79347e-7839-4694-83d6-560d0e5fcb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220150732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1220150732
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2511960458
Short name T5
Test name
Test status
Simulation time 899949647 ps
CPU time 5.04 seconds
Started Jun 06 02:42:58 PM PDT 24
Finished Jun 06 02:43:05 PM PDT 24
Peak memory 232752 kb
Host smart-106ead96-8d69-46f9-92af-bfc8bc751ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511960458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2511960458
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.4144282536
Short name T33
Test name
Test status
Simulation time 7345179817 ps
CPU time 13.06 seconds
Started Jun 06 02:42:58 PM PDT 24
Finished Jun 06 02:43:12 PM PDT 24
Peak memory 223020 kb
Host smart-db8f13e9-cc86-4e68-9cd2-3dc038d47be8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4144282536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.4144282536
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2009645720
Short name T809
Test name
Test status
Simulation time 1344437768 ps
CPU time 3.08 seconds
Started Jun 06 02:42:56 PM PDT 24
Finished Jun 06 02:43:01 PM PDT 24
Peak memory 216224 kb
Host smart-0f00bce3-c938-41d0-b916-1a5a9b7d5d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009645720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2009645720
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2796954532
Short name T388
Test name
Test status
Simulation time 10249910 ps
CPU time 0.7 seconds
Started Jun 06 02:43:10 PM PDT 24
Finished Jun 06 02:43:13 PM PDT 24
Peak memory 205332 kb
Host smart-8ad721a7-bd0f-416c-88f1-9e8d9acb15fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796954532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2796954532
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2349330604
Short name T876
Test name
Test status
Simulation time 146032968 ps
CPU time 0.91 seconds
Started Jun 06 02:43:00 PM PDT 24
Finished Jun 06 02:43:03 PM PDT 24
Peak memory 206804 kb
Host smart-7867293f-cf66-4a21-a641-2b7a7c030607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349330604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2349330604
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3232228088
Short name T396
Test name
Test status
Simulation time 210131361 ps
CPU time 2.27 seconds
Started Jun 06 02:43:09 PM PDT 24
Finished Jun 06 02:43:13 PM PDT 24
Peak memory 223128 kb
Host smart-09a5f728-ae75-4244-8149-0628bab02f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232228088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3232228088
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2206176726
Short name T369
Test name
Test status
Simulation time 30143331 ps
CPU time 0.68 seconds
Started Jun 06 02:43:08 PM PDT 24
Finished Jun 06 02:43:11 PM PDT 24
Peak memory 204568 kb
Host smart-d225b061-6e79-459c-a1a3-1324587fdb66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206176726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2206176726
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1567501420
Short name T640
Test name
Test status
Simulation time 349708998 ps
CPU time 2.72 seconds
Started Jun 06 02:43:01 PM PDT 24
Finished Jun 06 02:43:05 PM PDT 24
Peak memory 224524 kb
Host smart-05b43a6a-b2d9-4b27-a54b-bad566555f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567501420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1567501420
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3118766363
Short name T703
Test name
Test status
Simulation time 17419186 ps
CPU time 0.81 seconds
Started Jun 06 02:42:58 PM PDT 24
Finished Jun 06 02:43:01 PM PDT 24
Peak memory 205752 kb
Host smart-3091b895-3da6-4699-9ab0-563732f36d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118766363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3118766363
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2165827338
Short name T65
Test name
Test status
Simulation time 38939337876 ps
CPU time 78.76 seconds
Started Jun 06 02:42:58 PM PDT 24
Finished Jun 06 02:44:18 PM PDT 24
Peak memory 252812 kb
Host smart-e5bc28be-3b49-40a1-be54-ffe86f024ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165827338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2165827338
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1434360699
Short name T469
Test name
Test status
Simulation time 13215081508 ps
CPU time 175.07 seconds
Started Jun 06 02:43:10 PM PDT 24
Finished Jun 06 02:46:08 PM PDT 24
Peak memory 256216 kb
Host smart-29dc344c-1d6c-48fa-a02f-d74a9ff491e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434360699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1434360699
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1190331943
Short name T596
Test name
Test status
Simulation time 35957410609 ps
CPU time 22.77 seconds
Started Jun 06 02:43:00 PM PDT 24
Finished Jun 06 02:43:25 PM PDT 24
Peak memory 241016 kb
Host smart-b4237fc1-0a0e-4947-bb4e-cddb7676add7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190331943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1190331943
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1494285445
Short name T476
Test name
Test status
Simulation time 731031068 ps
CPU time 8.88 seconds
Started Jun 06 02:43:04 PM PDT 24
Finished Jun 06 02:43:14 PM PDT 24
Peak memory 224504 kb
Host smart-fb00b3d2-43b1-4736-bdeb-9f1b63214f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494285445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1494285445
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1019940389
Short name T859
Test name
Test status
Simulation time 21678783452 ps
CPU time 126.49 seconds
Started Jun 06 02:43:02 PM PDT 24
Finished Jun 06 02:45:10 PM PDT 24
Peak memory 249168 kb
Host smart-99b3f5bf-be1c-496c-aa93-2df5b96e6108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019940389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1019940389
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3185450089
Short name T290
Test name
Test status
Simulation time 6574766661 ps
CPU time 12.94 seconds
Started Jun 06 02:42:58 PM PDT 24
Finished Jun 06 02:43:13 PM PDT 24
Peak memory 233860 kb
Host smart-6c609307-e4a7-4bd5-8c89-92d3b8b32bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185450089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3185450089
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2540718876
Short name T742
Test name
Test status
Simulation time 5785397136 ps
CPU time 11.77 seconds
Started Jun 06 02:42:57 PM PDT 24
Finished Jun 06 02:43:10 PM PDT 24
Peak memory 232764 kb
Host smart-5ad42c14-3a41-4699-84eb-af9ccbd185bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540718876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2540718876
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2863427664
Short name T836
Test name
Test status
Simulation time 1836707225 ps
CPU time 7.79 seconds
Started Jun 06 02:43:06 PM PDT 24
Finished Jun 06 02:43:15 PM PDT 24
Peak memory 220000 kb
Host smart-1c5b14b5-e3d0-4ed9-be32-6c2ad3e60f25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2863427664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2863427664
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1904164634
Short name T330
Test name
Test status
Simulation time 3658210134 ps
CPU time 25.01 seconds
Started Jun 06 02:43:02 PM PDT 24
Finished Jun 06 02:43:28 PM PDT 24
Peak memory 216432 kb
Host smart-5063d6b3-1f13-4c18-b576-643a6b17ebe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904164634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1904164634
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2189185155
Short name T804
Test name
Test status
Simulation time 590100958 ps
CPU time 3.91 seconds
Started Jun 06 02:42:59 PM PDT 24
Finished Jun 06 02:43:05 PM PDT 24
Peak memory 216260 kb
Host smart-6970c6b2-ca30-4637-a54b-14c9013bb1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189185155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2189185155
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2446318698
Short name T467
Test name
Test status
Simulation time 201338780 ps
CPU time 1.78 seconds
Started Jun 06 02:43:05 PM PDT 24
Finished Jun 06 02:43:08 PM PDT 24
Peak memory 216332 kb
Host smart-b4081abd-be07-4c81-833c-e9f20e1fef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446318698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2446318698
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3091833629
Short name T561
Test name
Test status
Simulation time 68031609 ps
CPU time 0.74 seconds
Started Jun 06 02:42:58 PM PDT 24
Finished Jun 06 02:43:00 PM PDT 24
Peak memory 205760 kb
Host smart-15522bf4-28ee-4307-836d-f2f84f739a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091833629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3091833629
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3816377322
Short name T820
Test name
Test status
Simulation time 436557220 ps
CPU time 5.24 seconds
Started Jun 06 02:43:00 PM PDT 24
Finished Jun 06 02:43:07 PM PDT 24
Peak memory 232736 kb
Host smart-0fbbf08f-af81-4468-80a9-e96fe679f7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816377322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3816377322
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3114893489
Short name T46
Test name
Test status
Simulation time 72355210 ps
CPU time 0.71 seconds
Started Jun 06 02:43:15 PM PDT 24
Finished Jun 06 02:43:19 PM PDT 24
Peak memory 205168 kb
Host smart-ace9f4a0-e2e6-4adf-85f7-e620711d07a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114893489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3114893489
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1887838134
Short name T622
Test name
Test status
Simulation time 651250144 ps
CPU time 6.32 seconds
Started Jun 06 02:42:59 PM PDT 24
Finished Jun 06 02:43:07 PM PDT 24
Peak memory 232676 kb
Host smart-08e846ca-d1a9-4dc1-b5cd-26ab9eebbc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887838134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1887838134
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2115611375
Short name T542
Test name
Test status
Simulation time 46686071 ps
CPU time 0.75 seconds
Started Jun 06 02:42:58 PM PDT 24
Finished Jun 06 02:43:00 PM PDT 24
Peak memory 205736 kb
Host smart-c8d3aef3-81e1-4c07-9970-9add2146800e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115611375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2115611375
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.123506017
Short name T713
Test name
Test status
Simulation time 16286157540 ps
CPU time 129.06 seconds
Started Jun 06 02:42:58 PM PDT 24
Finished Jun 06 02:45:08 PM PDT 24
Peak memory 250244 kb
Host smart-0571d652-bc1a-4cec-b269-2d14d1f2d44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123506017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.123506017
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.287252652
Short name T952
Test name
Test status
Simulation time 34005712766 ps
CPU time 82.42 seconds
Started Jun 06 02:43:04 PM PDT 24
Finished Jun 06 02:44:28 PM PDT 24
Peak memory 240592 kb
Host smart-4ff719a6-4a8c-440a-9fa6-a74436507668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287252652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.287252652
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1705864550
Short name T208
Test name
Test status
Simulation time 11554544319 ps
CPU time 135.56 seconds
Started Jun 06 02:43:01 PM PDT 24
Finished Jun 06 02:45:18 PM PDT 24
Peak memory 249256 kb
Host smart-d5efa47a-e3eb-4c84-b617-079e2ccf0d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705864550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1705864550
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3740707608
Short name T909
Test name
Test status
Simulation time 95392420 ps
CPU time 2.71 seconds
Started Jun 06 02:42:57 PM PDT 24
Finished Jun 06 02:43:01 PM PDT 24
Peak memory 224564 kb
Host smart-2e5b57e1-74a1-44bf-a867-8ac6273af932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740707608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3740707608
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2216314936
Short name T349
Test name
Test status
Simulation time 249378774 ps
CPU time 2.11 seconds
Started Jun 06 02:42:57 PM PDT 24
Finished Jun 06 02:43:01 PM PDT 24
Peak memory 223128 kb
Host smart-740afca2-bd48-47fe-9b15-2d323d9d62f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216314936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2216314936
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1385221318
Short name T887
Test name
Test status
Simulation time 1236870081 ps
CPU time 6.82 seconds
Started Jun 06 02:43:01 PM PDT 24
Finished Jun 06 02:43:09 PM PDT 24
Peak memory 224524 kb
Host smart-c5b1b317-1b6a-40fc-8aec-7a8f1bedc084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385221318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1385221318
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3188433358
Short name T66
Test name
Test status
Simulation time 22380431830 ps
CPU time 16.86 seconds
Started Jun 06 02:42:57 PM PDT 24
Finished Jun 06 02:43:16 PM PDT 24
Peak memory 232820 kb
Host smart-99529f7b-73e1-4502-a5c5-8d4e872b2f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188433358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3188433358
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2653068440
Short name T481
Test name
Test status
Simulation time 218286379 ps
CPU time 3.05 seconds
Started Jun 06 02:43:00 PM PDT 24
Finished Jun 06 02:43:05 PM PDT 24
Peak memory 224452 kb
Host smart-9b58102d-fdd8-462d-9f64-018a2dcf49f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653068440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2653068440
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1325464649
Short name T385
Test name
Test status
Simulation time 412656475 ps
CPU time 4.08 seconds
Started Jun 06 02:43:00 PM PDT 24
Finished Jun 06 02:43:06 PM PDT 24
Peak memory 222972 kb
Host smart-3c411598-31a5-4eac-a15a-62820a77e43c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1325464649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1325464649
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1962220053
Short name T324
Test name
Test status
Simulation time 26539008552 ps
CPU time 33.61 seconds
Started Jun 06 02:42:59 PM PDT 24
Finished Jun 06 02:43:35 PM PDT 24
Peak memory 216380 kb
Host smart-55d63b85-1555-417f-94f5-63434d14f6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962220053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1962220053
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1504565545
Short name T531
Test name
Test status
Simulation time 2607996044 ps
CPU time 5.66 seconds
Started Jun 06 02:43:08 PM PDT 24
Finished Jun 06 02:43:16 PM PDT 24
Peak memory 216296 kb
Host smart-7b211ce3-8605-455a-ad77-6d4f3da13274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504565545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1504565545
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1351610552
Short name T592
Test name
Test status
Simulation time 336152022 ps
CPU time 1.65 seconds
Started Jun 06 02:42:59 PM PDT 24
Finished Jun 06 02:43:03 PM PDT 24
Peak memory 216344 kb
Host smart-14dbccac-5754-45ae-8bcd-e06735d40fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351610552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1351610552
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.604793226
Short name T484
Test name
Test status
Simulation time 151854974 ps
CPU time 0.84 seconds
Started Jun 06 02:43:09 PM PDT 24
Finished Jun 06 02:43:12 PM PDT 24
Peak memory 205772 kb
Host smart-2ce72acd-236d-4a8c-8635-4c5d9a9ccd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604793226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.604793226
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.619413874
Short name T704
Test name
Test status
Simulation time 986819148 ps
CPU time 6.84 seconds
Started Jun 06 02:43:16 PM PDT 24
Finished Jun 06 02:43:26 PM PDT 24
Peak memory 232728 kb
Host smart-61aa7b52-6a15-4027-b2ef-37799e3bad18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619413874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.619413874
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.603113337
Short name T403
Test name
Test status
Simulation time 15053623 ps
CPU time 0.73 seconds
Started Jun 06 02:43:06 PM PDT 24
Finished Jun 06 02:43:08 PM PDT 24
Peak memory 205160 kb
Host smart-b25f6e4b-f53c-460b-8eb8-644d739f2ebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603113337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.603113337
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3115098061
Short name T412
Test name
Test status
Simulation time 68239511 ps
CPU time 2.53 seconds
Started Jun 06 02:43:13 PM PDT 24
Finished Jun 06 02:43:18 PM PDT 24
Peak memory 232412 kb
Host smart-d5d0751f-737c-41c8-90dc-48a0c5b99f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115098061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3115098061
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3920513528
Short name T844
Test name
Test status
Simulation time 237519941 ps
CPU time 0.74 seconds
Started Jun 06 02:43:09 PM PDT 24
Finished Jun 06 02:43:12 PM PDT 24
Peak memory 205448 kb
Host smart-2256c017-59da-4f31-8127-49cf2a11322b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920513528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3920513528
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1623672729
Short name T249
Test name
Test status
Simulation time 341280543151 ps
CPU time 229.47 seconds
Started Jun 06 02:43:06 PM PDT 24
Finished Jun 06 02:46:57 PM PDT 24
Peak memory 240348 kb
Host smart-aac7913c-c9b1-4af1-91b5-8309088d9ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623672729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1623672729
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.655148812
Short name T166
Test name
Test status
Simulation time 8088594277 ps
CPU time 68.54 seconds
Started Jun 06 02:43:11 PM PDT 24
Finished Jun 06 02:44:23 PM PDT 24
Peak memory 251136 kb
Host smart-c54382cf-ba3f-4b9b-aee3-dc2591f31402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655148812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.655148812
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.959029141
Short name T287
Test name
Test status
Simulation time 39044485088 ps
CPU time 144.66 seconds
Started Jun 06 02:43:07 PM PDT 24
Finished Jun 06 02:45:34 PM PDT 24
Peak memory 249576 kb
Host smart-172b1445-6df7-4186-a8b9-c498beca9402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959029141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.959029141
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1137450386
Short name T377
Test name
Test status
Simulation time 118088351 ps
CPU time 4.08 seconds
Started Jun 06 02:43:06 PM PDT 24
Finished Jun 06 02:43:12 PM PDT 24
Peak memory 232736 kb
Host smart-48f46b5b-4bac-40d1-b7db-fdd4506f19ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137450386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1137450386
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3612198604
Short name T177
Test name
Test status
Simulation time 102807341 ps
CPU time 2.58 seconds
Started Jun 06 02:43:07 PM PDT 24
Finished Jun 06 02:43:12 PM PDT 24
Peak memory 232688 kb
Host smart-5aa47e02-a3c2-4c26-911d-566fed4fd5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612198604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3612198604
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1982043651
Short name T847
Test name
Test status
Simulation time 657619195 ps
CPU time 6.84 seconds
Started Jun 06 02:43:05 PM PDT 24
Finished Jun 06 02:43:14 PM PDT 24
Peak memory 232704 kb
Host smart-b8009ffe-f177-475b-a99a-7965b74a4b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982043651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1982043651
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2631153084
Short name T512
Test name
Test status
Simulation time 1332477598 ps
CPU time 4.63 seconds
Started Jun 06 02:43:08 PM PDT 24
Finished Jun 06 02:43:15 PM PDT 24
Peak memory 224584 kb
Host smart-60d0840f-0163-4452-8ba6-e3dd5f8c9cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631153084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2631153084
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3014307888
Short name T584
Test name
Test status
Simulation time 35596331 ps
CPU time 2.54 seconds
Started Jun 06 02:43:07 PM PDT 24
Finished Jun 06 02:43:12 PM PDT 24
Peak memory 232496 kb
Host smart-f2262aa7-943f-4b98-9587-281da1a70cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014307888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3014307888
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3200890938
Short name T414
Test name
Test status
Simulation time 5724240671 ps
CPU time 14.21 seconds
Started Jun 06 02:43:05 PM PDT 24
Finished Jun 06 02:43:21 PM PDT 24
Peak memory 219816 kb
Host smart-0d157c2f-b6ca-4b6b-bc92-fad915a75850
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3200890938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3200890938
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2585811015
Short name T382
Test name
Test status
Simulation time 1744766594 ps
CPU time 3.74 seconds
Started Jun 06 02:43:06 PM PDT 24
Finished Jun 06 02:43:11 PM PDT 24
Peak memory 216348 kb
Host smart-1587e2c7-789b-43a1-9b61-a3b0a2933779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585811015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2585811015
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3288858921
Short name T499
Test name
Test status
Simulation time 1119819432 ps
CPU time 3.05 seconds
Started Jun 06 02:43:06 PM PDT 24
Finished Jun 06 02:43:11 PM PDT 24
Peak memory 216328 kb
Host smart-f086f5aa-4ec0-4d40-919d-f6afaba121f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288858921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3288858921
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1562371357
Short name T372
Test name
Test status
Simulation time 17872382 ps
CPU time 0.99 seconds
Started Jun 06 02:43:06 PM PDT 24
Finished Jun 06 02:43:09 PM PDT 24
Peak memory 207028 kb
Host smart-e9544b42-80cc-40c2-b3a1-1da9e7d66c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562371357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1562371357
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2142859231
Short name T782
Test name
Test status
Simulation time 121370004 ps
CPU time 1.01 seconds
Started Jun 06 02:43:10 PM PDT 24
Finished Jun 06 02:43:13 PM PDT 24
Peak memory 205740 kb
Host smart-c3c827a6-2c63-45a8-8063-7473e0d2017f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142859231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2142859231
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1354101887
Short name T159
Test name
Test status
Simulation time 5816540850 ps
CPU time 9.08 seconds
Started Jun 06 02:43:08 PM PDT 24
Finished Jun 06 02:43:19 PM PDT 24
Peak memory 232832 kb
Host smart-8a5c7644-6b26-4cc8-bfd2-e3c168d3548f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354101887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1354101887
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2742300675
Short name T381
Test name
Test status
Simulation time 16122270 ps
CPU time 0.71 seconds
Started Jun 06 02:43:05 PM PDT 24
Finished Jun 06 02:43:07 PM PDT 24
Peak memory 204584 kb
Host smart-ca1d0391-af72-47d6-9f22-38562b0dac92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742300675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2742300675
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2568299595
Short name T483
Test name
Test status
Simulation time 55601639 ps
CPU time 2.42 seconds
Started Jun 06 02:43:20 PM PDT 24
Finished Jun 06 02:43:24 PM PDT 24
Peak memory 232508 kb
Host smart-2a9fbabf-aa58-4713-b3d8-070479d0cd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568299595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2568299595
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3313624365
Short name T458
Test name
Test status
Simulation time 17901374 ps
CPU time 0.83 seconds
Started Jun 06 02:43:10 PM PDT 24
Finished Jun 06 02:43:14 PM PDT 24
Peak memory 205764 kb
Host smart-11fd2956-3875-41c9-9dae-5a1d1eeca0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313624365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3313624365
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1847985733
Short name T850
Test name
Test status
Simulation time 29359449 ps
CPU time 0.73 seconds
Started Jun 06 02:43:04 PM PDT 24
Finished Jun 06 02:43:06 PM PDT 24
Peak memory 215820 kb
Host smart-181d7710-f5e6-4204-9326-b975bf07a2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847985733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1847985733
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.998942587
Short name T837
Test name
Test status
Simulation time 15027266967 ps
CPU time 61.63 seconds
Started Jun 06 02:43:06 PM PDT 24
Finished Jun 06 02:44:10 PM PDT 24
Peak memory 249740 kb
Host smart-280f4f5f-43ee-4c8f-852f-90eb1a45c803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998942587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.998942587
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1534202325
Short name T590
Test name
Test status
Simulation time 1591842127 ps
CPU time 16 seconds
Started Jun 06 02:43:05 PM PDT 24
Finished Jun 06 02:43:23 PM PDT 24
Peak memory 232784 kb
Host smart-831ad311-d4e0-48a2-8d33-4860be5fdf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534202325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1534202325
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2330178626
Short name T277
Test name
Test status
Simulation time 265447531 ps
CPU time 2.54 seconds
Started Jun 06 02:43:10 PM PDT 24
Finished Jun 06 02:43:15 PM PDT 24
Peak memory 232740 kb
Host smart-460950bf-4c18-49ad-a785-28a3b5f8993d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330178626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2330178626
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2764555978
Short name T293
Test name
Test status
Simulation time 9480740096 ps
CPU time 25.07 seconds
Started Jun 06 02:43:07 PM PDT 24
Finished Jun 06 02:43:35 PM PDT 24
Peak memory 227976 kb
Host smart-3f0548ac-3e52-43f7-8bcf-188ec887d2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764555978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2764555978
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.609178564
Short name T380
Test name
Test status
Simulation time 418182365 ps
CPU time 2.38 seconds
Started Jun 06 02:43:08 PM PDT 24
Finished Jun 06 02:43:13 PM PDT 24
Peak memory 223004 kb
Host smart-03673c63-860e-48ec-904e-3c91cfd32e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609178564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.609178564
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3505804270
Short name T533
Test name
Test status
Simulation time 9855375526 ps
CPU time 31.12 seconds
Started Jun 06 02:43:07 PM PDT 24
Finished Jun 06 02:43:40 PM PDT 24
Peak memory 249712 kb
Host smart-93937611-e660-488a-baa4-e652fdc0058b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505804270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3505804270
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3995271320
Short name T138
Test name
Test status
Simulation time 6823993479 ps
CPU time 16.29 seconds
Started Jun 06 02:43:05 PM PDT 24
Finished Jun 06 02:43:22 PM PDT 24
Peak memory 219812 kb
Host smart-5b074039-8723-4784-8fed-875ac7b768ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3995271320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3995271320
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.128181658
Short name T40
Test name
Test status
Simulation time 135904766741 ps
CPU time 210.4 seconds
Started Jun 06 02:43:08 PM PDT 24
Finished Jun 06 02:46:41 PM PDT 24
Peak memory 271404 kb
Host smart-80d2604f-7881-4e8f-959c-33ba016c618a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128181658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.128181658
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3425497951
Short name T459
Test name
Test status
Simulation time 10554159248 ps
CPU time 25.83 seconds
Started Jun 06 02:43:05 PM PDT 24
Finished Jun 06 02:43:33 PM PDT 24
Peak memory 220076 kb
Host smart-b5f7533f-dfc3-449a-826c-54cbf78b4baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425497951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3425497951
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2881062196
Short name T587
Test name
Test status
Simulation time 821436407 ps
CPU time 4.56 seconds
Started Jun 06 02:43:07 PM PDT 24
Finished Jun 06 02:43:14 PM PDT 24
Peak memory 216252 kb
Host smart-71895bcd-4464-4f8b-9698-644df87e8510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881062196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2881062196
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.19173440
Short name T344
Test name
Test status
Simulation time 11552299 ps
CPU time 0.7 seconds
Started Jun 06 02:43:13 PM PDT 24
Finished Jun 06 02:43:17 PM PDT 24
Peak memory 205416 kb
Host smart-1e83c696-686b-4c0f-b65c-34223d60daaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19173440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.19173440
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3961943611
Short name T373
Test name
Test status
Simulation time 84446236 ps
CPU time 0.95 seconds
Started Jun 06 02:43:05 PM PDT 24
Finished Jun 06 02:43:08 PM PDT 24
Peak memory 205776 kb
Host smart-76630d74-7583-4d34-ae36-3ad3ebe0824b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961943611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3961943611
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3132431895
Short name T976
Test name
Test status
Simulation time 10393215076 ps
CPU time 19.15 seconds
Started Jun 06 02:43:08 PM PDT 24
Finished Jun 06 02:43:30 PM PDT 24
Peak memory 240600 kb
Host smart-795b9ce3-1723-4020-9ba2-5d63419be0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132431895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3132431895
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1365718943
Short name T945
Test name
Test status
Simulation time 11962378 ps
CPU time 0.68 seconds
Started Jun 06 02:43:15 PM PDT 24
Finished Jun 06 02:43:18 PM PDT 24
Peak memory 205572 kb
Host smart-1945d60e-444c-4bd2-a0f0-64228d2a0710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365718943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1365718943
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.987388531
Short name T851
Test name
Test status
Simulation time 1154457443 ps
CPU time 2.38 seconds
Started Jun 06 02:43:13 PM PDT 24
Finished Jun 06 02:43:18 PM PDT 24
Peak memory 224516 kb
Host smart-fb3a35a5-c9ab-43f8-a683-2c4363effbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987388531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.987388531
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1823902432
Short name T702
Test name
Test status
Simulation time 58896690 ps
CPU time 0.77 seconds
Started Jun 06 02:43:08 PM PDT 24
Finished Jun 06 02:43:12 PM PDT 24
Peak memory 206436 kb
Host smart-ce9f157c-9844-4dfe-b6f7-13795e936245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823902432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1823902432
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.861631343
Short name T579
Test name
Test status
Simulation time 460231274 ps
CPU time 5.49 seconds
Started Jun 06 02:43:16 PM PDT 24
Finished Jun 06 02:43:25 PM PDT 24
Peak memory 224492 kb
Host smart-5bf9fe43-5998-49e9-b48e-734ed06d1f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861631343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.861631343
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1234695028
Short name T47
Test name
Test status
Simulation time 1601489161 ps
CPU time 8.5 seconds
Started Jun 06 02:43:16 PM PDT 24
Finished Jun 06 02:43:28 PM PDT 24
Peak memory 232784 kb
Host smart-f6024bdc-e5fb-45a1-b7b9-3a061e935066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234695028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1234695028
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1550481994
Short name T829
Test name
Test status
Simulation time 4540898422 ps
CPU time 41.98 seconds
Started Jun 06 02:43:09 PM PDT 24
Finished Jun 06 02:43:54 PM PDT 24
Peak memory 232748 kb
Host smart-26543446-bdaf-4b39-979b-f19817bbd20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550481994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1550481994
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2227344046
Short name T487
Test name
Test status
Simulation time 5930622352 ps
CPU time 17.14 seconds
Started Jun 06 02:43:07 PM PDT 24
Finished Jun 06 02:43:26 PM PDT 24
Peak memory 224548 kb
Host smart-2bb99da6-1404-4d38-aec7-5f565323f567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227344046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2227344046
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1297971785
Short name T551
Test name
Test status
Simulation time 47502596658 ps
CPU time 30.9 seconds
Started Jun 06 02:43:06 PM PDT 24
Finished Jun 06 02:43:39 PM PDT 24
Peak memory 248776 kb
Host smart-d94d2281-82ed-42c9-b9d4-a613ff0919d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297971785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1297971785
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2218191461
Short name T181
Test name
Test status
Simulation time 940821504 ps
CPU time 7.04 seconds
Started Jun 06 02:43:08 PM PDT 24
Finished Jun 06 02:43:18 PM PDT 24
Peak memory 227220 kb
Host smart-b6e34517-0857-446b-bf47-4637e654df02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218191461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2218191461
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1629427479
Short name T559
Test name
Test status
Simulation time 1175165249 ps
CPU time 13.57 seconds
Started Jun 06 02:43:14 PM PDT 24
Finished Jun 06 02:43:30 PM PDT 24
Peak memory 218780 kb
Host smart-ac5cbc6c-1dd6-4c2a-868f-7e901e9354c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1629427479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1629427479
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2497928873
Short name T149
Test name
Test status
Simulation time 72431674 ps
CPU time 1.14 seconds
Started Jun 06 02:43:15 PM PDT 24
Finished Jun 06 02:43:19 PM PDT 24
Peak memory 207108 kb
Host smart-7c928ce2-0345-4a1f-ae0d-748646294fdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497928873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2497928873
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2210325632
Short name T321
Test name
Test status
Simulation time 2075842837 ps
CPU time 31.04 seconds
Started Jun 06 02:43:25 PM PDT 24
Finished Jun 06 02:43:58 PM PDT 24
Peak memory 216320 kb
Host smart-57368dbd-570c-4725-b129-18b7f8c28800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210325632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2210325632
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2544124937
Short name T639
Test name
Test status
Simulation time 34353399 ps
CPU time 0.72 seconds
Started Jun 06 02:43:06 PM PDT 24
Finished Jun 06 02:43:09 PM PDT 24
Peak memory 205544 kb
Host smart-4f991d23-a657-4791-8be9-465907004bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544124937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2544124937
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3368261637
Short name T17
Test name
Test status
Simulation time 85792354 ps
CPU time 3.84 seconds
Started Jun 06 02:43:05 PM PDT 24
Finished Jun 06 02:43:11 PM PDT 24
Peak memory 216524 kb
Host smart-d09b1e87-200c-4740-bb50-9d4adb32ddbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368261637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3368261637
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.4149152584
Short name T541
Test name
Test status
Simulation time 12864962 ps
CPU time 0.69 seconds
Started Jun 06 02:43:10 PM PDT 24
Finished Jun 06 02:43:13 PM PDT 24
Peak memory 205388 kb
Host smart-0dd69dee-ed02-42fa-8f65-bbca70435de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149152584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4149152584
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.112125918
Short name T729
Test name
Test status
Simulation time 711938610 ps
CPU time 6.25 seconds
Started Jun 06 02:43:05 PM PDT 24
Finished Jun 06 02:43:13 PM PDT 24
Peak memory 232732 kb
Host smart-311eb92d-31ec-45eb-bca3-6614c84fddd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112125918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.112125918
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.34188145
Short name T681
Test name
Test status
Simulation time 19982265 ps
CPU time 0.69 seconds
Started Jun 06 02:43:14 PM PDT 24
Finished Jun 06 02:43:18 PM PDT 24
Peak memory 205148 kb
Host smart-c1689d1d-f94b-4d55-b451-ced3362740ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34188145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.34188145
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2290872130
Short name T810
Test name
Test status
Simulation time 126154718 ps
CPU time 2.63 seconds
Started Jun 06 02:43:19 PM PDT 24
Finished Jun 06 02:43:23 PM PDT 24
Peak memory 232692 kb
Host smart-0da7f341-dd0d-4e30-934f-060a144cf310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290872130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2290872130
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3078750554
Short name T500
Test name
Test status
Simulation time 14903041 ps
CPU time 0.77 seconds
Started Jun 06 02:43:19 PM PDT 24
Finished Jun 06 02:43:22 PM PDT 24
Peak memory 206976 kb
Host smart-1ad2f08a-b643-42ee-b4dc-7de6d126be88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078750554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3078750554
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3073140007
Short name T607
Test name
Test status
Simulation time 9005398902 ps
CPU time 41.18 seconds
Started Jun 06 02:43:18 PM PDT 24
Finished Jun 06 02:44:02 PM PDT 24
Peak memory 249236 kb
Host smart-93bb3a93-a43c-4ac8-ab9e-ead51d1135cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073140007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3073140007
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2470877415
Short name T555
Test name
Test status
Simulation time 48450325970 ps
CPU time 171.09 seconds
Started Jun 06 02:43:18 PM PDT 24
Finished Jun 06 02:46:11 PM PDT 24
Peak memory 253764 kb
Host smart-4f256b25-3232-4c27-bc86-5af24cfc848d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470877415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2470877415
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1206827189
Short name T828
Test name
Test status
Simulation time 91995375 ps
CPU time 0.77 seconds
Started Jun 06 02:43:17 PM PDT 24
Finished Jun 06 02:43:21 PM PDT 24
Peak memory 216952 kb
Host smart-acecc32e-4685-41ef-a56c-8d4fffa22fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206827189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1206827189
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3771443833
Short name T752
Test name
Test status
Simulation time 4777440363 ps
CPU time 35.82 seconds
Started Jun 06 02:43:15 PM PDT 24
Finished Jun 06 02:43:54 PM PDT 24
Peak memory 249196 kb
Host smart-75d71a9f-dd46-4a07-9410-4e1fdb40def7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771443833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3771443833
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.146593833
Short name T550
Test name
Test status
Simulation time 6128928970 ps
CPU time 16.41 seconds
Started Jun 06 02:43:16 PM PDT 24
Finished Jun 06 02:43:36 PM PDT 24
Peak memory 232848 kb
Host smart-69605f48-b61f-41f6-a465-3eb407df721e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146593833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.146593833
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2866511883
Short name T167
Test name
Test status
Simulation time 1131583217 ps
CPU time 10.29 seconds
Started Jun 06 02:43:16 PM PDT 24
Finished Jun 06 02:43:29 PM PDT 24
Peak memory 224512 kb
Host smart-20206ed7-1bb6-4928-a9f9-40618ba34134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866511883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2866511883
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.552423212
Short name T943
Test name
Test status
Simulation time 1274722819 ps
CPU time 3.73 seconds
Started Jun 06 02:43:16 PM PDT 24
Finished Jun 06 02:43:23 PM PDT 24
Peak memory 232664 kb
Host smart-10f7a23c-0a2d-4dac-bf58-44ee93a6a622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552423212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.552423212
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1545479316
Short name T402
Test name
Test status
Simulation time 3257829509 ps
CPU time 15.43 seconds
Started Jun 06 02:43:18 PM PDT 24
Finished Jun 06 02:43:36 PM PDT 24
Peak memory 232752 kb
Host smart-c8f05e8c-9d04-4bed-a4dd-6bdae0b554d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545479316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1545479316
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1599934350
Short name T432
Test name
Test status
Simulation time 4722803161 ps
CPU time 7.32 seconds
Started Jun 06 02:43:16 PM PDT 24
Finished Jun 06 02:43:27 PM PDT 24
Peak memory 220596 kb
Host smart-893f6d92-1bc0-40a5-b9a9-def2ee4f89a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1599934350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1599934350
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2969627287
Short name T675
Test name
Test status
Simulation time 4578667873 ps
CPU time 32.68 seconds
Started Jun 06 02:43:13 PM PDT 24
Finished Jun 06 02:43:49 PM PDT 24
Peak memory 219940 kb
Host smart-88567a65-8439-400a-b67e-610adc44f25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969627287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2969627287
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.37593432
Short name T911
Test name
Test status
Simulation time 1812895568 ps
CPU time 3.39 seconds
Started Jun 06 02:43:21 PM PDT 24
Finished Jun 06 02:43:26 PM PDT 24
Peak memory 216272 kb
Host smart-6fcac121-8a7a-4805-a784-c1927027323c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37593432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.37593432
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.998064168
Short name T696
Test name
Test status
Simulation time 21241869 ps
CPU time 0.96 seconds
Started Jun 06 02:43:15 PM PDT 24
Finished Jun 06 02:43:19 PM PDT 24
Peak memory 207912 kb
Host smart-0aa91803-e2ae-41e0-8d48-3f291803b630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998064168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.998064168
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1728319212
Short name T732
Test name
Test status
Simulation time 78492388 ps
CPU time 0.67 seconds
Started Jun 06 02:43:21 PM PDT 24
Finished Jun 06 02:43:23 PM PDT 24
Peak memory 205452 kb
Host smart-d4032e7a-8887-447d-b94b-c58f9339631e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728319212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1728319212
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1039908359
Short name T36
Test name
Test status
Simulation time 6548813832 ps
CPU time 12.22 seconds
Started Jun 06 02:43:14 PM PDT 24
Finished Jun 06 02:43:29 PM PDT 24
Peak memory 239900 kb
Host smart-5047f32b-be6a-4a63-8828-b1f1e2cb2e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039908359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1039908359
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2037959222
Short name T427
Test name
Test status
Simulation time 19015055 ps
CPU time 0.73 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:42:02 PM PDT 24
Peak memory 205216 kb
Host smart-59b79b54-7fe9-4c8f-8c5e-0dfd73f0d551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037959222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
037959222
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3395852899
Short name T942
Test name
Test status
Simulation time 124570090 ps
CPU time 2.4 seconds
Started Jun 06 02:42:05 PM PDT 24
Finished Jun 06 02:42:10 PM PDT 24
Peak memory 232676 kb
Host smart-79c64ab9-a23b-4d65-bba7-3479c3deea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395852899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3395852899
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1496017210
Short name T457
Test name
Test status
Simulation time 29124961 ps
CPU time 0.71 seconds
Started Jun 06 02:41:55 PM PDT 24
Finished Jun 06 02:41:59 PM PDT 24
Peak memory 205424 kb
Host smart-b127f6fa-8794-4379-8f21-07ffeca1157c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496017210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1496017210
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.266284610
Short name T236
Test name
Test status
Simulation time 18573418291 ps
CPU time 80.39 seconds
Started Jun 06 02:41:58 PM PDT 24
Finished Jun 06 02:43:21 PM PDT 24
Peak memory 256612 kb
Host smart-7e9b34ae-19c5-4aa3-8782-7c2ed53cd109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266284610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.266284610
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.115245582
Short name T3
Test name
Test status
Simulation time 4346155280 ps
CPU time 21.01 seconds
Started Jun 06 02:42:06 PM PDT 24
Finished Jun 06 02:42:29 PM PDT 24
Peak memory 233912 kb
Host smart-1d315b1f-2ed6-4097-bddd-f84d42258d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115245582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.115245582
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.33244059
Short name T450
Test name
Test status
Simulation time 11835526305 ps
CPU time 65.42 seconds
Started Jun 06 02:42:04 PM PDT 24
Finished Jun 06 02:43:11 PM PDT 24
Peak memory 255060 kb
Host smart-0ec0cc90-3875-4980-95d3-e00ddc00a654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33244059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.33244059
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1362205831
Short name T319
Test name
Test status
Simulation time 3637356069 ps
CPU time 20.63 seconds
Started Jun 06 02:42:05 PM PDT 24
Finished Jun 06 02:42:28 PM PDT 24
Peak memory 224592 kb
Host smart-6348f7c0-9b45-49c4-b46d-f65e116dd9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362205831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1362205831
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.104826579
Short name T173
Test name
Test status
Simulation time 2508849370 ps
CPU time 19.71 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:42:29 PM PDT 24
Peak memory 232804 kb
Host smart-9881cd29-269d-4644-b943-11b16df5d2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104826579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.104826579
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1993021407
Short name T301
Test name
Test status
Simulation time 25923168359 ps
CPU time 26.25 seconds
Started Jun 06 02:41:58 PM PDT 24
Finished Jun 06 02:42:27 PM PDT 24
Peak memory 224568 kb
Host smart-f8da63d7-8ff4-48d2-a0c6-70cc574d754f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993021407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1993021407
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2848970934
Short name T528
Test name
Test status
Simulation time 31491100 ps
CPU time 1.05 seconds
Started Jun 06 02:41:56 PM PDT 24
Finished Jun 06 02:42:01 PM PDT 24
Peak memory 216528 kb
Host smart-f3b59369-3be7-4dd2-99bb-bc19088d5e98
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848970934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2848970934
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1185203102
Short name T303
Test name
Test status
Simulation time 1588301038 ps
CPU time 8.1 seconds
Started Jun 06 02:41:56 PM PDT 24
Finished Jun 06 02:42:08 PM PDT 24
Peak memory 232716 kb
Host smart-868bcb08-77e1-4c90-a3e6-243a1b5e5d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185203102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1185203102
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.591821056
Short name T865
Test name
Test status
Simulation time 277150626 ps
CPU time 6.38 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:42:07 PM PDT 24
Peak memory 224452 kb
Host smart-3a9ff76a-b2c5-4278-bbfa-4e6be4969800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591821056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.591821056
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3643755264
Short name T80
Test name
Test status
Simulation time 278790357 ps
CPU time 3.12 seconds
Started Jun 06 02:42:04 PM PDT 24
Finished Jun 06 02:42:09 PM PDT 24
Peak memory 219036 kb
Host smart-6da81576-cdaf-4cf2-a026-efcc8f8ac738
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3643755264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3643755264
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1415313943
Short name T58
Test name
Test status
Simulation time 38902823 ps
CPU time 0.99 seconds
Started Jun 06 02:41:59 PM PDT 24
Finished Jun 06 02:42:03 PM PDT 24
Peak memory 234912 kb
Host smart-09de1dee-2866-444e-84c2-5bf44a09356b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415313943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1415313943
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1334279751
Short name T662
Test name
Test status
Simulation time 75794940 ps
CPU time 1.01 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:42:02 PM PDT 24
Peak memory 206844 kb
Host smart-eca7f7e9-ae25-4dcd-900e-4b46fe1ab88c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334279751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1334279751
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.611937136
Short name T23
Test name
Test status
Simulation time 1353168195 ps
CPU time 13.94 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:42:23 PM PDT 24
Peak memory 216496 kb
Host smart-ee43358a-4df5-4678-aab4-7d7f64e49e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611937136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.611937136
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3639323479
Short name T353
Test name
Test status
Simulation time 113291681404 ps
CPU time 20.76 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:42:21 PM PDT 24
Peak memory 216288 kb
Host smart-89b7aa6e-a95c-482b-91ea-0b950779929d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639323479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3639323479
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.725022711
Short name T423
Test name
Test status
Simulation time 116209839 ps
CPU time 1.18 seconds
Started Jun 06 02:41:55 PM PDT 24
Finished Jun 06 02:42:00 PM PDT 24
Peak memory 207076 kb
Host smart-f53876c8-962f-475d-a4d0-c13913b7f5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725022711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.725022711
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2545626052
Short name T77
Test name
Test status
Simulation time 60974621 ps
CPU time 0.83 seconds
Started Jun 06 02:42:10 PM PDT 24
Finished Jun 06 02:42:13 PM PDT 24
Peak memory 205756 kb
Host smart-23c676d9-1b35-4ac0-b412-9a742e7e8424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545626052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2545626052
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1394605443
Short name T179
Test name
Test status
Simulation time 47297110155 ps
CPU time 37.42 seconds
Started Jun 06 02:42:04 PM PDT 24
Finished Jun 06 02:42:43 PM PDT 24
Peak memory 232816 kb
Host smart-43685305-6f74-4d4e-a74b-ac7160c8d055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394605443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1394605443
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3414499859
Short name T1
Test name
Test status
Simulation time 190491424 ps
CPU time 0.7 seconds
Started Jun 06 02:43:13 PM PDT 24
Finished Jun 06 02:43:17 PM PDT 24
Peak memory 205568 kb
Host smart-d6bf78ad-5987-4963-9eb5-d4715ec8b298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414499859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3414499859
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.490504773
Short name T845
Test name
Test status
Simulation time 155218001 ps
CPU time 2.6 seconds
Started Jun 06 02:43:12 PM PDT 24
Finished Jun 06 02:43:17 PM PDT 24
Peak memory 224468 kb
Host smart-c617f453-4b6c-4332-b810-a8d618eff918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490504773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.490504773
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2044065850
Short name T860
Test name
Test status
Simulation time 68123867 ps
CPU time 0.77 seconds
Started Jun 06 02:43:19 PM PDT 24
Finished Jun 06 02:43:22 PM PDT 24
Peak memory 206984 kb
Host smart-1260cd94-ff1b-4257-b764-5c3c1eadef13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044065850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2044065850
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1168410204
Short name T835
Test name
Test status
Simulation time 22760912767 ps
CPU time 99.55 seconds
Started Jun 06 02:43:15 PM PDT 24
Finished Jun 06 02:44:57 PM PDT 24
Peak memory 236612 kb
Host smart-d86ce014-ef48-4e5d-940e-ee41a6de87f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168410204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1168410204
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1930667227
Short name T12
Test name
Test status
Simulation time 3418662553 ps
CPU time 43.29 seconds
Started Jun 06 02:43:15 PM PDT 24
Finished Jun 06 02:44:02 PM PDT 24
Peak memory 224728 kb
Host smart-6db5e549-b4c2-4df6-b49a-88dfb31be4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930667227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1930667227
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2752505154
Short name T519
Test name
Test status
Simulation time 5072517041 ps
CPU time 66.64 seconds
Started Jun 06 02:43:21 PM PDT 24
Finished Jun 06 02:44:29 PM PDT 24
Peak memory 232952 kb
Host smart-e7daa8de-8f83-473e-9d83-cf4240cbc9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752505154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2752505154
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2736958122
Short name T950
Test name
Test status
Simulation time 578531139 ps
CPU time 7.65 seconds
Started Jun 06 02:43:17 PM PDT 24
Finished Jun 06 02:43:28 PM PDT 24
Peak memory 234240 kb
Host smart-c1e3fbe7-4e33-46f1-a938-6765a779180a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736958122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2736958122
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3586750825
Short name T787
Test name
Test status
Simulation time 585103662 ps
CPU time 6.21 seconds
Started Jun 06 02:43:18 PM PDT 24
Finished Jun 06 02:43:27 PM PDT 24
Peak memory 232696 kb
Host smart-8c0c927b-50e0-4cf8-9237-8db2cdf83458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586750825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3586750825
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.576540405
Short name T7
Test name
Test status
Simulation time 1008276361 ps
CPU time 17.12 seconds
Started Jun 06 02:43:14 PM PDT 24
Finished Jun 06 02:43:34 PM PDT 24
Peak memory 249552 kb
Host smart-529b23df-e2b2-4814-a765-fd9ee4056105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576540405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.576540405
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1554254967
Short name T302
Test name
Test status
Simulation time 13640981240 ps
CPU time 13.52 seconds
Started Jun 06 02:43:15 PM PDT 24
Finished Jun 06 02:43:31 PM PDT 24
Peak memory 224624 kb
Host smart-b77d6bbe-6774-474c-a226-aab8bed38542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554254967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1554254967
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2301280883
Short name T478
Test name
Test status
Simulation time 5109366229 ps
CPU time 3.69 seconds
Started Jun 06 02:43:14 PM PDT 24
Finished Jun 06 02:43:21 PM PDT 24
Peak memory 224528 kb
Host smart-4532c608-32c1-4174-869b-283ebc0466cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301280883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2301280883
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1284646269
Short name T833
Test name
Test status
Simulation time 2633080534 ps
CPU time 9.61 seconds
Started Jun 06 02:43:12 PM PDT 24
Finished Jun 06 02:43:24 PM PDT 24
Peak memory 223112 kb
Host smart-b31cfb39-4313-4b22-bad2-2e814b9d5120
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1284646269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1284646269
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.467245608
Short name T151
Test name
Test status
Simulation time 153036000737 ps
CPU time 735.79 seconds
Started Jun 06 02:43:16 PM PDT 24
Finished Jun 06 02:55:35 PM PDT 24
Peak memory 266448 kb
Host smart-7a096299-1559-4b4b-8137-9519e5bf9590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467245608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.467245608
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.80639357
Short name T329
Test name
Test status
Simulation time 24586093168 ps
CPU time 36.08 seconds
Started Jun 06 02:43:15 PM PDT 24
Finished Jun 06 02:43:54 PM PDT 24
Peak memory 216360 kb
Host smart-daf35c1a-53cf-4f84-b438-6e64cef8e37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80639357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.80639357
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4133990557
Short name T560
Test name
Test status
Simulation time 80121487 ps
CPU time 1.37 seconds
Started Jun 06 02:43:22 PM PDT 24
Finished Jun 06 02:43:25 PM PDT 24
Peak memory 216384 kb
Host smart-91b6fd19-0abd-4312-afac-b4d9ed2a862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133990557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4133990557
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.942225447
Short name T888
Test name
Test status
Simulation time 94152748 ps
CPU time 1.06 seconds
Started Jun 06 02:43:15 PM PDT 24
Finished Jun 06 02:43:19 PM PDT 24
Peak memory 206824 kb
Host smart-25d40127-5fd6-4778-9cf4-453979c349f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942225447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.942225447
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2882575612
Short name T205
Test name
Test status
Simulation time 1136076452 ps
CPU time 4.35 seconds
Started Jun 06 02:43:15 PM PDT 24
Finished Jun 06 02:43:22 PM PDT 24
Peak memory 224540 kb
Host smart-ceb1d74e-15b3-4fa4-81bc-727e779bc972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882575612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2882575612
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2390066560
Short name T767
Test name
Test status
Simulation time 25906012 ps
CPU time 0.72 seconds
Started Jun 06 02:43:26 PM PDT 24
Finished Jun 06 02:43:28 PM PDT 24
Peak memory 204512 kb
Host smart-1b3c2a27-46bb-44db-9d1d-edfdd42e7d05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390066560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2390066560
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2691723285
Short name T631
Test name
Test status
Simulation time 285900035 ps
CPU time 2.32 seconds
Started Jun 06 02:43:23 PM PDT 24
Finished Jun 06 02:43:27 PM PDT 24
Peak memory 224520 kb
Host smart-789f4f49-c650-4284-addd-903f22536c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691723285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2691723285
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1592404294
Short name T123
Test name
Test status
Simulation time 46077353 ps
CPU time 0.75 seconds
Started Jun 06 02:43:16 PM PDT 24
Finished Jun 06 02:43:20 PM PDT 24
Peak memory 206512 kb
Host smart-8c015201-078d-4900-993d-36d22842c9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592404294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1592404294
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1320253769
Short name T861
Test name
Test status
Simulation time 313013336 ps
CPU time 5.73 seconds
Started Jun 06 02:43:24 PM PDT 24
Finished Jun 06 02:43:31 PM PDT 24
Peak memory 224520 kb
Host smart-397e7097-fa58-4673-b410-2d431324e47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320253769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1320253769
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.448772719
Short name T284
Test name
Test status
Simulation time 20892829986 ps
CPU time 53.94 seconds
Started Jun 06 02:43:24 PM PDT 24
Finished Jun 06 02:44:20 PM PDT 24
Peak memory 249356 kb
Host smart-b6378709-a820-4535-94b7-095a62932623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448772719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.448772719
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2929365863
Short name T343
Test name
Test status
Simulation time 4407276303 ps
CPU time 70.94 seconds
Started Jun 06 02:43:23 PM PDT 24
Finished Jun 06 02:44:35 PM PDT 24
Peak memory 249304 kb
Host smart-fba07d25-161b-4249-98c0-b846344746d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929365863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2929365863
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1579576115
Short name T318
Test name
Test status
Simulation time 1565043038 ps
CPU time 10 seconds
Started Jun 06 02:43:24 PM PDT 24
Finished Jun 06 02:43:35 PM PDT 24
Peak memory 249124 kb
Host smart-7e46ed0d-016d-41a6-abc4-a65b91b80cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579576115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1579576115
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3577092592
Short name T299
Test name
Test status
Simulation time 268068093 ps
CPU time 6.06 seconds
Started Jun 06 02:43:27 PM PDT 24
Finished Jun 06 02:43:34 PM PDT 24
Peak memory 232756 kb
Host smart-ec7ed0cb-1861-4c47-9a96-7fdbf0adf982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577092592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3577092592
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2126913149
Short name T797
Test name
Test status
Simulation time 6839005549 ps
CPU time 21.22 seconds
Started Jun 06 02:43:26 PM PDT 24
Finished Jun 06 02:43:49 PM PDT 24
Peak memory 224528 kb
Host smart-10eaf8ff-95aa-4c30-8dba-9d567a23a440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126913149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2126913149
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2011377421
Short name T968
Test name
Test status
Simulation time 1242664586 ps
CPU time 8.2 seconds
Started Jun 06 02:43:17 PM PDT 24
Finished Jun 06 02:43:28 PM PDT 24
Peak memory 240324 kb
Host smart-152ef408-ab07-4ea7-82ef-7d91a0025b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011377421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2011377421
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3699130951
Short name T562
Test name
Test status
Simulation time 1144290683 ps
CPU time 4.58 seconds
Started Jun 06 02:43:21 PM PDT 24
Finished Jun 06 02:43:28 PM PDT 24
Peak memory 224684 kb
Host smart-82ae9133-0061-4fc0-a01d-1e971a7fd461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699130951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3699130951
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1997806301
Short name T611
Test name
Test status
Simulation time 91809476 ps
CPU time 3.8 seconds
Started Jun 06 02:43:27 PM PDT 24
Finished Jun 06 02:43:32 PM PDT 24
Peak memory 222892 kb
Host smart-af32e5c3-be73-46be-a671-a01a86887b71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1997806301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1997806301
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2112850115
Short name T53
Test name
Test status
Simulation time 43307817334 ps
CPU time 202.39 seconds
Started Jun 06 02:43:23 PM PDT 24
Finished Jun 06 02:46:47 PM PDT 24
Peak memory 253824 kb
Host smart-61e96b74-bc91-4600-b45c-e205d1e0584e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112850115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2112850115
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4016504381
Short name T741
Test name
Test status
Simulation time 8287992346 ps
CPU time 40.13 seconds
Started Jun 06 02:43:21 PM PDT 24
Finished Jun 06 02:44:03 PM PDT 24
Peak memory 216528 kb
Host smart-6a9f919d-8764-499b-8daa-83ddf3787969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016504381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4016504381
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.474225834
Short name T650
Test name
Test status
Simulation time 410443007 ps
CPU time 2.09 seconds
Started Jun 06 02:43:14 PM PDT 24
Finished Jun 06 02:43:18 PM PDT 24
Peak memory 207780 kb
Host smart-e50a60dc-0040-4899-b08d-f8ab2b486131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474225834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.474225834
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1245089625
Short name T359
Test name
Test status
Simulation time 37059560 ps
CPU time 1.02 seconds
Started Jun 06 02:43:21 PM PDT 24
Finished Jun 06 02:43:23 PM PDT 24
Peak memory 207904 kb
Host smart-4188c988-5334-479e-a133-48fb14b25f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245089625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1245089625
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3507428631
Short name T867
Test name
Test status
Simulation time 346517559 ps
CPU time 0.76 seconds
Started Jun 06 02:43:21 PM PDT 24
Finished Jun 06 02:43:23 PM PDT 24
Peak memory 205968 kb
Host smart-f956bbe5-4b93-4641-9611-79fd46afeacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507428631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3507428631
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1999548960
Short name T632
Test name
Test status
Simulation time 82949484 ps
CPU time 2.79 seconds
Started Jun 06 02:43:26 PM PDT 24
Finished Jun 06 02:43:31 PM PDT 24
Peak memory 232740 kb
Host smart-3a73f918-ca17-4f7d-810d-0ce714dc80ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999548960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1999548960
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1008192220
Short name T564
Test name
Test status
Simulation time 30561334 ps
CPU time 0.72 seconds
Started Jun 06 02:43:27 PM PDT 24
Finished Jun 06 02:43:29 PM PDT 24
Peak memory 205216 kb
Host smart-1ed10af5-5c5a-472d-805f-03c5cc1e45e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008192220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1008192220
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.308468952
Short name T930
Test name
Test status
Simulation time 116566172 ps
CPU time 3.08 seconds
Started Jun 06 02:43:24 PM PDT 24
Finished Jun 06 02:43:28 PM PDT 24
Peak memory 224580 kb
Host smart-71cadb4c-b24c-49fc-9293-d797c6b13909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308468952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.308468952
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1991484457
Short name T360
Test name
Test status
Simulation time 56373924 ps
CPU time 0.78 seconds
Started Jun 06 02:43:23 PM PDT 24
Finished Jun 06 02:43:25 PM PDT 24
Peak memory 206508 kb
Host smart-03b7b7e3-f650-436c-8547-2667dd9fcde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991484457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1991484457
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2931549008
Short name T250
Test name
Test status
Simulation time 801123261 ps
CPU time 15.07 seconds
Started Jun 06 02:43:25 PM PDT 24
Finished Jun 06 02:43:41 PM PDT 24
Peak memory 240952 kb
Host smart-f490b0f6-84a7-409d-b165-2654e2e18582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931549008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2931549008
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3125886579
Short name T254
Test name
Test status
Simulation time 1269481157 ps
CPU time 31.25 seconds
Started Jun 06 02:43:24 PM PDT 24
Finished Jun 06 02:43:57 PM PDT 24
Peak memory 240764 kb
Host smart-f9ed82ae-b551-4b21-98a4-33e856adee51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125886579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3125886579
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1770364841
Short name T521
Test name
Test status
Simulation time 341563705 ps
CPU time 6.6 seconds
Started Jun 06 02:43:25 PM PDT 24
Finished Jun 06 02:43:33 PM PDT 24
Peak memory 224540 kb
Host smart-9b9291a3-6b3a-42c7-8624-527cb57a41be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770364841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1770364841
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1971324986
Short name T281
Test name
Test status
Simulation time 6981822065 ps
CPU time 18.37 seconds
Started Jun 06 02:43:24 PM PDT 24
Finished Jun 06 02:43:44 PM PDT 24
Peak memory 232816 kb
Host smart-878f3b42-111b-4b76-8105-73892e8f6267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971324986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1971324986
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3126789958
Short name T356
Test name
Test status
Simulation time 30331067 ps
CPU time 2.64 seconds
Started Jun 06 02:43:26 PM PDT 24
Finished Jun 06 02:43:30 PM PDT 24
Peak memory 232512 kb
Host smart-d4cfd52a-cea9-4364-9376-587fe0656e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126789958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3126789958
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1446305155
Short name T221
Test name
Test status
Simulation time 2013600568 ps
CPU time 9.07 seconds
Started Jun 06 02:43:25 PM PDT 24
Finished Jun 06 02:43:35 PM PDT 24
Peak memory 240832 kb
Host smart-218c48da-6b6f-4d79-9519-5eaea85ec612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446305155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1446305155
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1713910333
Short name T728
Test name
Test status
Simulation time 504201052 ps
CPU time 3.92 seconds
Started Jun 06 02:43:26 PM PDT 24
Finished Jun 06 02:43:31 PM PDT 24
Peak memory 232680 kb
Host smart-9cabb086-ede0-4a34-929e-970f761eb68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713910333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1713910333
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2284421511
Short name T967
Test name
Test status
Simulation time 867307324 ps
CPU time 8.76 seconds
Started Jun 06 02:43:25 PM PDT 24
Finished Jun 06 02:43:36 PM PDT 24
Peak memory 220468 kb
Host smart-6d95c126-2897-459c-80a5-cfaf469905e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2284421511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2284421511
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3503486760
Short name T157
Test name
Test status
Simulation time 100609861 ps
CPU time 1.06 seconds
Started Jun 06 02:43:26 PM PDT 24
Finished Jun 06 02:43:29 PM PDT 24
Peak memory 206772 kb
Host smart-c80fc598-9087-4842-a078-c9c4785a8953
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503486760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3503486760
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1140664227
Short name T885
Test name
Test status
Simulation time 7359331568 ps
CPU time 18.91 seconds
Started Jun 06 02:43:26 PM PDT 24
Finished Jun 06 02:43:46 PM PDT 24
Peak memory 216420 kb
Host smart-1ac8da19-068b-4ddf-9432-af647e3c45d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140664227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1140664227
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1585168717
Short name T638
Test name
Test status
Simulation time 15145722692 ps
CPU time 17.99 seconds
Started Jun 06 02:43:26 PM PDT 24
Finished Jun 06 02:43:46 PM PDT 24
Peak memory 216260 kb
Host smart-be4a8e50-d391-42e2-a6f1-c612b2fcb95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585168717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1585168717
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2855423874
Short name T429
Test name
Test status
Simulation time 34325697 ps
CPU time 1.09 seconds
Started Jun 06 02:43:23 PM PDT 24
Finished Jun 06 02:43:26 PM PDT 24
Peak memory 207856 kb
Host smart-016305a1-dbe7-4a86-9768-0d7b7529265f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855423874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2855423874
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2069575235
Short name T355
Test name
Test status
Simulation time 21045401 ps
CPU time 0.75 seconds
Started Jun 06 02:43:25 PM PDT 24
Finished Jun 06 02:43:27 PM PDT 24
Peak memory 205748 kb
Host smart-877eccec-3e50-4903-9391-1fbab990965c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069575235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2069575235
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3211374953
Short name T174
Test name
Test status
Simulation time 660341519 ps
CPU time 7.61 seconds
Started Jun 06 02:43:25 PM PDT 24
Finished Jun 06 02:43:34 PM PDT 24
Peak memory 232736 kb
Host smart-be82a294-d1e5-4d39-9e2d-667426085a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211374953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3211374953
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3845905318
Short name T805
Test name
Test status
Simulation time 14030753 ps
CPU time 0.72 seconds
Started Jun 06 02:43:33 PM PDT 24
Finished Jun 06 02:43:35 PM PDT 24
Peak memory 204552 kb
Host smart-65243c18-7600-4b41-916e-30e9d498ee0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845905318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3845905318
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4000901488
Short name T553
Test name
Test status
Simulation time 204688879 ps
CPU time 5.02 seconds
Started Jun 06 02:43:34 PM PDT 24
Finished Jun 06 02:43:41 PM PDT 24
Peak memory 232380 kb
Host smart-c71c5949-2931-4419-82ed-624114d30a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000901488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4000901488
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.184149
Short name T884
Test name
Test status
Simulation time 21675412 ps
CPU time 0.77 seconds
Started Jun 06 02:43:24 PM PDT 24
Finished Jun 06 02:43:26 PM PDT 24
Peak memory 205416 kb
Host smart-bf6993b5-76b8-4f29-9a12-7e6668852a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.184149
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1927144782
Short name T13
Test name
Test status
Simulation time 99027931 ps
CPU time 3.83 seconds
Started Jun 06 02:43:30 PM PDT 24
Finished Jun 06 02:43:35 PM PDT 24
Peak memory 234484 kb
Host smart-0b8e8ef4-7652-42b6-b41c-5c19d4dc5306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927144782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1927144782
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.205092573
Short name T28
Test name
Test status
Simulation time 28652706196 ps
CPU time 118.14 seconds
Started Jun 06 02:43:35 PM PDT 24
Finished Jun 06 02:45:35 PM PDT 24
Peak memory 254196 kb
Host smart-18994f81-d672-4113-811f-2051274e9bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205092573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.205092573
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.4047285127
Short name T244
Test name
Test status
Simulation time 20761816807 ps
CPU time 190.79 seconds
Started Jun 06 02:43:35 PM PDT 24
Finished Jun 06 02:46:49 PM PDT 24
Peak memory 240904 kb
Host smart-bd0adbcd-23c1-4359-b5ce-d84c6cc1c706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047285127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.4047285127
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3251943091
Short name T397
Test name
Test status
Simulation time 290926736 ps
CPU time 7.56 seconds
Started Jun 06 02:43:33 PM PDT 24
Finished Jun 06 02:43:42 PM PDT 24
Peak memory 238052 kb
Host smart-0fc24e14-1102-479e-b83b-5665180d7dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251943091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3251943091
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3143097817
Short name T308
Test name
Test status
Simulation time 1782653591 ps
CPU time 5.29 seconds
Started Jun 06 02:43:25 PM PDT 24
Finished Jun 06 02:43:32 PM PDT 24
Peak memory 232728 kb
Host smart-0ac44352-7d70-4e49-b65c-4543765314f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143097817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3143097817
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.379275615
Short name T184
Test name
Test status
Simulation time 5047428392 ps
CPU time 53.22 seconds
Started Jun 06 02:43:30 PM PDT 24
Finished Jun 06 02:44:25 PM PDT 24
Peak memory 232764 kb
Host smart-6cfd219b-d0fe-4c0e-8d41-46ea121c13b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379275615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.379275615
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1827717273
Short name T227
Test name
Test status
Simulation time 31212072950 ps
CPU time 24.66 seconds
Started Jun 06 02:43:25 PM PDT 24
Finished Jun 06 02:43:51 PM PDT 24
Peak memory 232740 kb
Host smart-99fa2f3f-b380-4c05-b138-70f96ee74115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827717273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1827717273
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.786218021
Short name T215
Test name
Test status
Simulation time 495396426 ps
CPU time 3.97 seconds
Started Jun 06 02:43:26 PM PDT 24
Finished Jun 06 02:43:32 PM PDT 24
Peak memory 224428 kb
Host smart-cb9cb994-d428-4974-9ac4-9dea5d1a0f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786218021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.786218021
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.807579048
Short name T854
Test name
Test status
Simulation time 993500640 ps
CPU time 15.14 seconds
Started Jun 06 02:43:35 PM PDT 24
Finished Jun 06 02:43:53 PM PDT 24
Peak memory 218784 kb
Host smart-966ffd39-2921-42cc-84ca-22348d1d4882
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=807579048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.807579048
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2896356736
Short name T304
Test name
Test status
Simulation time 18730468313 ps
CPU time 222.03 seconds
Started Jun 06 02:43:32 PM PDT 24
Finished Jun 06 02:47:15 PM PDT 24
Peak memory 255092 kb
Host smart-6f96f469-6f0f-4f15-8f55-0dd48b1d159f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896356736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2896356736
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2599646101
Short name T322
Test name
Test status
Simulation time 4626884135 ps
CPU time 30.32 seconds
Started Jun 06 02:43:33 PM PDT 24
Finished Jun 06 02:44:06 PM PDT 24
Peak memory 216360 kb
Host smart-d8e425f6-88c0-4a51-9144-19610b524d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599646101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2599646101
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.412114779
Short name T757
Test name
Test status
Simulation time 6000217489 ps
CPU time 8.58 seconds
Started Jun 06 02:43:26 PM PDT 24
Finished Jun 06 02:43:37 PM PDT 24
Peak memory 216336 kb
Host smart-ebc6ef59-8bf5-4e91-af6f-ef1909063ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412114779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.412114779
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4202323464
Short name T464
Test name
Test status
Simulation time 11759269 ps
CPU time 0.74 seconds
Started Jun 06 02:43:24 PM PDT 24
Finished Jun 06 02:43:26 PM PDT 24
Peak memory 205856 kb
Host smart-3c906415-53ee-4eff-8b2d-8669630cfd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202323464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4202323464
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.767850681
Short name T666
Test name
Test status
Simulation time 158357071 ps
CPU time 0.82 seconds
Started Jun 06 02:43:23 PM PDT 24
Finished Jun 06 02:43:25 PM PDT 24
Peak memory 205728 kb
Host smart-6b589df0-525e-4dd3-aa50-e0ca90c0b9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767850681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.767850681
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.168196651
Short name T41
Test name
Test status
Simulation time 93109195 ps
CPU time 2.5 seconds
Started Jun 06 02:43:32 PM PDT 24
Finished Jun 06 02:43:36 PM PDT 24
Peak memory 232496 kb
Host smart-b5608450-fed4-4ba3-9cb6-46387eb01451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168196651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.168196651
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1706314804
Short name T421
Test name
Test status
Simulation time 11994021 ps
CPU time 0.7 seconds
Started Jun 06 02:43:38 PM PDT 24
Finished Jun 06 02:43:40 PM PDT 24
Peak memory 205176 kb
Host smart-cef7887d-f62b-435d-83d8-e77e335a1f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706314804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1706314804
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.562510082
Short name T633
Test name
Test status
Simulation time 1485359622 ps
CPU time 8.91 seconds
Started Jun 06 02:43:32 PM PDT 24
Finished Jun 06 02:43:42 PM PDT 24
Peak memory 224528 kb
Host smart-f7c80317-cb88-4ad0-88a1-089e10e41374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562510082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.562510082
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.586857383
Short name T522
Test name
Test status
Simulation time 46530999 ps
CPU time 0.73 seconds
Started Jun 06 02:43:35 PM PDT 24
Finished Jun 06 02:43:38 PM PDT 24
Peak memory 206464 kb
Host smart-1e69c318-5339-47d0-b44c-042fafd2ee33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586857383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.586857383
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2356671985
Short name T164
Test name
Test status
Simulation time 12550240973 ps
CPU time 65.51 seconds
Started Jun 06 02:43:33 PM PDT 24
Finished Jun 06 02:44:41 PM PDT 24
Peak memory 239056 kb
Host smart-1ba8c813-cab0-46ae-a79a-99293e8793ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356671985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2356671985
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2641795669
Short name T440
Test name
Test status
Simulation time 6167101224 ps
CPU time 64.95 seconds
Started Jun 06 02:43:36 PM PDT 24
Finished Jun 06 02:44:43 PM PDT 24
Peak memory 249328 kb
Host smart-e17eaeda-83f6-4fca-ac09-c482087c03d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641795669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2641795669
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.4039788681
Short name T201
Test name
Test status
Simulation time 163470008290 ps
CPU time 350.94 seconds
Started Jun 06 02:43:35 PM PDT 24
Finished Jun 06 02:49:28 PM PDT 24
Peak memory 249344 kb
Host smart-e58801e1-e183-4d58-8c65-77a966f11f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039788681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.4039788681
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2064412343
Short name T963
Test name
Test status
Simulation time 1950025211 ps
CPU time 9.52 seconds
Started Jun 06 02:43:35 PM PDT 24
Finished Jun 06 02:43:47 PM PDT 24
Peak memory 240300 kb
Host smart-e7a21a95-98dd-4662-9018-b9351a27d198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064412343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2064412343
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3801120106
Short name T849
Test name
Test status
Simulation time 967452206 ps
CPU time 9.63 seconds
Started Jun 06 02:43:34 PM PDT 24
Finished Jun 06 02:43:46 PM PDT 24
Peak memory 224468 kb
Host smart-127067b2-c250-4d71-9a5d-a502412c942d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801120106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3801120106
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2549206547
Short name T656
Test name
Test status
Simulation time 2895683446 ps
CPU time 23.03 seconds
Started Jun 06 02:43:37 PM PDT 24
Finished Jun 06 02:44:02 PM PDT 24
Peak memory 240784 kb
Host smart-2496112b-0a1e-47c1-bc90-29a9861d8052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549206547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2549206547
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2838609634
Short name T783
Test name
Test status
Simulation time 4997870641 ps
CPU time 14.1 seconds
Started Jun 06 02:43:33 PM PDT 24
Finished Jun 06 02:43:50 PM PDT 24
Peak memory 224568 kb
Host smart-0f283c7e-97db-454d-8cf2-606377f9c351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838609634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2838609634
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2342704480
Short name T941
Test name
Test status
Simulation time 354550452 ps
CPU time 7.43 seconds
Started Jun 06 02:43:35 PM PDT 24
Finished Jun 06 02:43:45 PM PDT 24
Peak memory 240364 kb
Host smart-805200a4-41f9-4509-9f64-da9513c2fb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342704480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2342704480
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3707228148
Short name T864
Test name
Test status
Simulation time 4615683700 ps
CPU time 10.9 seconds
Started Jun 06 02:43:37 PM PDT 24
Finished Jun 06 02:43:50 PM PDT 24
Peak memory 218804 kb
Host smart-05a6f4cd-1122-4716-a84e-18a2801010f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3707228148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3707228148
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.708091119
Short name T974
Test name
Test status
Simulation time 99106291864 ps
CPU time 187.91 seconds
Started Jun 06 02:43:34 PM PDT 24
Finished Jun 06 02:46:45 PM PDT 24
Peak memory 249084 kb
Host smart-c3df8d85-a172-4b5c-87fb-36fe3bc9947d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708091119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.708091119
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1745733692
Short name T556
Test name
Test status
Simulation time 13540259976 ps
CPU time 19.54 seconds
Started Jun 06 02:43:34 PM PDT 24
Finished Jun 06 02:43:57 PM PDT 24
Peak memory 216452 kb
Host smart-6ab8dc10-68d6-416c-bda0-c69b136da173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745733692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1745733692
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.486451450
Short name T434
Test name
Test status
Simulation time 2461080651 ps
CPU time 5.62 seconds
Started Jun 06 02:43:33 PM PDT 24
Finished Jun 06 02:43:40 PM PDT 24
Peak memory 216348 kb
Host smart-e69f958e-5d79-4df3-a325-44273afec283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486451450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.486451450
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2843759609
Short name T862
Test name
Test status
Simulation time 133430649 ps
CPU time 0.95 seconds
Started Jun 06 02:43:37 PM PDT 24
Finished Jun 06 02:43:40 PM PDT 24
Peak memory 207668 kb
Host smart-5409903e-11ed-433c-bd39-7929c83afd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843759609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2843759609
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3107464196
Short name T645
Test name
Test status
Simulation time 37887569 ps
CPU time 0.76 seconds
Started Jun 06 02:43:32 PM PDT 24
Finished Jun 06 02:43:34 PM PDT 24
Peak memory 205764 kb
Host smart-47f9bb53-ecc4-46cb-a79a-cabbd964deb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107464196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3107464196
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2838324428
Short name T693
Test name
Test status
Simulation time 1381156519 ps
CPU time 8.56 seconds
Started Jun 06 02:43:38 PM PDT 24
Finished Jun 06 02:43:49 PM PDT 24
Peak memory 232748 kb
Host smart-87b5b4d6-51ec-4e0f-b68c-c164aae5f96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838324428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2838324428
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3523833793
Short name T604
Test name
Test status
Simulation time 33541193 ps
CPU time 0.71 seconds
Started Jun 06 02:43:31 PM PDT 24
Finished Jun 06 02:43:33 PM PDT 24
Peak memory 205200 kb
Host smart-c8033224-7ffa-45da-ba1f-e4767ed82cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523833793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3523833793
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.295878490
Short name T924
Test name
Test status
Simulation time 74920486 ps
CPU time 2.73 seconds
Started Jun 06 02:43:32 PM PDT 24
Finished Jun 06 02:43:37 PM PDT 24
Peak memory 232732 kb
Host smart-11280a75-38c9-4625-9873-568ee604d0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295878490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.295878490
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1138275526
Short name T460
Test name
Test status
Simulation time 72024067 ps
CPU time 0.78 seconds
Started Jun 06 02:43:33 PM PDT 24
Finished Jun 06 02:43:36 PM PDT 24
Peak memory 205444 kb
Host smart-655e7824-a158-4acd-8989-40ccfc5b1fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138275526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1138275526
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1785543361
Short name T583
Test name
Test status
Simulation time 21938098359 ps
CPU time 158.4 seconds
Started Jun 06 02:43:30 PM PDT 24
Finished Jun 06 02:46:10 PM PDT 24
Peak memory 249184 kb
Host smart-d2aafff6-a4cc-4498-85cd-5beb1a437f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785543361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1785543361
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.4166087008
Short name T292
Test name
Test status
Simulation time 2226230845 ps
CPU time 34.39 seconds
Started Jun 06 02:43:33 PM PDT 24
Finished Jun 06 02:44:10 PM PDT 24
Peak memory 248608 kb
Host smart-e2425dee-d865-4b81-8239-8b3845fb66d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166087008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.4166087008
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4137631038
Short name T222
Test name
Test status
Simulation time 33986313778 ps
CPU time 267.58 seconds
Started Jun 06 02:43:32 PM PDT 24
Finished Jun 06 02:48:01 PM PDT 24
Peak memory 254888 kb
Host smart-8d170923-d88d-43bf-8541-ca2ec9818ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137631038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.4137631038
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.656938521
Short name T312
Test name
Test status
Simulation time 7075265863 ps
CPU time 12.72 seconds
Started Jun 06 02:43:33 PM PDT 24
Finished Jun 06 02:43:48 PM PDT 24
Peak memory 224572 kb
Host smart-43e9368b-8086-4e76-8438-741beb5de242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656938521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.656938521
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2986142297
Short name T691
Test name
Test status
Simulation time 2059311329 ps
CPU time 11.4 seconds
Started Jun 06 02:43:32 PM PDT 24
Finished Jun 06 02:43:46 PM PDT 24
Peak memory 232684 kb
Host smart-fd2c7214-fe45-45fa-a354-ca8533dcccf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986142297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2986142297
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.913845495
Short name T969
Test name
Test status
Simulation time 32763631306 ps
CPU time 15.9 seconds
Started Jun 06 02:43:34 PM PDT 24
Finished Jun 06 02:43:52 PM PDT 24
Peak memory 224304 kb
Host smart-e72514f0-b67b-470a-a48f-3d9c8f9100ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913845495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.913845495
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1064970008
Short name T870
Test name
Test status
Simulation time 10169686517 ps
CPU time 11.11 seconds
Started Jun 06 02:43:34 PM PDT 24
Finished Jun 06 02:43:47 PM PDT 24
Peak memory 232780 kb
Host smart-4d88a1ee-abd3-408a-9174-f9cafcaff54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064970008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1064970008
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3039190812
Short name T537
Test name
Test status
Simulation time 75044486 ps
CPU time 2.11 seconds
Started Jun 06 02:43:34 PM PDT 24
Finished Jun 06 02:43:39 PM PDT 24
Peak memory 223040 kb
Host smart-da20f6dc-365b-4e3c-9af8-761c05cb35ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039190812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3039190812
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1704573908
Short name T435
Test name
Test status
Simulation time 2771046336 ps
CPU time 9.65 seconds
Started Jun 06 02:43:31 PM PDT 24
Finished Jun 06 02:43:42 PM PDT 24
Peak memory 219376 kb
Host smart-0c2bf974-a1d8-4275-87e0-6b92acfb8641
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1704573908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1704573908
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1566898187
Short name T538
Test name
Test status
Simulation time 186354522 ps
CPU time 0.97 seconds
Started Jun 06 02:43:38 PM PDT 24
Finished Jun 06 02:43:41 PM PDT 24
Peak memory 205420 kb
Host smart-0e0b075c-9725-4fa8-b3ee-cf7b0213184b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566898187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1566898187
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.132857506
Short name T817
Test name
Test status
Simulation time 11897089947 ps
CPU time 64.14 seconds
Started Jun 06 02:43:34 PM PDT 24
Finished Jun 06 02:44:40 PM PDT 24
Peak memory 216396 kb
Host smart-940a6498-2ec6-4115-b459-5a4b11ef4c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132857506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.132857506
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2679662659
Short name T548
Test name
Test status
Simulation time 8208719083 ps
CPU time 11.8 seconds
Started Jun 06 02:43:33 PM PDT 24
Finished Jun 06 02:43:47 PM PDT 24
Peak memory 216348 kb
Host smart-a9f3ea65-3745-482c-bdae-8034c02af719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679662659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2679662659
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2206767086
Short name T778
Test name
Test status
Simulation time 11618460 ps
CPU time 0.67 seconds
Started Jun 06 02:43:32 PM PDT 24
Finished Jun 06 02:43:34 PM PDT 24
Peak memory 205400 kb
Host smart-22d3bb72-d76f-4f93-89d6-2779bfd75b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206767086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2206767086
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4185828316
Short name T543
Test name
Test status
Simulation time 322936485 ps
CPU time 0.96 seconds
Started Jun 06 02:43:33 PM PDT 24
Finished Jun 06 02:43:36 PM PDT 24
Peak memory 205788 kb
Host smart-31641d5a-2aba-4fe5-aea9-78ae542ef2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185828316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4185828316
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2737323460
Short name T819
Test name
Test status
Simulation time 461369251 ps
CPU time 4.85 seconds
Started Jun 06 02:43:31 PM PDT 24
Finished Jun 06 02:43:37 PM PDT 24
Peak memory 224560 kb
Host smart-49949890-d0b7-4c0a-abfe-308f9713f548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737323460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2737323460
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1627269977
Short name T575
Test name
Test status
Simulation time 23385331 ps
CPU time 0.71 seconds
Started Jun 06 02:43:43 PM PDT 24
Finished Jun 06 02:43:46 PM PDT 24
Peak memory 204532 kb
Host smart-7c23457f-86f2-4d13-a1f6-f5e02239a38c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627269977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1627269977
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2571086293
Short name T198
Test name
Test status
Simulation time 148483323 ps
CPU time 2.27 seconds
Started Jun 06 02:43:43 PM PDT 24
Finished Jun 06 02:43:48 PM PDT 24
Peak memory 224316 kb
Host smart-110fc17d-1778-4be1-a17c-af5dd58b1090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571086293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2571086293
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2630715671
Short name T937
Test name
Test status
Simulation time 19278825 ps
CPU time 0.78 seconds
Started Jun 06 02:43:33 PM PDT 24
Finished Jun 06 02:43:35 PM PDT 24
Peak memory 206796 kb
Host smart-4736105f-0f71-498f-8b86-44062d2f3821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630715671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2630715671
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.134349708
Short name T577
Test name
Test status
Simulation time 66979541677 ps
CPU time 142.22 seconds
Started Jun 06 02:43:43 PM PDT 24
Finished Jun 06 02:46:08 PM PDT 24
Peak memory 251140 kb
Host smart-927f3cf0-18b6-484b-b290-8291e152c760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134349708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.134349708
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.475213129
Short name T748
Test name
Test status
Simulation time 3532793982 ps
CPU time 43.06 seconds
Started Jun 06 02:43:45 PM PDT 24
Finished Jun 06 02:44:31 PM PDT 24
Peak memory 239620 kb
Host smart-69da4632-80ac-4bd8-b88a-14ec042a07c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475213129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.475213129
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2165105073
Short name T285
Test name
Test status
Simulation time 399735476 ps
CPU time 4.1 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:43:51 PM PDT 24
Peak memory 236424 kb
Host smart-19f354bd-de72-480c-8227-a8025cdedb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165105073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2165105073
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3345411093
Short name T816
Test name
Test status
Simulation time 486080529 ps
CPU time 4.43 seconds
Started Jun 06 02:43:37 PM PDT 24
Finished Jun 06 02:43:44 PM PDT 24
Peak memory 232696 kb
Host smart-5883571d-0163-41d2-b4f3-94714ae98145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345411093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3345411093
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.766083582
Short name T449
Test name
Test status
Simulation time 125854723 ps
CPU time 2.27 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:43:48 PM PDT 24
Peak memory 224500 kb
Host smart-d54d5791-f112-4a2a-b96c-2e34a16e6fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766083582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.766083582
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2427675216
Short name T306
Test name
Test status
Simulation time 633523046 ps
CPU time 4.34 seconds
Started Jun 06 02:43:35 PM PDT 24
Finished Jun 06 02:43:42 PM PDT 24
Peak memory 224544 kb
Host smart-33950c9a-350f-4da5-937f-4f967c3140d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427675216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2427675216
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1289562837
Short name T214
Test name
Test status
Simulation time 96837995 ps
CPU time 2.65 seconds
Started Jun 06 02:43:36 PM PDT 24
Finished Jun 06 02:43:41 PM PDT 24
Peak memory 224380 kb
Host smart-f9dd0f3c-196e-4173-b645-a2458555d39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289562837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1289562837
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1951748425
Short name T608
Test name
Test status
Simulation time 971947992 ps
CPU time 8.07 seconds
Started Jun 06 02:43:45 PM PDT 24
Finished Jun 06 02:43:57 PM PDT 24
Peak memory 223004 kb
Host smart-5a082e1a-6301-42ca-a64b-6d775e267d99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1951748425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1951748425
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3898180711
Short name T253
Test name
Test status
Simulation time 192665211557 ps
CPU time 468.85 seconds
Started Jun 06 02:43:43 PM PDT 24
Finished Jun 06 02:51:34 PM PDT 24
Peak memory 249348 kb
Host smart-33d3c16b-ef36-4dc4-9ae3-063a00d25a26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898180711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3898180711
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.970346764
Short name T939
Test name
Test status
Simulation time 4197570966 ps
CPU time 17.45 seconds
Started Jun 06 02:43:33 PM PDT 24
Finished Jun 06 02:43:53 PM PDT 24
Peak memory 216436 kb
Host smart-7efc4409-8c11-4f22-92a5-4c651caeda30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970346764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.970346764
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3912733086
Short name T367
Test name
Test status
Simulation time 2908264367 ps
CPU time 11.5 seconds
Started Jun 06 02:43:34 PM PDT 24
Finished Jun 06 02:43:48 PM PDT 24
Peak memory 216404 kb
Host smart-737591e1-35d9-4b3b-8ff1-b3f49c28312d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912733086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3912733086
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3439136809
Short name T647
Test name
Test status
Simulation time 44882219 ps
CPU time 1.27 seconds
Started Jun 06 02:43:36 PM PDT 24
Finished Jun 06 02:43:39 PM PDT 24
Peak memory 216388 kb
Host smart-39149ee0-55dc-4199-88ea-c36e6d56f048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439136809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3439136809
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.589089397
Short name T394
Test name
Test status
Simulation time 228358650 ps
CPU time 0.95 seconds
Started Jun 06 02:43:35 PM PDT 24
Finished Jun 06 02:43:39 PM PDT 24
Peak memory 205468 kb
Host smart-2f937863-9bf7-43d8-9f2a-8d3ba5ab60b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589089397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.589089397
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2798044796
Short name T793
Test name
Test status
Simulation time 10943239099 ps
CPU time 5.33 seconds
Started Jun 06 02:43:43 PM PDT 24
Finished Jun 06 02:43:51 PM PDT 24
Peak memory 232852 kb
Host smart-9674cf89-7296-439b-b518-88906f1c3e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798044796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2798044796
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.345045292
Short name T526
Test name
Test status
Simulation time 23454742 ps
CPU time 0.7 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:43:48 PM PDT 24
Peak memory 205172 kb
Host smart-3c921696-aff2-4f94-b2c6-eed484e59732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345045292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.345045292
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2023792131
Short name T947
Test name
Test status
Simulation time 63211281 ps
CPU time 2.21 seconds
Started Jun 06 02:43:42 PM PDT 24
Finished Jun 06 02:43:47 PM PDT 24
Peak memory 224508 kb
Host smart-11994779-3bb4-4d5a-9564-58a697714efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023792131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2023792131
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.978275725
Short name T644
Test name
Test status
Simulation time 20506037 ps
CPU time 0.78 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:43:47 PM PDT 24
Peak memory 206404 kb
Host smart-a99751b9-6fc7-4a47-8618-dc965ac1201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978275725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.978275725
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3880071983
Short name T170
Test name
Test status
Simulation time 8153836277 ps
CPU time 16.68 seconds
Started Jun 06 02:43:43 PM PDT 24
Finished Jun 06 02:44:02 PM PDT 24
Peak memory 224500 kb
Host smart-154b97a3-da92-438f-b73f-9488132f2f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880071983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3880071983
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3667952800
Short name T339
Test name
Test status
Simulation time 7936396113 ps
CPU time 46.27 seconds
Started Jun 06 02:43:45 PM PDT 24
Finished Jun 06 02:44:35 PM PDT 24
Peak memory 249780 kb
Host smart-f187f335-fc2d-4093-94f7-e17fe6679e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667952800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3667952800
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3734123705
Short name T316
Test name
Test status
Simulation time 119575478 ps
CPU time 6.57 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:43:54 PM PDT 24
Peak memory 249196 kb
Host smart-66217ed8-9aa9-44f0-a096-a5bf91a09b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734123705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3734123705
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2598864181
Short name T535
Test name
Test status
Simulation time 928620330 ps
CPU time 4.59 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:43:51 PM PDT 24
Peak memory 224456 kb
Host smart-f3d48d57-fe33-46e5-a0fe-d1e6f99aa734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598864181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2598864181
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2052028991
Short name T698
Test name
Test status
Simulation time 1982407497 ps
CPU time 26.84 seconds
Started Jun 06 02:43:42 PM PDT 24
Finished Jun 06 02:44:11 PM PDT 24
Peak memory 224468 kb
Host smart-b08d79cb-7052-41f1-8754-49ee454f2743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052028991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2052028991
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3224474029
Short name T121
Test name
Test status
Simulation time 7711332634 ps
CPU time 6.6 seconds
Started Jun 06 02:43:46 PM PDT 24
Finished Jun 06 02:43:56 PM PDT 24
Peak memory 224620 kb
Host smart-9a827289-d693-4174-bf24-d661150c1beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224474029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3224474029
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3043889000
Short name T417
Test name
Test status
Simulation time 32729434 ps
CPU time 2.46 seconds
Started Jun 06 02:43:48 PM PDT 24
Finished Jun 06 02:43:53 PM PDT 24
Peak memory 226408 kb
Host smart-d6cad113-0bd4-4bf7-b5bf-c5739f0ef592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043889000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3043889000
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3422680181
Short name T701
Test name
Test status
Simulation time 1407352264 ps
CPU time 14.05 seconds
Started Jun 06 02:43:46 PM PDT 24
Finished Jun 06 02:44:04 PM PDT 24
Peak memory 222180 kb
Host smart-13126be6-69af-46c4-8d7b-ab48147e830e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3422680181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3422680181
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2670223455
Short name T131
Test name
Test status
Simulation time 115719878008 ps
CPU time 289.86 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:48:37 PM PDT 24
Peak memory 249296 kb
Host smart-318ae95f-4579-492b-a453-942874989aad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670223455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2670223455
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.587372683
Short name T734
Test name
Test status
Simulation time 582949349 ps
CPU time 5.65 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:43:53 PM PDT 24
Peak memory 216360 kb
Host smart-14779e91-eeee-4af1-bcd9-ace87e773a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587372683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.587372683
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2834293771
Short name T868
Test name
Test status
Simulation time 7598055766 ps
CPU time 21.92 seconds
Started Jun 06 02:43:46 PM PDT 24
Finished Jun 06 02:44:11 PM PDT 24
Peak memory 216348 kb
Host smart-df31103b-9ecd-43cb-97c2-86bbce78c58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834293771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2834293771
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.824108411
Short name T424
Test name
Test status
Simulation time 296861168 ps
CPU time 3.44 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:43:50 PM PDT 24
Peak memory 216324 kb
Host smart-79997d99-ad0a-4dc6-9029-394d4d1df209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824108411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.824108411
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.820697773
Short name T714
Test name
Test status
Simulation time 100834249 ps
CPU time 0.86 seconds
Started Jun 06 02:43:45 PM PDT 24
Finished Jun 06 02:43:50 PM PDT 24
Peak memory 205772 kb
Host smart-9de39e44-0a72-45e7-9123-7bd383b5845a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820697773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.820697773
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2908295536
Short name T800
Test name
Test status
Simulation time 65052426 ps
CPU time 2.49 seconds
Started Jun 06 02:43:40 PM PDT 24
Finished Jun 06 02:43:44 PM PDT 24
Peak memory 224296 kb
Host smart-3b7ed3e5-2f4b-471e-8a5a-da2152746ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908295536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2908295536
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1123757601
Short name T456
Test name
Test status
Simulation time 38832168 ps
CPU time 0.68 seconds
Started Jun 06 02:43:46 PM PDT 24
Finished Jun 06 02:43:50 PM PDT 24
Peak memory 204520 kb
Host smart-1c167913-94b9-483a-8ede-093149a85f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123757601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1123757601
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1124790264
Short name T918
Test name
Test status
Simulation time 543450948 ps
CPU time 8.1 seconds
Started Jun 06 02:43:47 PM PDT 24
Finished Jun 06 02:43:59 PM PDT 24
Peak memory 232516 kb
Host smart-604439f5-8eb7-46d8-bd15-2380d2b03987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124790264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1124790264
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2172247135
Short name T832
Test name
Test status
Simulation time 32775157 ps
CPU time 0.72 seconds
Started Jun 06 02:43:41 PM PDT 24
Finished Jun 06 02:43:43 PM PDT 24
Peak memory 206812 kb
Host smart-58ace8ca-8d39-4773-b075-34a1a6f140bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172247135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2172247135
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3731741621
Short name T25
Test name
Test status
Simulation time 7147990090 ps
CPU time 35.41 seconds
Started Jun 06 02:43:43 PM PDT 24
Finished Jun 06 02:44:20 PM PDT 24
Peak memory 240988 kb
Host smart-3b224ed9-639d-423e-983b-0f8718fd503b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731741621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3731741621
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2904791647
Short name T219
Test name
Test status
Simulation time 348775347248 ps
CPU time 323.67 seconds
Started Jun 06 02:43:42 PM PDT 24
Finished Jun 06 02:49:07 PM PDT 24
Peak memory 256256 kb
Host smart-6327f13a-423e-4af8-840a-ee8ff57f6bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904791647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2904791647
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1992330895
Short name T598
Test name
Test status
Simulation time 207774035 ps
CPU time 7.37 seconds
Started Jun 06 02:43:43 PM PDT 24
Finished Jun 06 02:43:52 PM PDT 24
Peak memory 233572 kb
Host smart-eb0be768-0a61-473d-9834-6f134345087d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992330895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1992330895
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2491441316
Short name T212
Test name
Test status
Simulation time 122263278 ps
CPU time 4.7 seconds
Started Jun 06 02:43:43 PM PDT 24
Finished Jun 06 02:43:50 PM PDT 24
Peak memory 232720 kb
Host smart-c9110f5c-42dd-4cc8-a3d7-01ae5c6ae360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491441316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2491441316
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4254651532
Short name T505
Test name
Test status
Simulation time 1538537986 ps
CPU time 13.87 seconds
Started Jun 06 02:43:46 PM PDT 24
Finished Jun 06 02:44:03 PM PDT 24
Peak memory 239288 kb
Host smart-54be19c7-6260-4d1f-8b8b-7a74886b3a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254651532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4254651532
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1908985162
Short name T217
Test name
Test status
Simulation time 313300715 ps
CPU time 3.19 seconds
Started Jun 06 02:43:47 PM PDT 24
Finished Jun 06 02:43:54 PM PDT 24
Peak memory 224548 kb
Host smart-4abf9210-ee40-4d6b-9ea0-2946df4e8f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908985162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1908985162
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.697419598
Short name T127
Test name
Test status
Simulation time 5408766965 ps
CPU time 16.43 seconds
Started Jun 06 02:43:46 PM PDT 24
Finished Jun 06 02:44:06 PM PDT 24
Peak memory 224644 kb
Host smart-b239949f-47ca-4914-9191-17f133892c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697419598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.697419598
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1315924899
Short name T897
Test name
Test status
Simulation time 6435932869 ps
CPU time 16.65 seconds
Started Jun 06 02:43:45 PM PDT 24
Finished Jun 06 02:44:04 PM PDT 24
Peak memory 219740 kb
Host smart-5550682a-0a45-4f96-b989-99adf237cbbe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1315924899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1315924899
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.4225170326
Short name T156
Test name
Test status
Simulation time 18767802495 ps
CPU time 48.04 seconds
Started Jun 06 02:43:41 PM PDT 24
Finished Jun 06 02:44:31 PM PDT 24
Peak memory 249332 kb
Host smart-821756eb-3788-4225-843d-fadd6010650a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225170326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.4225170326
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.473583249
Short name T517
Test name
Test status
Simulation time 463654320 ps
CPU time 3.17 seconds
Started Jun 06 02:43:42 PM PDT 24
Finished Jun 06 02:43:46 PM PDT 24
Peak memory 216368 kb
Host smart-bf55d6b6-adff-412b-a7ed-f6e62fa9e62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473583249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.473583249
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3493321340
Short name T510
Test name
Test status
Simulation time 2585212283 ps
CPU time 6.51 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:43:54 PM PDT 24
Peak memory 216536 kb
Host smart-84449cc9-aefd-494c-9a5f-ae79da2da281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493321340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3493321340
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2647113897
Short name T683
Test name
Test status
Simulation time 733478465 ps
CPU time 3.95 seconds
Started Jun 06 02:43:45 PM PDT 24
Finished Jun 06 02:43:51 PM PDT 24
Peak memory 216360 kb
Host smart-e2431e51-93da-463b-96d7-3f51448fb4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647113897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2647113897
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3399063619
Short name T358
Test name
Test status
Simulation time 80225849 ps
CPU time 0.8 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:43:48 PM PDT 24
Peak memory 205792 kb
Host smart-bf96fc0d-20dc-4be7-9d04-ea044e203b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399063619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3399063619
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1486888093
Short name T949
Test name
Test status
Simulation time 266810393 ps
CPU time 4.38 seconds
Started Jun 06 02:43:42 PM PDT 24
Finished Jun 06 02:43:49 PM PDT 24
Peak memory 232796 kb
Host smart-422b09ba-1ed4-4aba-bbc6-855bd0a9135f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486888093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1486888093
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2244758028
Short name T495
Test name
Test status
Simulation time 23928192 ps
CPU time 0.71 seconds
Started Jun 06 02:43:52 PM PDT 24
Finished Jun 06 02:43:56 PM PDT 24
Peak memory 205208 kb
Host smart-dcee0ae8-d20f-4031-b900-fe80fb44e6ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244758028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2244758028
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2640814752
Short name T82
Test name
Test status
Simulation time 1182103074 ps
CPU time 7.46 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:43:55 PM PDT 24
Peak memory 224536 kb
Host smart-8bd99f31-e35d-4fc4-90d3-2b9405a49610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640814752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2640814752
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3607736421
Short name T547
Test name
Test status
Simulation time 35640807 ps
CPU time 0.8 seconds
Started Jun 06 02:43:46 PM PDT 24
Finished Jun 06 02:43:50 PM PDT 24
Peak memory 206680 kb
Host smart-2427fcd1-70c7-4a1d-83ba-63fab0e7515e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607736421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3607736421
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1453558348
Short name T263
Test name
Test status
Simulation time 14809596804 ps
CPU time 32.32 seconds
Started Jun 06 02:43:53 PM PDT 24
Finished Jun 06 02:44:29 PM PDT 24
Peak memory 240224 kb
Host smart-ac675da0-e4cd-49e3-8161-ead0e1cb039f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453558348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1453558348
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3068079729
Short name T228
Test name
Test status
Simulation time 4365845768 ps
CPU time 117.64 seconds
Started Jun 06 02:43:51 PM PDT 24
Finished Jun 06 02:45:53 PM PDT 24
Peak memory 265552 kb
Host smart-6b5710b8-c95b-44e1-bb40-6a64ad347869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068079729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3068079729
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1089703175
Short name T283
Test name
Test status
Simulation time 13299479028 ps
CPU time 138.49 seconds
Started Jun 06 02:43:50 PM PDT 24
Finished Jun 06 02:46:11 PM PDT 24
Peak memory 249316 kb
Host smart-bced41b9-b840-4c6a-a02a-9593795dc551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089703175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1089703175
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1572525601
Short name T317
Test name
Test status
Simulation time 1829087408 ps
CPU time 13.36 seconds
Started Jun 06 02:43:47 PM PDT 24
Finished Jun 06 02:44:04 PM PDT 24
Peak memory 224308 kb
Host smart-384d05d7-6a7b-4466-89dc-8c96fc30a5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572525601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1572525601
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.735808688
Short name T275
Test name
Test status
Simulation time 371879350 ps
CPU time 4.25 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:43:50 PM PDT 24
Peak memory 232728 kb
Host smart-b522a485-9925-4e9c-b159-b2994804a54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735808688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.735808688
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1043774079
Short name T880
Test name
Test status
Simulation time 17805650699 ps
CPU time 46.05 seconds
Started Jun 06 02:43:46 PM PDT 24
Finished Jun 06 02:44:36 PM PDT 24
Peak memory 232792 kb
Host smart-1acc20c8-15cc-464b-a532-a0b5a44cbc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043774079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1043774079
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.653136550
Short name T904
Test name
Test status
Simulation time 378019798 ps
CPU time 6.26 seconds
Started Jun 06 02:43:43 PM PDT 24
Finished Jun 06 02:43:51 PM PDT 24
Peak memory 232824 kb
Host smart-b8215084-ade7-4217-a4df-a8faa5012065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653136550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.653136550
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1714201730
Short name T975
Test name
Test status
Simulation time 32844847 ps
CPU time 2.38 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:43:49 PM PDT 24
Peak memory 232464 kb
Host smart-5d8a4931-3fdf-4d7e-84e6-795ce710061b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714201730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1714201730
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3691444981
Short name T140
Test name
Test status
Simulation time 93340554 ps
CPU time 3.7 seconds
Started Jun 06 02:43:46 PM PDT 24
Finished Jun 06 02:43:53 PM PDT 24
Peak memory 218776 kb
Host smart-ef786de5-aa3c-4792-bab7-5b99a71efea9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3691444981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3691444981
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2117554772
Short name T900
Test name
Test status
Simulation time 2022556469 ps
CPU time 26.39 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:44:13 PM PDT 24
Peak memory 216372 kb
Host smart-46efc488-5517-45fa-a0b1-2bf32d076f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117554772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2117554772
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3662647115
Short name T758
Test name
Test status
Simulation time 10466165407 ps
CPU time 28.64 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:44:15 PM PDT 24
Peak memory 216312 kb
Host smart-e2223e87-9b89-40c7-8827-b578abcdfd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662647115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3662647115
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.602560345
Short name T730
Test name
Test status
Simulation time 308410043 ps
CPU time 2.2 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:43:49 PM PDT 24
Peak memory 216356 kb
Host smart-3fc3c88b-35e8-4e3f-8a65-288949b4c824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602560345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.602560345
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.623418850
Short name T426
Test name
Test status
Simulation time 83057283 ps
CPU time 0.94 seconds
Started Jun 06 02:43:44 PM PDT 24
Finished Jun 06 02:43:48 PM PDT 24
Peak memory 205764 kb
Host smart-de59f32f-4ad5-442b-a26c-4c3cd4aabe24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623418850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.623418850
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.4294292551
Short name T534
Test name
Test status
Simulation time 34465906737 ps
CPU time 29.06 seconds
Started Jun 06 02:43:46 PM PDT 24
Finished Jun 06 02:44:18 PM PDT 24
Peak memory 232792 kb
Host smart-5235891b-f84c-4c6a-8e02-dfbc5e790a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294292551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.4294292551
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3896859787
Short name T846
Test name
Test status
Simulation time 70734021 ps
CPU time 0.73 seconds
Started Jun 06 02:42:13 PM PDT 24
Finished Jun 06 02:42:15 PM PDT 24
Peak memory 204568 kb
Host smart-802b664e-88d8-4809-affe-e42f67a6d5ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896859787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
896859787
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.438555441
Short name T964
Test name
Test status
Simulation time 230920889 ps
CPU time 2.29 seconds
Started Jun 06 02:42:11 PM PDT 24
Finished Jun 06 02:42:15 PM PDT 24
Peak memory 224468 kb
Host smart-b4048616-5b42-4e68-a413-758cf7124a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438555441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.438555441
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3539760544
Short name T406
Test name
Test status
Simulation time 34676577 ps
CPU time 0.73 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:42:01 PM PDT 24
Peak memory 206468 kb
Host smart-3c57380a-cfe1-433e-80d3-ae2d3b6eb952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539760544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3539760544
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.505914088
Short name T516
Test name
Test status
Simulation time 79281220583 ps
CPU time 219.29 seconds
Started Jun 06 02:42:03 PM PDT 24
Finished Jun 06 02:45:44 PM PDT 24
Peak memory 251716 kb
Host smart-f40e8c0a-022b-46cf-a96f-74077833e821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505914088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.505914088
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3043784160
Short name T269
Test name
Test status
Simulation time 171157028966 ps
CPU time 398.03 seconds
Started Jun 06 02:42:06 PM PDT 24
Finished Jun 06 02:48:46 PM PDT 24
Peak memory 255640 kb
Host smart-c557379e-2a10-4456-be0e-a6f3cdff3aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043784160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3043784160
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3055965019
Short name T745
Test name
Test status
Simulation time 229083691558 ps
CPU time 374.99 seconds
Started Jun 06 02:42:03 PM PDT 24
Finished Jun 06 02:48:20 PM PDT 24
Peak memory 256472 kb
Host smart-0a2553aa-9007-4c14-977a-2f4338b37166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055965019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3055965019
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2134306957
Short name T430
Test name
Test status
Simulation time 1326766000 ps
CPU time 5.65 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:42:15 PM PDT 24
Peak memory 224460 kb
Host smart-c5ee6729-fae5-4b78-b550-356283208d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134306957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2134306957
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.46462081
Short name T663
Test name
Test status
Simulation time 334804945 ps
CPU time 6.66 seconds
Started Jun 06 02:41:55 PM PDT 24
Finished Jun 06 02:42:06 PM PDT 24
Peak memory 232784 kb
Host smart-b9d06792-3112-4042-9bde-225ab5bac450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46462081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.46462081
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.72159194
Short name T195
Test name
Test status
Simulation time 461953577 ps
CPU time 10.82 seconds
Started Jun 06 02:42:04 PM PDT 24
Finished Jun 06 02:42:17 PM PDT 24
Peak memory 249136 kb
Host smart-16f96cd0-231b-4a75-bcd3-7e0d00f9f801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72159194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.72159194
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2041989314
Short name T552
Test name
Test status
Simulation time 236132906 ps
CPU time 1.1 seconds
Started Jun 06 02:41:56 PM PDT 24
Finished Jun 06 02:42:01 PM PDT 24
Peak memory 217756 kb
Host smart-579699fc-ae4d-4672-bb51-6b532201e286
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041989314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2041989314
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3826393994
Short name T529
Test name
Test status
Simulation time 635925515 ps
CPU time 5.1 seconds
Started Jun 06 02:41:58 PM PDT 24
Finished Jun 06 02:42:06 PM PDT 24
Peak memory 224488 kb
Host smart-2f825536-3d77-4079-922e-a49340ed40e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826393994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3826393994
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2459931548
Short name T872
Test name
Test status
Simulation time 10923042247 ps
CPU time 9.57 seconds
Started Jun 06 02:42:06 PM PDT 24
Finished Jun 06 02:42:17 PM PDT 24
Peak memory 233000 kb
Host smart-311ee39f-a211-4aed-95ee-01b4d44db0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459931548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2459931548
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3524202906
Short name T466
Test name
Test status
Simulation time 1189281904 ps
CPU time 14.03 seconds
Started Jun 06 02:42:04 PM PDT 24
Finished Jun 06 02:42:20 PM PDT 24
Peak memory 222116 kb
Host smart-0bc22c58-d1ca-4d0d-a38c-02212fb70099
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3524202906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3524202906
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.83714258
Short name T932
Test name
Test status
Simulation time 3082534762 ps
CPU time 24.72 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:42:33 PM PDT 24
Peak memory 241188 kb
Host smart-e3508dd8-ef5a-47ca-83ee-60fbb255184f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83714258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_
all.83714258
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.252517971
Short name T878
Test name
Test status
Simulation time 10330975852 ps
CPU time 28.98 seconds
Started Jun 06 02:42:04 PM PDT 24
Finished Jun 06 02:42:35 PM PDT 24
Peak memory 216152 kb
Host smart-8be0ce13-7140-4a9c-8c2e-520fbec98940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252517971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.252517971
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1419599023
Short name T492
Test name
Test status
Simulation time 11262506227 ps
CPU time 8 seconds
Started Jun 06 02:41:55 PM PDT 24
Finished Jun 06 02:42:07 PM PDT 24
Peak memory 216296 kb
Host smart-b999f7ab-45e8-4c32-b0ce-d1187621a541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419599023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1419599023
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3156694006
Short name T334
Test name
Test status
Simulation time 82056700 ps
CPU time 0.75 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:42:01 PM PDT 24
Peak memory 205856 kb
Host smart-88a4e999-d889-40f5-add9-72fa599a557e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156694006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3156694006
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1384988188
Short name T574
Test name
Test status
Simulation time 28746435 ps
CPU time 0.73 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:42:10 PM PDT 24
Peak memory 205968 kb
Host smart-a09e246a-02be-46ba-8ecc-dde18ad1c2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384988188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1384988188
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3819955948
Short name T6
Test name
Test status
Simulation time 1934323903 ps
CPU time 5.99 seconds
Started Jun 06 02:41:59 PM PDT 24
Finished Jun 06 02:42:08 PM PDT 24
Peak memory 224472 kb
Host smart-4f9de156-c01d-4028-9e76-523c54fce79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819955948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3819955948
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4212089539
Short name T971
Test name
Test status
Simulation time 11814525 ps
CPU time 0.73 seconds
Started Jun 06 02:43:53 PM PDT 24
Finished Jun 06 02:43:57 PM PDT 24
Peak memory 205180 kb
Host smart-73de78ff-9ead-4a38-a4ee-48df881dc251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212089539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4212089539
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.4149308515
Short name T774
Test name
Test status
Simulation time 87378558 ps
CPU time 2.49 seconds
Started Jun 06 02:43:53 PM PDT 24
Finished Jun 06 02:43:59 PM PDT 24
Peak memory 232664 kb
Host smart-3f9a0c10-19df-44f0-aec9-45d4e4bc5532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149308515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.4149308515
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3776129012
Short name T50
Test name
Test status
Simulation time 63550239 ps
CPU time 0.77 seconds
Started Jun 06 02:43:57 PM PDT 24
Finished Jun 06 02:43:59 PM PDT 24
Peak memory 206712 kb
Host smart-66dd647b-727a-4678-8469-867fc006d616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776129012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3776129012
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3196036380
Short name T601
Test name
Test status
Simulation time 183434299740 ps
CPU time 311.04 seconds
Started Jun 06 02:43:56 PM PDT 24
Finished Jun 06 02:49:09 PM PDT 24
Peak memory 257372 kb
Host smart-947df75d-65ef-4896-8b14-29da144393ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196036380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3196036380
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.227286151
Short name T234
Test name
Test status
Simulation time 9151214864 ps
CPU time 43.46 seconds
Started Jun 06 02:43:53 PM PDT 24
Finished Jun 06 02:44:40 PM PDT 24
Peak memory 255696 kb
Host smart-bb113322-4ade-455f-8486-c438abe68cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227286151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.227286151
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1932349965
Short name T966
Test name
Test status
Simulation time 53502163457 ps
CPU time 121.1 seconds
Started Jun 06 02:43:53 PM PDT 24
Finished Jun 06 02:45:57 PM PDT 24
Peak memory 249776 kb
Host smart-8745f2b4-fa2c-4392-8435-39ed2ee0bc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932349965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1932349965
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2342416508
Short name T376
Test name
Test status
Simulation time 1358933518 ps
CPU time 12.85 seconds
Started Jun 06 02:43:57 PM PDT 24
Finished Jun 06 02:44:11 PM PDT 24
Peak memory 236220 kb
Host smart-106f2e88-6ff5-4e22-bfbd-ff67a9e86184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342416508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2342416508
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2351582711
Short name T746
Test name
Test status
Simulation time 3101483863 ps
CPU time 5.26 seconds
Started Jun 06 02:43:51 PM PDT 24
Finished Jun 06 02:44:00 PM PDT 24
Peak memory 224540 kb
Host smart-9b1f2363-15ee-4d4f-92aa-b12ff68b14f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351582711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2351582711
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.732253163
Short name T811
Test name
Test status
Simulation time 21309057570 ps
CPU time 48.09 seconds
Started Jun 06 02:43:50 PM PDT 24
Finished Jun 06 02:44:40 PM PDT 24
Peak memory 232828 kb
Host smart-6817376a-e33a-4c5c-990c-a0aa4be1affa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732253163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.732253163
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3306967192
Short name T168
Test name
Test status
Simulation time 3957329891 ps
CPU time 13.24 seconds
Started Jun 06 02:43:52 PM PDT 24
Finished Jun 06 02:44:08 PM PDT 24
Peak memory 224504 kb
Host smart-2bcc504d-51bb-4899-b881-16ecdaa5245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306967192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3306967192
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4230045278
Short name T751
Test name
Test status
Simulation time 3700774788 ps
CPU time 11.17 seconds
Started Jun 06 02:43:50 PM PDT 24
Finished Jun 06 02:44:04 PM PDT 24
Peak memory 248824 kb
Host smart-39c0b432-aa00-4222-990a-fbe759a0f396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230045278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4230045278
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1722360795
Short name T951
Test name
Test status
Simulation time 1278428313 ps
CPU time 5.86 seconds
Started Jun 06 02:43:51 PM PDT 24
Finished Jun 06 02:44:00 PM PDT 24
Peak memory 222948 kb
Host smart-ce4cd249-92d8-4967-a099-40b8ba782bfb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1722360795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1722360795
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.4204823056
Short name T485
Test name
Test status
Simulation time 5124853516 ps
CPU time 69.34 seconds
Started Jun 06 02:43:53 PM PDT 24
Finished Jun 06 02:45:06 PM PDT 24
Peak memory 265320 kb
Host smart-ccca9e98-3753-4b28-ac2c-189c2b7f4c7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204823056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.4204823056
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2167402716
Short name T335
Test name
Test status
Simulation time 804111938 ps
CPU time 9.49 seconds
Started Jun 06 02:43:51 PM PDT 24
Finished Jun 06 02:44:04 PM PDT 24
Peak memory 216348 kb
Host smart-aeba7058-d0eb-4858-aeb5-5e6eaf42c483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167402716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2167402716
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2380064527
Short name T124
Test name
Test status
Simulation time 1681710327 ps
CPU time 7.05 seconds
Started Jun 06 02:43:53 PM PDT 24
Finished Jun 06 02:44:03 PM PDT 24
Peak memory 216152 kb
Host smart-f79699df-b5f1-4331-afd2-6447f683a808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380064527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2380064527
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.703863707
Short name T581
Test name
Test status
Simulation time 74978360 ps
CPU time 1.02 seconds
Started Jun 06 02:43:52 PM PDT 24
Finished Jun 06 02:43:57 PM PDT 24
Peak memory 207188 kb
Host smart-b5883029-585c-4b17-b30e-297feffa723b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703863707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.703863707
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1620622413
Short name T616
Test name
Test status
Simulation time 98747895 ps
CPU time 0.73 seconds
Started Jun 06 02:43:51 PM PDT 24
Finished Jun 06 02:43:55 PM PDT 24
Peak memory 205804 kb
Host smart-9b8c362b-6f0b-4b03-899e-8ea9712b5606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620622413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1620622413
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3144810132
Short name T769
Test name
Test status
Simulation time 29141326438 ps
CPU time 25.81 seconds
Started Jun 06 02:43:50 PM PDT 24
Finished Jun 06 02:44:18 PM PDT 24
Peak memory 232824 kb
Host smart-161be6ec-7cce-4277-9f93-509a4ec6e50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144810132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3144810132
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.493197851
Short name T902
Test name
Test status
Simulation time 14372611 ps
CPU time 0.74 seconds
Started Jun 06 02:44:01 PM PDT 24
Finished Jun 06 02:44:03 PM PDT 24
Peak memory 204520 kb
Host smart-f39e6afe-c979-49db-9916-e18d18d50c42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493197851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.493197851
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.704315622
Short name T572
Test name
Test status
Simulation time 248958999 ps
CPU time 4.06 seconds
Started Jun 06 02:43:52 PM PDT 24
Finished Jun 06 02:44:00 PM PDT 24
Peak memory 224532 kb
Host smart-c8e504e9-2675-4015-847a-9d83b80b8981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704315622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.704315622
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1240257139
Short name T493
Test name
Test status
Simulation time 17365098 ps
CPU time 0.78 seconds
Started Jun 06 02:43:51 PM PDT 24
Finished Jun 06 02:43:55 PM PDT 24
Peak memory 206808 kb
Host smart-27403d36-0cce-400d-8546-e669480bb059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240257139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1240257139
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1715759483
Short name T576
Test name
Test status
Simulation time 8606775412 ps
CPU time 70.17 seconds
Started Jun 06 02:43:51 PM PDT 24
Finished Jun 06 02:45:05 PM PDT 24
Peak memory 257388 kb
Host smart-6f5815e1-261e-425f-8c37-d2069c8c3cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715759483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1715759483
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1588318880
Short name T658
Test name
Test status
Simulation time 30503555222 ps
CPU time 278.47 seconds
Started Jun 06 02:43:52 PM PDT 24
Finished Jun 06 02:48:34 PM PDT 24
Peak memory 253128 kb
Host smart-57cb6d6b-b5ab-4f12-b258-ec12069df732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588318880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1588318880
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1031033783
Short name T938
Test name
Test status
Simulation time 2880417126 ps
CPU time 32.49 seconds
Started Jun 06 02:43:51 PM PDT 24
Finished Jun 06 02:44:27 PM PDT 24
Peak memory 248656 kb
Host smart-cf265e4a-3094-4a98-b50e-27ec20665ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031033783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1031033783
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3828909406
Short name T418
Test name
Test status
Simulation time 943400617 ps
CPU time 13.77 seconds
Started Jun 06 02:43:51 PM PDT 24
Finished Jun 06 02:44:07 PM PDT 24
Peak memory 224440 kb
Host smart-38577000-fb26-4ed4-835d-6b5b5c025223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828909406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3828909406
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2671714354
Short name T626
Test name
Test status
Simulation time 380581944 ps
CPU time 6.11 seconds
Started Jun 06 02:43:52 PM PDT 24
Finished Jun 06 02:44:01 PM PDT 24
Peak memory 232664 kb
Host smart-7af9cf37-358d-4a3d-811d-cd22418362bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671714354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2671714354
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1373421522
Short name T63
Test name
Test status
Simulation time 3028432869 ps
CPU time 20.3 seconds
Started Jun 06 02:43:53 PM PDT 24
Finished Jun 06 02:44:17 PM PDT 24
Peak memory 240864 kb
Host smart-78e91308-6477-41b8-937d-d9973d1685eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373421522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1373421522
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2767430021
Short name T192
Test name
Test status
Simulation time 1135062043 ps
CPU time 5.13 seconds
Started Jun 06 02:43:52 PM PDT 24
Finished Jun 06 02:44:00 PM PDT 24
Peak memory 232684 kb
Host smart-5a764845-1871-4f50-9ceb-a2314f5f9a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767430021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2767430021
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2029475572
Short name T901
Test name
Test status
Simulation time 33626988 ps
CPU time 2.48 seconds
Started Jun 06 02:43:52 PM PDT 24
Finished Jun 06 02:43:58 PM PDT 24
Peak memory 232720 kb
Host smart-08872903-2968-40b4-9e16-aa880bcaaaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029475572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2029475572
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2349437256
Short name T721
Test name
Test status
Simulation time 1523176169 ps
CPU time 5.93 seconds
Started Jun 06 02:43:52 PM PDT 24
Finished Jun 06 02:44:02 PM PDT 24
Peak memory 222388 kb
Host smart-0db9dd11-63c0-4d04-85c0-ea3db3c80470
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2349437256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2349437256
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1306273375
Short name T332
Test name
Test status
Simulation time 4524613502 ps
CPU time 33.26 seconds
Started Jun 06 02:43:52 PM PDT 24
Finished Jun 06 02:44:28 PM PDT 24
Peak memory 224732 kb
Host smart-31ef974a-ad41-4217-a5d0-eb72e5398113
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306273375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1306273375
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.122130463
Short name T619
Test name
Test status
Simulation time 13139345881 ps
CPU time 19.47 seconds
Started Jun 06 02:43:52 PM PDT 24
Finished Jun 06 02:44:15 PM PDT 24
Peak memory 216680 kb
Host smart-b5a4b8c8-2c57-4b3a-b687-7b7e769ac2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122130463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.122130463
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2288580252
Short name T593
Test name
Test status
Simulation time 10195224 ps
CPU time 0.71 seconds
Started Jun 06 02:43:52 PM PDT 24
Finished Jun 06 02:43:56 PM PDT 24
Peak memory 205520 kb
Host smart-1941935a-9505-4860-92d1-567fb3dffe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288580252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2288580252
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2606752498
Short name T953
Test name
Test status
Simulation time 451712036 ps
CPU time 1.85 seconds
Started Jun 06 02:43:54 PM PDT 24
Finished Jun 06 02:43:59 PM PDT 24
Peak memory 216376 kb
Host smart-ec3c7d55-249e-4293-83ac-9153e6fe5c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606752498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2606752498
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2718024861
Short name T617
Test name
Test status
Simulation time 24471371 ps
CPU time 0.7 seconds
Started Jun 06 02:43:55 PM PDT 24
Finished Jun 06 02:43:58 PM PDT 24
Peak memory 205780 kb
Host smart-3fc5ba5b-b780-47d5-9aa8-64599b2d1d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718024861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2718024861
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1686429517
Short name T654
Test name
Test status
Simulation time 12444415215 ps
CPU time 21.48 seconds
Started Jun 06 02:43:51 PM PDT 24
Finished Jun 06 02:44:15 PM PDT 24
Peak memory 224636 kb
Host smart-d7da7b25-9e72-4fb4-a4f0-e3b3f06d3457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686429517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1686429517
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3581898845
Short name T345
Test name
Test status
Simulation time 19518997 ps
CPU time 0.7 seconds
Started Jun 06 02:44:01 PM PDT 24
Finished Jun 06 02:44:03 PM PDT 24
Peak memory 205180 kb
Host smart-b0a31d99-15a2-4211-82b2-bfd9d7b71e3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581898845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3581898845
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2933688604
Short name T566
Test name
Test status
Simulation time 389293064 ps
CPU time 6.26 seconds
Started Jun 06 02:44:01 PM PDT 24
Finished Jun 06 02:44:09 PM PDT 24
Peak memory 232744 kb
Host smart-2494a16d-775d-4be7-8eb1-1f28e7df04b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933688604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2933688604
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2478832644
Short name T545
Test name
Test status
Simulation time 29617596 ps
CPU time 0.73 seconds
Started Jun 06 02:43:54 PM PDT 24
Finished Jun 06 02:43:58 PM PDT 24
Peak memory 205788 kb
Host smart-a7ee553e-8703-40f7-8238-ed7a92a1f812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478832644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2478832644
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.172185933
Short name T479
Test name
Test status
Simulation time 20737665342 ps
CPU time 152.47 seconds
Started Jun 06 02:44:00 PM PDT 24
Finished Jun 06 02:46:34 PM PDT 24
Peak memory 252268 kb
Host smart-e0994d3f-054b-4ab7-9985-4348b0d83fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172185933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.172185933
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3459137029
Short name T649
Test name
Test status
Simulation time 26488486909 ps
CPU time 67.56 seconds
Started Jun 06 02:44:02 PM PDT 24
Finished Jun 06 02:45:12 PM PDT 24
Peak memory 249212 kb
Host smart-f74efefc-9e65-4ee2-92dc-4f6b1d872501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459137029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3459137029
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1417739111
Short name T643
Test name
Test status
Simulation time 6413176846 ps
CPU time 107.12 seconds
Started Jun 06 02:44:00 PM PDT 24
Finished Jun 06 02:45:49 PM PDT 24
Peak memory 250356 kb
Host smart-8abd5ab2-f3e5-460e-9f4c-1f6b8da10b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417739111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1417739111
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2021991169
Short name T315
Test name
Test status
Simulation time 3094495534 ps
CPU time 48.17 seconds
Started Jun 06 02:44:02 PM PDT 24
Finished Jun 06 02:44:52 PM PDT 24
Peak memory 241020 kb
Host smart-97c7d2e5-cb66-4f31-8e0f-d19866ab3f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021991169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2021991169
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3337784226
Short name T276
Test name
Test status
Simulation time 346318391 ps
CPU time 4.86 seconds
Started Jun 06 02:44:01 PM PDT 24
Finished Jun 06 02:44:08 PM PDT 24
Peak memory 232712 kb
Host smart-ff55da42-843f-4b5b-a566-2d1af2d0e907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337784226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3337784226
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3752529284
Short name T497
Test name
Test status
Simulation time 23638231237 ps
CPU time 105.42 seconds
Started Jun 06 02:43:59 PM PDT 24
Finished Jun 06 02:45:46 PM PDT 24
Peak memory 224604 kb
Host smart-3b25ef25-919e-4a28-897c-54658fa4457a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752529284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3752529284
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2264779550
Short name T711
Test name
Test status
Simulation time 6326345965 ps
CPU time 8.78 seconds
Started Jun 06 02:44:04 PM PDT 24
Finished Jun 06 02:44:15 PM PDT 24
Peak memory 232788 kb
Host smart-d789ad5d-f726-433d-bbca-875ec54f56be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264779550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2264779550
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.432898492
Short name T915
Test name
Test status
Simulation time 1099432245 ps
CPU time 7.84 seconds
Started Jun 06 02:44:00 PM PDT 24
Finished Jun 06 02:44:10 PM PDT 24
Peak memory 226912 kb
Host smart-be3bf70f-d781-4e5c-9e01-1221c2a37bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432898492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.432898492
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.682398390
Short name T451
Test name
Test status
Simulation time 174517786 ps
CPU time 4.86 seconds
Started Jun 06 02:44:01 PM PDT 24
Finished Jun 06 02:44:07 PM PDT 24
Peak memory 219292 kb
Host smart-7abf6e78-4996-4573-8d41-c91fdb18850f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=682398390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.682398390
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.4268693746
Short name T152
Test name
Test status
Simulation time 37436432717 ps
CPU time 435.3 seconds
Started Jun 06 02:44:02 PM PDT 24
Finished Jun 06 02:51:19 PM PDT 24
Peak memory 252928 kb
Host smart-b8f3bb48-7144-491a-972d-afd9020a00c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268693746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.4268693746
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3021827836
Short name T877
Test name
Test status
Simulation time 41246052642 ps
CPU time 52.67 seconds
Started Jun 06 02:43:50 PM PDT 24
Finished Jun 06 02:44:45 PM PDT 24
Peak memory 216456 kb
Host smart-ec4a36e9-e532-43fa-bb24-1b479844e34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021827836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3021827836
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3693001313
Short name T700
Test name
Test status
Simulation time 1316100639 ps
CPU time 4.47 seconds
Started Jun 06 02:43:53 PM PDT 24
Finished Jun 06 02:44:01 PM PDT 24
Peak memory 216248 kb
Host smart-176a2049-e5f1-4417-b7dc-a486f8875d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693001313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3693001313
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3041716522
Short name T371
Test name
Test status
Simulation time 106238286 ps
CPU time 0.97 seconds
Started Jun 06 02:43:51 PM PDT 24
Finished Jun 06 02:43:54 PM PDT 24
Peak memory 206872 kb
Host smart-327190d4-d564-478a-94dd-e845c046daa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041716522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3041716522
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3248720688
Short name T808
Test name
Test status
Simulation time 159444132 ps
CPU time 0.93 seconds
Started Jun 06 02:43:56 PM PDT 24
Finished Jun 06 02:43:59 PM PDT 24
Peak memory 205776 kb
Host smart-3c957c35-b4d2-41b8-bff6-a6310e56ba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248720688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3248720688
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1221238868
Short name T211
Test name
Test status
Simulation time 608412898 ps
CPU time 2.37 seconds
Started Jun 06 02:44:00 PM PDT 24
Finished Jun 06 02:44:05 PM PDT 24
Peak memory 224572 kb
Host smart-459750fd-b807-4d3d-b22f-8a859cf8eb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221238868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1221238868
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3437765892
Short name T502
Test name
Test status
Simulation time 15243255 ps
CPU time 0.79 seconds
Started Jun 06 02:44:04 PM PDT 24
Finished Jun 06 02:44:06 PM PDT 24
Peak memory 205764 kb
Host smart-11eb907b-e455-45dd-a8cc-45e19dc7e65d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437765892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3437765892
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4125457361
Short name T891
Test name
Test status
Simulation time 2226394593 ps
CPU time 22.12 seconds
Started Jun 06 02:44:03 PM PDT 24
Finished Jun 06 02:44:27 PM PDT 24
Peak memory 224556 kb
Host smart-a0c755e1-b264-4e45-aaa0-c45f2c522e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125457361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4125457361
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3389697496
Short name T347
Test name
Test status
Simulation time 39913772 ps
CPU time 0.81 seconds
Started Jun 06 02:44:02 PM PDT 24
Finished Jun 06 02:44:05 PM PDT 24
Peak memory 205792 kb
Host smart-46c1684e-894d-48e0-90e3-9e0c71ee1567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389697496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3389697496
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3645900227
Short name T869
Test name
Test status
Simulation time 32668544462 ps
CPU time 60.36 seconds
Started Jun 06 02:44:03 PM PDT 24
Finished Jun 06 02:45:05 PM PDT 24
Peak memory 248428 kb
Host smart-02f6ce54-51a4-4078-8f07-5144861a78fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645900227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3645900227
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3504655867
Short name T178
Test name
Test status
Simulation time 183985120087 ps
CPU time 450.86 seconds
Started Jun 06 02:44:01 PM PDT 24
Finished Jun 06 02:51:34 PM PDT 24
Peak memory 257472 kb
Host smart-27bb148b-5634-43d8-ba51-2191d986a322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504655867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3504655867
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1250853467
Short name T251
Test name
Test status
Simulation time 11697818683 ps
CPU time 61.37 seconds
Started Jun 06 02:44:03 PM PDT 24
Finished Jun 06 02:45:06 PM PDT 24
Peak memory 252760 kb
Host smart-96c53dc4-2991-465d-b059-43fd8f024c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250853467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1250853467
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1791379634
Short name T931
Test name
Test status
Simulation time 3219133888 ps
CPU time 45.15 seconds
Started Jun 06 02:44:01 PM PDT 24
Finished Jun 06 02:44:48 PM PDT 24
Peak memory 232836 kb
Host smart-a387776b-e1b5-43e8-bbca-e747cf0a3f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791379634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1791379634
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1914413702
Short name T567
Test name
Test status
Simulation time 182398036 ps
CPU time 2.14 seconds
Started Jun 06 02:44:00 PM PDT 24
Finished Jun 06 02:44:03 PM PDT 24
Peak memory 222828 kb
Host smart-26728e91-b21f-4fc3-aedc-8d97e3d80d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914413702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1914413702
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2536929210
Short name T278
Test name
Test status
Simulation time 531099367 ps
CPU time 10.55 seconds
Started Jun 06 02:43:58 PM PDT 24
Finished Jun 06 02:44:10 PM PDT 24
Peak memory 232764 kb
Host smart-162281ba-8ac7-42c3-9486-8d8718b0a1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536929210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2536929210
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3965219963
Short name T712
Test name
Test status
Simulation time 21663340439 ps
CPU time 18.87 seconds
Started Jun 06 02:44:02 PM PDT 24
Finished Jun 06 02:44:23 PM PDT 24
Peak memory 240536 kb
Host smart-f4250ecc-9fe0-4b34-9617-612d39f909f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965219963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3965219963
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.567883292
Short name T346
Test name
Test status
Simulation time 110540986 ps
CPU time 2.19 seconds
Started Jun 06 02:44:00 PM PDT 24
Finished Jun 06 02:44:04 PM PDT 24
Peak memory 222736 kb
Host smart-f5888c89-a7c6-4214-b125-6b3ada82e4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567883292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.567883292
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3057510847
Short name T405
Test name
Test status
Simulation time 1528791464 ps
CPU time 7.55 seconds
Started Jun 06 02:44:03 PM PDT 24
Finished Jun 06 02:44:12 PM PDT 24
Peak memory 220680 kb
Host smart-7d8be96c-56f7-4110-8d1f-7f3bd2c6e922
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3057510847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3057510847
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4115474767
Short name T200
Test name
Test status
Simulation time 27268490067 ps
CPU time 258.08 seconds
Started Jun 06 02:44:03 PM PDT 24
Finished Jun 06 02:48:23 PM PDT 24
Peak memory 249344 kb
Host smart-da5f2d08-955c-4214-9134-b7bb3c7c0357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115474767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4115474767
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2192362129
Short name T326
Test name
Test status
Simulation time 406184653 ps
CPU time 6.4 seconds
Started Jun 06 02:44:01 PM PDT 24
Finished Jun 06 02:44:09 PM PDT 24
Peak memory 216332 kb
Host smart-6cc8fe35-1d21-4b6e-97b6-3b770946792f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192362129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2192362129
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3951104592
Short name T754
Test name
Test status
Simulation time 6943888914 ps
CPU time 19.17 seconds
Started Jun 06 02:44:00 PM PDT 24
Finished Jun 06 02:44:20 PM PDT 24
Peak memory 216200 kb
Host smart-e55f30ec-623b-4a56-8c63-0509c4b92917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951104592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3951104592
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1403042165
Short name T333
Test name
Test status
Simulation time 448076942 ps
CPU time 1.22 seconds
Started Jun 06 02:44:01 PM PDT 24
Finished Jun 06 02:44:04 PM PDT 24
Peak memory 208160 kb
Host smart-be7e3bfb-233d-4059-a837-198425954762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403042165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1403042165
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1359800607
Short name T914
Test name
Test status
Simulation time 751341977 ps
CPU time 0.99 seconds
Started Jun 06 02:44:02 PM PDT 24
Finished Jun 06 02:44:05 PM PDT 24
Peak memory 205732 kb
Host smart-c6516123-a9be-4c79-b9dd-43b2e56f6735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359800607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1359800607
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3353740807
Short name T895
Test name
Test status
Simulation time 35421428180 ps
CPU time 16.88 seconds
Started Jun 06 02:44:01 PM PDT 24
Finished Jun 06 02:44:21 PM PDT 24
Peak memory 233032 kb
Host smart-961a16c6-d1c9-474c-8058-e762347b3d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353740807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3353740807
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1090947280
Short name T802
Test name
Test status
Simulation time 20629954 ps
CPU time 0.7 seconds
Started Jun 06 02:44:12 PM PDT 24
Finished Jun 06 02:44:15 PM PDT 24
Peak memory 205136 kb
Host smart-8cfcbf2f-d183-49db-a2e0-77d746674f92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090947280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1090947280
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2582466099
Short name T771
Test name
Test status
Simulation time 3345546097 ps
CPU time 7.5 seconds
Started Jun 06 02:44:01 PM PDT 24
Finished Jun 06 02:44:11 PM PDT 24
Peak memory 232804 kb
Host smart-3ca0c90f-061b-4c61-a3e7-423bd4c1abda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582466099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2582466099
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2693471471
Short name T842
Test name
Test status
Simulation time 22497771 ps
CPU time 0.75 seconds
Started Jun 06 02:44:06 PM PDT 24
Finished Jun 06 02:44:08 PM PDT 24
Peak memory 206816 kb
Host smart-414236f2-d909-4a38-9d9f-66d9bbe0a5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693471471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2693471471
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2646504494
Short name T384
Test name
Test status
Simulation time 11544499 ps
CPU time 0.72 seconds
Started Jun 06 02:44:05 PM PDT 24
Finished Jun 06 02:44:07 PM PDT 24
Peak memory 215868 kb
Host smart-c1a26336-f9cb-491d-8725-5c31b4073af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646504494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2646504494
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1530703547
Short name T946
Test name
Test status
Simulation time 2888837429 ps
CPU time 55.26 seconds
Started Jun 06 02:44:05 PM PDT 24
Finished Jun 06 02:45:02 PM PDT 24
Peak memory 249688 kb
Host smart-75fcab41-efd1-4c6f-99ef-9ed1f5870060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530703547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1530703547
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1819938240
Short name T624
Test name
Test status
Simulation time 2750225635 ps
CPU time 54.81 seconds
Started Jun 06 02:44:13 PM PDT 24
Finished Jun 06 02:45:09 PM PDT 24
Peak memory 239640 kb
Host smart-07b3f500-d0e7-4db7-ab07-6e2fb91aaea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819938240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1819938240
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2754697005
Short name T673
Test name
Test status
Simulation time 678426016 ps
CPU time 11.2 seconds
Started Jun 06 02:44:03 PM PDT 24
Finished Jun 06 02:44:16 PM PDT 24
Peak memory 224512 kb
Host smart-a84d2909-8aad-45cb-86bb-47ff35f033fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754697005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2754697005
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.4168685077
Short name T896
Test name
Test status
Simulation time 3338669573 ps
CPU time 4.37 seconds
Started Jun 06 02:44:05 PM PDT 24
Finished Jun 06 02:44:10 PM PDT 24
Peak memory 224496 kb
Host smart-2cd7885c-24a8-45c7-b239-9f25a3acf81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168685077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4168685077
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.912276955
Short name T641
Test name
Test status
Simulation time 15806798625 ps
CPU time 37.12 seconds
Started Jun 06 02:44:06 PM PDT 24
Finished Jun 06 02:44:44 PM PDT 24
Peak memory 232796 kb
Host smart-de34bff8-5d04-4098-a3a0-6a5dea6d2ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912276955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.912276955
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1198242300
Short name T806
Test name
Test status
Simulation time 16480575312 ps
CPU time 14.59 seconds
Started Jun 06 02:44:06 PM PDT 24
Finished Jun 06 02:44:22 PM PDT 24
Peak memory 232720 kb
Host smart-fff2b97f-1040-465a-81cc-339388a6574f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198242300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1198242300
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3422643961
Short name T623
Test name
Test status
Simulation time 115218024 ps
CPU time 2.22 seconds
Started Jun 06 02:44:06 PM PDT 24
Finished Jun 06 02:44:09 PM PDT 24
Peak memory 223284 kb
Host smart-90c3d636-b3e2-4592-b9ed-4d3fb0418c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422643961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3422643961
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3484411664
Short name T743
Test name
Test status
Simulation time 2241028628 ps
CPU time 9.35 seconds
Started Jun 06 02:44:00 PM PDT 24
Finished Jun 06 02:44:11 PM PDT 24
Peak memory 222856 kb
Host smart-5a644d9a-0556-4d09-93ef-9fc719e53793
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3484411664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3484411664
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.459864131
Short name T146
Test name
Test status
Simulation time 126809706 ps
CPU time 1.09 seconds
Started Jun 06 02:44:06 PM PDT 24
Finished Jun 06 02:44:09 PM PDT 24
Peak memory 206968 kb
Host smart-2bb6239b-addd-498e-8487-4711c33be763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459864131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.459864131
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1438744448
Short name T323
Test name
Test status
Simulation time 17171911483 ps
CPU time 28.81 seconds
Started Jun 06 02:44:02 PM PDT 24
Finished Jun 06 02:44:33 PM PDT 24
Peak memory 216356 kb
Host smart-391c2128-9579-4641-8ad6-d6aa42f81cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438744448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1438744448
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3973229281
Short name T468
Test name
Test status
Simulation time 29962641 ps
CPU time 0.73 seconds
Started Jun 06 02:44:30 PM PDT 24
Finished Jun 06 02:44:34 PM PDT 24
Peak memory 205468 kb
Host smart-727d7d0e-4387-4f31-97ab-e6354c447c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973229281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3973229281
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1154130358
Short name T762
Test name
Test status
Simulation time 360568079 ps
CPU time 4.52 seconds
Started Jun 06 02:44:07 PM PDT 24
Finished Jun 06 02:44:13 PM PDT 24
Peak memory 216340 kb
Host smart-6fa7b4f2-7e3c-4931-b12e-d1ff4a03ef1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154130358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1154130358
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3807170715
Short name T410
Test name
Test status
Simulation time 87107355 ps
CPU time 0.81 seconds
Started Jun 06 02:44:01 PM PDT 24
Finished Jun 06 02:44:04 PM PDT 24
Peak memory 205748 kb
Host smart-9646cb73-3b2d-4c0b-9e45-2371345984b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807170715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3807170715
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3057529165
Short name T546
Test name
Test status
Simulation time 1876049876 ps
CPU time 8.78 seconds
Started Jun 06 02:44:07 PM PDT 24
Finished Jun 06 02:44:17 PM PDT 24
Peak memory 240124 kb
Host smart-aa337ea0-88e3-42fe-9636-78c1f4b2a57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057529165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3057529165
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4026523775
Short name T940
Test name
Test status
Simulation time 11334926 ps
CPU time 0.71 seconds
Started Jun 06 02:44:12 PM PDT 24
Finished Jun 06 02:44:15 PM PDT 24
Peak memory 204564 kb
Host smart-e1c51905-64c8-4fa5-be30-d499fd6fd2cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026523775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4026523775
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.4233232023
Short name T391
Test name
Test status
Simulation time 379886688 ps
CPU time 3.09 seconds
Started Jun 06 02:44:09 PM PDT 24
Finished Jun 06 02:44:15 PM PDT 24
Peak memory 224464 kb
Host smart-e367e710-dbdc-4d9c-9a88-5cca6dc28450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233232023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.4233232023
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2897753399
Short name T378
Test name
Test status
Simulation time 64147762 ps
CPU time 0.76 seconds
Started Jun 06 02:44:08 PM PDT 24
Finished Jun 06 02:44:10 PM PDT 24
Peak memory 205760 kb
Host smart-302ee952-eb77-4931-a292-586dd7c4b545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897753399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2897753399
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1865802916
Short name T894
Test name
Test status
Simulation time 21884663 ps
CPU time 0.74 seconds
Started Jun 06 02:44:08 PM PDT 24
Finished Jun 06 02:44:10 PM PDT 24
Peak memory 215872 kb
Host smart-4c9d841a-bec9-4c88-8499-a1cf1e4af586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865802916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1865802916
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1465822735
Short name T910
Test name
Test status
Simulation time 66802803543 ps
CPU time 29 seconds
Started Jun 06 02:44:10 PM PDT 24
Finished Jun 06 02:44:42 PM PDT 24
Peak memory 224704 kb
Host smart-14e4e0b9-4e48-4698-96c5-86d34e72eb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465822735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1465822735
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1426013219
Short name T29
Test name
Test status
Simulation time 149101386410 ps
CPU time 308.14 seconds
Started Jun 06 02:44:09 PM PDT 24
Finished Jun 06 02:49:20 PM PDT 24
Peak memory 264916 kb
Host smart-700dcf07-31d4-424b-a49e-b918c8b06bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426013219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1426013219
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.4019547015
Short name T646
Test name
Test status
Simulation time 1321322033 ps
CPU time 21.81 seconds
Started Jun 06 02:44:16 PM PDT 24
Finished Jun 06 02:44:39 PM PDT 24
Peak memory 232668 kb
Host smart-05ba5b0d-702b-43d9-ae49-877e7174affa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019547015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4019547015
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.644309478
Short name T81
Test name
Test status
Simulation time 295568572 ps
CPU time 5.18 seconds
Started Jun 06 02:44:10 PM PDT 24
Finished Jun 06 02:44:18 PM PDT 24
Peak memory 224504 kb
Host smart-44f64ddb-b8f3-4773-a15f-1ca62d9db054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644309478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.644309478
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.859936362
Short name T784
Test name
Test status
Simulation time 371614092 ps
CPU time 8.53 seconds
Started Jun 06 02:44:08 PM PDT 24
Finished Jun 06 02:44:18 PM PDT 24
Peak memory 238540 kb
Host smart-eeec0b1f-3876-4ac4-aded-4cc68da310c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859936362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.859936362
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2406214195
Short name T848
Test name
Test status
Simulation time 1527777771 ps
CPU time 4.18 seconds
Started Jun 06 02:44:09 PM PDT 24
Finished Jun 06 02:44:16 PM PDT 24
Peak memory 224472 kb
Host smart-a09e2fe6-5a94-4af9-86dc-252843f84710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406214195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2406214195
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.447682674
Short name T929
Test name
Test status
Simulation time 15768905058 ps
CPU time 14.21 seconds
Started Jun 06 02:44:15 PM PDT 24
Finished Jun 06 02:44:31 PM PDT 24
Peak memory 232760 kb
Host smart-4632722c-dde6-452f-b9fb-0daa81bf7154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447682674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.447682674
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.60211842
Short name T772
Test name
Test status
Simulation time 6606662161 ps
CPU time 12.79 seconds
Started Jun 06 02:44:09 PM PDT 24
Finished Jun 06 02:44:24 PM PDT 24
Peak memory 220384 kb
Host smart-e0842b23-9439-4ae6-87b7-f447d977a326
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=60211842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direc
t.60211842
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2819851194
Short name T223
Test name
Test status
Simulation time 378066301070 ps
CPU time 924.77 seconds
Started Jun 06 02:44:13 PM PDT 24
Finished Jun 06 02:59:40 PM PDT 24
Peak memory 282040 kb
Host smart-521bc59b-b6d1-443c-b983-aaf1900da4d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819851194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2819851194
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1045720035
Short name T612
Test name
Test status
Simulation time 34567304510 ps
CPU time 25.74 seconds
Started Jun 06 02:44:13 PM PDT 24
Finished Jun 06 02:44:41 PM PDT 24
Peak memory 216424 kb
Host smart-e2e07996-c188-4e52-92d7-d4318666ef9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045720035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1045720035
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.727679009
Short name T582
Test name
Test status
Simulation time 3537322751 ps
CPU time 3.57 seconds
Started Jun 06 02:44:04 PM PDT 24
Finished Jun 06 02:44:09 PM PDT 24
Peak memory 216060 kb
Host smart-5d2269cb-3015-49c9-97b6-0df802c5a5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727679009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.727679009
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3109819978
Short name T342
Test name
Test status
Simulation time 12694122 ps
CPU time 0.7 seconds
Started Jun 06 02:44:04 PM PDT 24
Finished Jun 06 02:44:07 PM PDT 24
Peak memory 205876 kb
Host smart-82cd53fd-6a30-4dda-b1dd-68edd403882f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109819978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3109819978
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3870577914
Short name T68
Test name
Test status
Simulation time 35489621 ps
CPU time 0.66 seconds
Started Jun 06 02:44:12 PM PDT 24
Finished Jun 06 02:44:15 PM PDT 24
Peak memory 205340 kb
Host smart-5e3196db-9428-4220-887c-6a2fdfc9199e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870577914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3870577914
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2814056412
Short name T923
Test name
Test status
Simulation time 74440002 ps
CPU time 2.33 seconds
Started Jun 06 02:44:12 PM PDT 24
Finished Jun 06 02:44:16 PM PDT 24
Peak memory 232480 kb
Host smart-81b80712-e968-49d0-a315-4128a3680ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814056412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2814056412
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3227198393
Short name T719
Test name
Test status
Simulation time 43332306 ps
CPU time 0.69 seconds
Started Jun 06 02:44:28 PM PDT 24
Finished Jun 06 02:44:30 PM PDT 24
Peak memory 204568 kb
Host smart-d4d28a72-d4d8-42c7-aeb2-7089b3538794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227198393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3227198393
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.260307973
Short name T300
Test name
Test status
Simulation time 722250050 ps
CPU time 7.57 seconds
Started Jun 06 02:44:09 PM PDT 24
Finished Jun 06 02:44:19 PM PDT 24
Peak memory 232748 kb
Host smart-35405323-26b0-41ba-8464-97440457caca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260307973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.260307973
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.142458309
Short name T539
Test name
Test status
Simulation time 100955540 ps
CPU time 0.79 seconds
Started Jun 06 02:44:15 PM PDT 24
Finished Jun 06 02:44:18 PM PDT 24
Peak memory 206416 kb
Host smart-dc28b079-4895-48d1-b000-880d9f21f51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142458309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.142458309
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.576646269
Short name T815
Test name
Test status
Simulation time 23381805289 ps
CPU time 154.02 seconds
Started Jun 06 02:44:09 PM PDT 24
Finished Jun 06 02:46:45 PM PDT 24
Peak memory 249176 kb
Host smart-029ee355-9c7b-44ad-a306-351a3364def5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576646269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.576646269
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2708777856
Short name T715
Test name
Test status
Simulation time 14777111338 ps
CPU time 62.45 seconds
Started Jun 06 02:44:14 PM PDT 24
Finished Jun 06 02:45:18 PM PDT 24
Peak memory 249296 kb
Host smart-9da8446d-177e-4cc2-9618-2022a022de62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708777856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2708777856
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1027619273
Short name T600
Test name
Test status
Simulation time 10424008508 ps
CPU time 49.17 seconds
Started Jun 06 02:44:10 PM PDT 24
Finished Jun 06 02:45:02 PM PDT 24
Peak memory 249344 kb
Host smart-86f448c2-2c71-4ce7-aeb5-9b207f67753a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027619273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1027619273
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3899520041
Short name T708
Test name
Test status
Simulation time 332937473 ps
CPU time 8.55 seconds
Started Jun 06 02:44:10 PM PDT 24
Finished Jun 06 02:44:21 PM PDT 24
Peak memory 248268 kb
Host smart-d5971697-2b04-41c9-953b-32bde37406c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899520041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3899520041
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.4208963645
Short name T171
Test name
Test status
Simulation time 7709788726 ps
CPU time 16.89 seconds
Started Jun 06 02:44:08 PM PDT 24
Finished Jun 06 02:44:27 PM PDT 24
Peak memory 224624 kb
Host smart-9f3d536f-9bce-454d-bad7-6fccafaf7b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208963645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.4208963645
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3930237484
Short name T501
Test name
Test status
Simulation time 12607372554 ps
CPU time 44.84 seconds
Started Jun 06 02:44:14 PM PDT 24
Finished Jun 06 02:45:01 PM PDT 24
Peak memory 224532 kb
Host smart-f3dbe2ee-c7bd-497c-9056-6044580528f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930237484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3930237484
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3386420434
Short name T209
Test name
Test status
Simulation time 7411811728 ps
CPU time 11.6 seconds
Started Jun 06 02:44:08 PM PDT 24
Finished Jun 06 02:44:22 PM PDT 24
Peak memory 232744 kb
Host smart-2ae0e1a7-8d9d-408a-baf7-f61e9500df9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386420434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3386420434
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3656413694
Short name T35
Test name
Test status
Simulation time 3742201197 ps
CPU time 14.12 seconds
Started Jun 06 02:44:10 PM PDT 24
Finished Jun 06 02:44:26 PM PDT 24
Peak memory 232828 kb
Host smart-95db3c25-7ca4-4101-9dad-e53168cfaf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656413694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3656413694
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.882892059
Short name T416
Test name
Test status
Simulation time 709553894 ps
CPU time 5 seconds
Started Jun 06 02:44:11 PM PDT 24
Finished Jun 06 02:44:19 PM PDT 24
Peak memory 218720 kb
Host smart-b449400f-5365-4001-a4ba-55fed6caea27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=882892059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.882892059
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3314724541
Short name T838
Test name
Test status
Simulation time 1805038836 ps
CPU time 17.62 seconds
Started Jun 06 02:44:07 PM PDT 24
Finished Jun 06 02:44:26 PM PDT 24
Peak memory 216364 kb
Host smart-53a0c4c4-7631-495b-8ca0-a43da7b29f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314724541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3314724541
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1157295025
Short name T352
Test name
Test status
Simulation time 392804331 ps
CPU time 1.03 seconds
Started Jun 06 02:44:11 PM PDT 24
Finished Jun 06 02:44:15 PM PDT 24
Peak memory 207596 kb
Host smart-02379237-f2a5-4771-9492-aee2bc5f03c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157295025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1157295025
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2252893172
Short name T670
Test name
Test status
Simulation time 42368193 ps
CPU time 0.93 seconds
Started Jun 06 02:44:17 PM PDT 24
Finished Jun 06 02:44:21 PM PDT 24
Peak memory 206548 kb
Host smart-6a52c868-c6c9-4104-9c64-5537f44da27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252893172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2252893172
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3686066527
Short name T609
Test name
Test status
Simulation time 13203115 ps
CPU time 0.75 seconds
Started Jun 06 02:44:17 PM PDT 24
Finished Jun 06 02:44:20 PM PDT 24
Peak memory 205788 kb
Host smart-26c951e5-2d09-4f0f-9c86-c69713875023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686066527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3686066527
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1005947536
Short name T507
Test name
Test status
Simulation time 7147759063 ps
CPU time 24.83 seconds
Started Jun 06 02:44:10 PM PDT 24
Finished Jun 06 02:44:38 PM PDT 24
Peak memory 232732 kb
Host smart-81bd9cf5-5db1-4fec-b1b1-5cc6a0118a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005947536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1005947536
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1231144793
Short name T447
Test name
Test status
Simulation time 16217480 ps
CPU time 0.77 seconds
Started Jun 06 02:44:10 PM PDT 24
Finished Jun 06 02:44:13 PM PDT 24
Peak memory 204536 kb
Host smart-2f5e6be0-2d93-40a0-96fd-600c671c3c3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231144793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1231144793
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3701669156
Short name T814
Test name
Test status
Simulation time 736211376 ps
CPU time 3.66 seconds
Started Jun 06 02:44:15 PM PDT 24
Finished Jun 06 02:44:21 PM PDT 24
Peak memory 224472 kb
Host smart-00af6447-c9be-48fc-abf1-f490df8b0817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701669156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3701669156
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2830816317
Short name T779
Test name
Test status
Simulation time 53457357 ps
CPU time 0.74 seconds
Started Jun 06 02:44:08 PM PDT 24
Finished Jun 06 02:44:10 PM PDT 24
Peak memory 206480 kb
Host smart-316d4199-551f-4e49-a437-9940d174cf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830816317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2830816317
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2997821311
Short name T448
Test name
Test status
Simulation time 23765797391 ps
CPU time 83.98 seconds
Started Jun 06 02:44:21 PM PDT 24
Finished Jun 06 02:45:48 PM PDT 24
Peak memory 249148 kb
Host smart-24d95630-2632-4d4c-a6a9-9669bac78f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997821311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2997821311
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.411962530
Short name T766
Test name
Test status
Simulation time 20570313368 ps
CPU time 98.5 seconds
Started Jun 06 02:44:09 PM PDT 24
Finished Jun 06 02:45:50 PM PDT 24
Peak memory 238916 kb
Host smart-829b3a3a-fe91-4fb5-b8a1-1cb493e7454c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411962530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.411962530
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_intercept.171536113
Short name T489
Test name
Test status
Simulation time 672281885 ps
CPU time 3.29 seconds
Started Jun 06 02:44:12 PM PDT 24
Finished Jun 06 02:44:17 PM PDT 24
Peak memory 224496 kb
Host smart-cc87df16-7aeb-4242-a932-c5635b9b90af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171536113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.171536113
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.539132586
Short name T977
Test name
Test status
Simulation time 34906418 ps
CPU time 2.57 seconds
Started Jun 06 02:44:21 PM PDT 24
Finished Jun 06 02:44:26 PM PDT 24
Peak memory 232468 kb
Host smart-e4fbb414-5cc6-45ce-8052-b36b7117af17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539132586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.539132586
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1975410166
Short name T863
Test name
Test status
Simulation time 5624526645 ps
CPU time 14.64 seconds
Started Jun 06 02:44:11 PM PDT 24
Finished Jun 06 02:44:28 PM PDT 24
Peak memory 224568 kb
Host smart-9744b345-2014-4e5d-bca3-0d6d5b79996f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975410166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1975410166
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3712272557
Short name T972
Test name
Test status
Simulation time 446202926 ps
CPU time 2.96 seconds
Started Jun 06 02:44:11 PM PDT 24
Finished Jun 06 02:44:17 PM PDT 24
Peak memory 232744 kb
Host smart-6d0011c8-26de-4f12-83e8-51e4a3da5fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712272557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3712272557
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.886827923
Short name T515
Test name
Test status
Simulation time 7498381775 ps
CPU time 14.82 seconds
Started Jun 06 02:44:17 PM PDT 24
Finished Jun 06 02:44:34 PM PDT 24
Peak memory 223056 kb
Host smart-326d1fdd-8bdd-49a7-ae9d-77739995a2f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=886827923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.886827923
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2832182402
Short name T130
Test name
Test status
Simulation time 135574291698 ps
CPU time 282.33 seconds
Started Jun 06 02:44:18 PM PDT 24
Finished Jun 06 02:49:02 PM PDT 24
Peak memory 268700 kb
Host smart-812bef09-c39e-4ea9-98bf-45bc9a3176eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832182402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2832182402
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2337710041
Short name T444
Test name
Test status
Simulation time 3230133384 ps
CPU time 13.87 seconds
Started Jun 06 02:44:11 PM PDT 24
Finished Jun 06 02:44:28 PM PDT 24
Peak memory 216468 kb
Host smart-abf74dd1-9306-4c11-83a8-9eee1f788f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337710041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2337710041
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.229764867
Short name T45
Test name
Test status
Simulation time 12666261239 ps
CPU time 7.58 seconds
Started Jun 06 02:44:09 PM PDT 24
Finished Jun 06 02:44:19 PM PDT 24
Peak memory 216320 kb
Host smart-a4488047-b667-45f3-a51e-650ac9663a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229764867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.229764867
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.361202714
Short name T439
Test name
Test status
Simulation time 30713484 ps
CPU time 1.76 seconds
Started Jun 06 02:44:10 PM PDT 24
Finished Jun 06 02:44:15 PM PDT 24
Peak memory 216352 kb
Host smart-d8ec87c6-5a77-43c5-ae40-e5237857e95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361202714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.361202714
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.747118089
Short name T350
Test name
Test status
Simulation time 170955102 ps
CPU time 0.94 seconds
Started Jun 06 02:44:14 PM PDT 24
Finished Jun 06 02:44:17 PM PDT 24
Peak memory 205864 kb
Host smart-229bc709-8c23-415c-ab91-ec3a45216d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747118089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.747118089
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3683188706
Short name T615
Test name
Test status
Simulation time 14003073501 ps
CPU time 16.43 seconds
Started Jun 06 02:44:10 PM PDT 24
Finished Jun 06 02:44:29 PM PDT 24
Peak memory 240488 kb
Host smart-f5449600-97f8-444d-9cd0-49336bced2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683188706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3683188706
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3134780443
Short name T962
Test name
Test status
Simulation time 50984241 ps
CPU time 0.68 seconds
Started Jun 06 02:44:22 PM PDT 24
Finished Jun 06 02:44:25 PM PDT 24
Peak memory 204544 kb
Host smart-f3ea960b-e964-4b11-b8f4-4fac214379ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134780443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3134780443
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.92852943
Short name T199
Test name
Test status
Simulation time 571529346 ps
CPU time 2.72 seconds
Started Jun 06 02:44:10 PM PDT 24
Finished Jun 06 02:44:15 PM PDT 24
Peak memory 224572 kb
Host smart-4213ae8f-bee5-4960-a818-f2e2686fdc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92852943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.92852943
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1491891837
Short name T508
Test name
Test status
Simulation time 40014805 ps
CPU time 0.81 seconds
Started Jun 06 02:44:14 PM PDT 24
Finished Jun 06 02:44:17 PM PDT 24
Peak memory 205852 kb
Host smart-eab25162-5cc3-462d-a1d5-e317062db202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491891837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1491891837
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2447507966
Short name T780
Test name
Test status
Simulation time 2401438119 ps
CPU time 62.6 seconds
Started Jun 06 02:44:21 PM PDT 24
Finished Jun 06 02:45:26 PM PDT 24
Peak memory 254248 kb
Host smart-65c3299c-b7d1-4a57-9a51-6c472a8deeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447507966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2447507966
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.4041656485
Short name T723
Test name
Test status
Simulation time 6410631291 ps
CPU time 92.98 seconds
Started Jun 06 02:44:18 PM PDT 24
Finished Jun 06 02:45:54 PM PDT 24
Peak memory 241064 kb
Host smart-1178baf6-6055-4a03-aa65-e3eac3752cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041656485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.4041656485
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2487602743
Short name T224
Test name
Test status
Simulation time 157997813871 ps
CPU time 357.05 seconds
Started Jun 06 02:44:18 PM PDT 24
Finished Jun 06 02:50:18 PM PDT 24
Peak memory 255328 kb
Host smart-0255aaff-1520-4cda-8281-d94f6b420146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487602743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2487602743
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1210615886
Short name T660
Test name
Test status
Simulation time 1711140269 ps
CPU time 4.45 seconds
Started Jun 06 02:44:22 PM PDT 24
Finished Jun 06 02:44:29 PM PDT 24
Peak memory 232728 kb
Host smart-6424b34d-0838-4b12-9fb5-ce6690ca6615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210615886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1210615886
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.771124729
Short name T271
Test name
Test status
Simulation time 7283568966 ps
CPU time 15.79 seconds
Started Jun 06 02:44:10 PM PDT 24
Finished Jun 06 02:44:29 PM PDT 24
Peak memory 232740 kb
Host smart-a7c6f61e-f675-4b55-980f-2ae3bdaf39a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771124729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.771124729
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.547683141
Short name T569
Test name
Test status
Simulation time 33864062068 ps
CPU time 77.84 seconds
Started Jun 06 02:44:17 PM PDT 24
Finished Jun 06 02:45:37 PM PDT 24
Peak memory 240596 kb
Host smart-a9bb655d-1106-4fa4-80cd-f86a17d17bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547683141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.547683141
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3741737600
Short name T237
Test name
Test status
Simulation time 2119405931 ps
CPU time 7.58 seconds
Started Jun 06 02:44:14 PM PDT 24
Finished Jun 06 02:44:23 PM PDT 24
Peak memory 240868 kb
Host smart-4796abc6-4f67-4c13-802a-810077ec744a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741737600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3741737600
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.509520005
Short name T392
Test name
Test status
Simulation time 115398749 ps
CPU time 2.2 seconds
Started Jun 06 02:44:16 PM PDT 24
Finished Jun 06 02:44:19 PM PDT 24
Peak memory 232388 kb
Host smart-2d696796-0c32-4872-8889-80eb583b6afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509520005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.509520005
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.292292793
Short name T795
Test name
Test status
Simulation time 143040895 ps
CPU time 4.75 seconds
Started Jun 06 02:44:20 PM PDT 24
Finished Jun 06 02:44:27 PM PDT 24
Peak memory 222892 kb
Host smart-5b020d60-a305-4a10-a7e3-3594a62599de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=292292793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.292292793
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2698895759
Short name T37
Test name
Test status
Simulation time 5659126299 ps
CPU time 59.26 seconds
Started Jun 06 02:44:23 PM PDT 24
Finished Jun 06 02:45:24 PM PDT 24
Peak memory 249616 kb
Host smart-5836d8c3-7085-4218-a06b-34fb45e2e3c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698895759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2698895759
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3908070402
Short name T327
Test name
Test status
Simulation time 1673595598 ps
CPU time 8.87 seconds
Started Jun 06 02:44:16 PM PDT 24
Finished Jun 06 02:44:27 PM PDT 24
Peak memory 216328 kb
Host smart-6bcee94f-c26a-406a-b07f-c89964ad92df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908070402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3908070402
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1077952159
Short name T857
Test name
Test status
Simulation time 3113062585 ps
CPU time 9.07 seconds
Started Jun 06 02:44:14 PM PDT 24
Finished Jun 06 02:44:25 PM PDT 24
Peak memory 216304 kb
Host smart-336d7d78-45dd-41e1-8741-ab2a134c4101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077952159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1077952159
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.503404792
Short name T568
Test name
Test status
Simulation time 133527175 ps
CPU time 1.12 seconds
Started Jun 06 02:44:09 PM PDT 24
Finished Jun 06 02:44:12 PM PDT 24
Peak memory 208052 kb
Host smart-ab6d9075-195f-4287-8239-77e4c2ce4efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503404792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.503404792
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.4227471804
Short name T912
Test name
Test status
Simulation time 232047701 ps
CPU time 0.87 seconds
Started Jun 06 02:44:15 PM PDT 24
Finished Jun 06 02:44:18 PM PDT 24
Peak memory 205704 kb
Host smart-ec32358b-5a67-4a29-85a2-aadbdfad6b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227471804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.4227471804
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.4221857200
Short name T669
Test name
Test status
Simulation time 471175791 ps
CPU time 7.95 seconds
Started Jun 06 02:44:09 PM PDT 24
Finished Jun 06 02:44:20 PM PDT 24
Peak memory 257096 kb
Host smart-aa50d1db-01cf-476b-836a-e6794be125d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221857200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.4221857200
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1873523308
Short name T718
Test name
Test status
Simulation time 46625421 ps
CPU time 0.71 seconds
Started Jun 06 02:44:24 PM PDT 24
Finished Jun 06 02:44:27 PM PDT 24
Peak memory 204536 kb
Host smart-7037aa08-faf9-4d65-9b5b-5208589962d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873523308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1873523308
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1916204484
Short name T893
Test name
Test status
Simulation time 36436721 ps
CPU time 2.53 seconds
Started Jun 06 02:44:24 PM PDT 24
Finished Jun 06 02:44:29 PM PDT 24
Peak memory 232680 kb
Host smart-77d082e3-57f3-448c-be1e-1ce105154323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916204484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1916204484
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1487388085
Short name T407
Test name
Test status
Simulation time 68984656 ps
CPU time 0.8 seconds
Started Jun 06 02:44:18 PM PDT 24
Finished Jun 06 02:44:21 PM PDT 24
Peak memory 206472 kb
Host smart-41f3e21c-8022-4d2c-81fe-169dd7249359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487388085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1487388085
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1523681444
Short name T163
Test name
Test status
Simulation time 1334172524 ps
CPU time 19.42 seconds
Started Jun 06 02:44:21 PM PDT 24
Finished Jun 06 02:44:43 PM PDT 24
Peak memory 239940 kb
Host smart-8186209c-ea21-43d5-aaeb-b31c9c653736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523681444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1523681444
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3393914667
Short name T231
Test name
Test status
Simulation time 9878021020 ps
CPU time 46.53 seconds
Started Jun 06 02:44:23 PM PDT 24
Finished Jun 06 02:45:12 PM PDT 24
Peak memory 237528 kb
Host smart-30d436bc-48ce-42ba-8727-932bc8089859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393914667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3393914667
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3138368706
Short name T15
Test name
Test status
Simulation time 5895901500 ps
CPU time 55.66 seconds
Started Jun 06 02:44:21 PM PDT 24
Finished Jun 06 02:45:20 PM PDT 24
Peak memory 236432 kb
Host smart-32ea4a2d-46c5-45a7-a686-f9c11997e9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138368706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3138368706
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2950883675
Short name T419
Test name
Test status
Simulation time 2986347841 ps
CPU time 21.7 seconds
Started Jun 06 02:44:21 PM PDT 24
Finished Jun 06 02:44:45 PM PDT 24
Peak memory 224600 kb
Host smart-03f5c33d-1412-447e-b131-5f6f70443a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950883675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2950883675
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1310633839
Short name T822
Test name
Test status
Simulation time 1103675003 ps
CPU time 4.2 seconds
Started Jun 06 02:44:22 PM PDT 24
Finished Jun 06 02:44:29 PM PDT 24
Peak memory 224488 kb
Host smart-3744cc33-1542-42e6-a33a-6d5c2f7b8420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310633839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1310633839
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1740607801
Short name T83
Test name
Test status
Simulation time 195865878 ps
CPU time 4.22 seconds
Started Jun 06 02:44:25 PM PDT 24
Finished Jun 06 02:44:31 PM PDT 24
Peak memory 224484 kb
Host smart-f66402c5-a135-4fcb-bdf3-263f47cae56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740607801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1740607801
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3117853195
Short name T613
Test name
Test status
Simulation time 6176062457 ps
CPU time 9.82 seconds
Started Jun 06 02:44:19 PM PDT 24
Finished Jun 06 02:44:31 PM PDT 24
Peak memory 240884 kb
Host smart-981164f9-4514-4390-a454-608c5d95ad93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117853195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3117853195
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2546590305
Short name T436
Test name
Test status
Simulation time 211455269 ps
CPU time 2.5 seconds
Started Jun 06 02:44:20 PM PDT 24
Finished Jun 06 02:44:25 PM PDT 24
Peak memory 224504 kb
Host smart-fea9fd26-37d5-4cf4-8af4-14f15f6f8e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546590305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2546590305
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1592347262
Short name T11
Test name
Test status
Simulation time 1286815259 ps
CPU time 18.68 seconds
Started Jun 06 02:44:21 PM PDT 24
Finished Jun 06 02:44:43 PM PDT 24
Peak memory 220092 kb
Host smart-c1a3c786-3bec-4e2b-95ba-de1ee08f1ef5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1592347262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1592347262
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2646371333
Short name T773
Test name
Test status
Simulation time 1952876797 ps
CPU time 14.55 seconds
Started Jun 06 02:44:22 PM PDT 24
Finished Jun 06 02:44:39 PM PDT 24
Peak memory 224668 kb
Host smart-f8983026-ce7d-4800-82d7-64e1dd618a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646371333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2646371333
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1117577791
Short name T775
Test name
Test status
Simulation time 4493724729 ps
CPU time 6.78 seconds
Started Jun 06 02:44:19 PM PDT 24
Finished Jun 06 02:44:29 PM PDT 24
Peak memory 216540 kb
Host smart-770fea85-f830-4c7e-8a5c-d5ef8f02ead0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117577791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1117577791
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1233914183
Short name T374
Test name
Test status
Simulation time 1546393411 ps
CPU time 5.77 seconds
Started Jun 06 02:44:19 PM PDT 24
Finished Jun 06 02:44:28 PM PDT 24
Peak memory 216188 kb
Host smart-7d855642-9605-4d87-9e04-c6a554d7ec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233914183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1233914183
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2895996781
Short name T770
Test name
Test status
Simulation time 156064978 ps
CPU time 2.78 seconds
Started Jun 06 02:44:20 PM PDT 24
Finished Jun 06 02:44:26 PM PDT 24
Peak memory 216372 kb
Host smart-e5ebc199-0a01-46cb-92a9-279669154401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895996781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2895996781
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.565461110
Short name T727
Test name
Test status
Simulation time 64295841 ps
CPU time 0.8 seconds
Started Jun 06 02:44:22 PM PDT 24
Finished Jun 06 02:44:25 PM PDT 24
Peak memory 205712 kb
Host smart-05172431-0a78-4a5b-9012-16164617002b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565461110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.565461110
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1031990351
Short name T903
Test name
Test status
Simulation time 41221825 ps
CPU time 2.29 seconds
Started Jun 06 02:44:25 PM PDT 24
Finished Jun 06 02:44:30 PM PDT 24
Peak memory 224244 kb
Host smart-50bb3d3c-93c8-4184-8a21-fe47f72a204b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031990351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1031990351
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2168078750
Short name T368
Test name
Test status
Simulation time 14364388 ps
CPU time 0.76 seconds
Started Jun 06 02:42:05 PM PDT 24
Finished Jun 06 02:42:07 PM PDT 24
Peak memory 205212 kb
Host smart-be29a50d-36c8-4bc2-8b59-cde8187046d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168078750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
168078750
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.21174270
Short name T190
Test name
Test status
Simulation time 803102127 ps
CPU time 9.45 seconds
Started Jun 06 02:42:11 PM PDT 24
Finished Jun 06 02:42:23 PM PDT 24
Peak memory 232680 kb
Host smart-41255530-4b70-4afa-a371-0e91bd927fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21174270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.21174270
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.984340548
Short name T390
Test name
Test status
Simulation time 16283901 ps
CPU time 0.77 seconds
Started Jun 06 02:42:03 PM PDT 24
Finished Jun 06 02:42:06 PM PDT 24
Peak memory 206788 kb
Host smart-d6a6b8ac-b074-410c-b7c2-d5acfda2bdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984340548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.984340548
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3231762295
Short name T506
Test name
Test status
Simulation time 9395049287 ps
CPU time 79.49 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:43:28 PM PDT 24
Peak memory 240952 kb
Host smart-5f395601-aacd-4587-a0e1-11a23b63a16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231762295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3231762295
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2784480980
Short name T295
Test name
Test status
Simulation time 27545987939 ps
CPU time 185.16 seconds
Started Jun 06 02:42:02 PM PDT 24
Finished Jun 06 02:45:09 PM PDT 24
Peak memory 255240 kb
Host smart-11e388a9-0537-4879-9f50-4f9a08f5709f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784480980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2784480980
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3411441894
Short name T328
Test name
Test status
Simulation time 4943695534 ps
CPU time 82.18 seconds
Started Jun 06 02:42:10 PM PDT 24
Finished Jun 06 02:43:35 PM PDT 24
Peak memory 249256 kb
Host smart-7c795d62-166f-4af3-aab6-64ea1296649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411441894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3411441894
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.902706735
Short name T490
Test name
Test status
Simulation time 341008404 ps
CPU time 7.96 seconds
Started Jun 06 02:42:04 PM PDT 24
Finished Jun 06 02:42:14 PM PDT 24
Peak memory 232692 kb
Host smart-f4ba6dca-05d7-49e5-8b50-a92770c38914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902706735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.902706735
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2087703993
Short name T267
Test name
Test status
Simulation time 1444131695 ps
CPU time 7.23 seconds
Started Jun 06 02:42:01 PM PDT 24
Finished Jun 06 02:42:10 PM PDT 24
Peak memory 218628 kb
Host smart-047abc2d-efa0-4fe5-a4df-c45d54feca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087703993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2087703993
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.495891557
Short name T684
Test name
Test status
Simulation time 55419799 ps
CPU time 1.95 seconds
Started Jun 06 02:42:10 PM PDT 24
Finished Jun 06 02:42:15 PM PDT 24
Peak memory 218512 kb
Host smart-94c3e533-094c-4fe3-992f-47a9a526b356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495891557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.495891557
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2151535527
Short name T667
Test name
Test status
Simulation time 26484516 ps
CPU time 1.06 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:42:10 PM PDT 24
Peak memory 216552 kb
Host smart-55300e9a-a74a-4a62-b54a-8fdff7957170
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151535527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2151535527
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2570835954
Short name T242
Test name
Test status
Simulation time 6709186328 ps
CPU time 13.06 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:42:24 PM PDT 24
Peak memory 224572 kb
Host smart-337c75fa-26a2-4cb9-b978-dd8505c3fda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570835954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2570835954
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1623030444
Short name T204
Test name
Test status
Simulation time 68965198 ps
CPU time 2.88 seconds
Started Jun 06 02:42:04 PM PDT 24
Finished Jun 06 02:42:09 PM PDT 24
Peak memory 232752 kb
Host smart-25780149-e4a6-4a15-8195-da335ae4c25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623030444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1623030444
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4146296465
Short name T139
Test name
Test status
Simulation time 277490995 ps
CPU time 3.51 seconds
Started Jun 06 02:42:18 PM PDT 24
Finished Jun 06 02:42:24 PM PDT 24
Peak memory 218680 kb
Host smart-f83965cb-1f08-411a-a8a7-81d5926f3f4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4146296465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4146296465
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1908236859
Short name T338
Test name
Test status
Simulation time 6572103035 ps
CPU time 34.9 seconds
Started Jun 06 02:42:03 PM PDT 24
Finished Jun 06 02:42:40 PM PDT 24
Peak memory 216344 kb
Host smart-d6403c94-121d-4b84-b445-e50cd260e389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908236859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1908236859
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1302245936
Short name T9
Test name
Test status
Simulation time 4183552962 ps
CPU time 12.14 seconds
Started Jun 06 02:42:03 PM PDT 24
Finished Jun 06 02:42:17 PM PDT 24
Peak memory 216368 kb
Host smart-472da9d0-964a-48c1-a441-97261cf0bfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302245936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1302245936
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.4189378579
Short name T970
Test name
Test status
Simulation time 432028490 ps
CPU time 4.38 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:42:15 PM PDT 24
Peak memory 216308 kb
Host smart-fe52858a-eb75-471e-8799-e1f430d818c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189378579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.4189378579
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3387383916
Short name T648
Test name
Test status
Simulation time 30263054 ps
CPU time 0.82 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:42:11 PM PDT 24
Peak memory 205760 kb
Host smart-a9ac2396-7e73-4d6c-863b-2fc80d1b6826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387383916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3387383916
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2855680488
Short name T618
Test name
Test status
Simulation time 5387533709 ps
CPU time 6.68 seconds
Started Jun 06 02:42:03 PM PDT 24
Finished Jun 06 02:42:12 PM PDT 24
Peak memory 232824 kb
Host smart-4a9cea81-f0b1-41c2-84a0-3a79144acdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855680488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2855680488
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2966973426
Short name T889
Test name
Test status
Simulation time 12196707 ps
CPU time 0.71 seconds
Started Jun 06 02:42:11 PM PDT 24
Finished Jun 06 02:42:14 PM PDT 24
Peak memory 205236 kb
Host smart-3948f5e9-9b0f-45a1-bf79-a1908c2af1cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966973426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
966973426
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2417589394
Short name T739
Test name
Test status
Simulation time 251242416 ps
CPU time 2.87 seconds
Started Jun 06 02:42:10 PM PDT 24
Finished Jun 06 02:42:16 PM PDT 24
Peak memory 232660 kb
Host smart-c554df1b-e91c-4f23-b457-afab98ce9a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417589394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2417589394
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2543374717
Short name T386
Test name
Test status
Simulation time 32387603 ps
CPU time 0.76 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:42:10 PM PDT 24
Peak memory 205424 kb
Host smart-ba3ec221-9063-43ba-bb70-ac1c2a15084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543374717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2543374717
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2789718837
Short name T162
Test name
Test status
Simulation time 633561125 ps
CPU time 13.54 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:42:24 PM PDT 24
Peak memory 236884 kb
Host smart-9a2b7b10-5635-4dec-84fc-de0111841c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789718837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2789718837
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2948978598
Short name T920
Test name
Test status
Simulation time 18038480346 ps
CPU time 60.31 seconds
Started Jun 06 02:42:04 PM PDT 24
Finished Jun 06 02:43:07 PM PDT 24
Peak memory 240692 kb
Host smart-89d4942b-0ccc-458a-80e9-1e64113abcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948978598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2948978598
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1493277064
Short name T871
Test name
Test status
Simulation time 2840916638 ps
CPU time 23.09 seconds
Started Jun 06 02:42:05 PM PDT 24
Finished Jun 06 02:42:30 PM PDT 24
Peak memory 224476 kb
Host smart-c3d53280-80cf-4eb1-ab63-7f31f775b996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493277064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1493277064
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1853409947
Short name T785
Test name
Test status
Simulation time 65808681814 ps
CPU time 118.4 seconds
Started Jun 06 02:42:05 PM PDT 24
Finished Jun 06 02:44:06 PM PDT 24
Peak memory 240800 kb
Host smart-00b2a4e2-9e2b-4cd5-8bf0-2dde36eabd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853409947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1853409947
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.566239680
Short name T370
Test name
Test status
Simulation time 16749809 ps
CPU time 1.05 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:42:10 PM PDT 24
Peak memory 216532 kb
Host smart-15ab5203-fcd1-4737-aa6b-6c76ec082720
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566239680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.566239680
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1731744820
Short name T738
Test name
Test status
Simulation time 903433168 ps
CPU time 4.8 seconds
Started Jun 06 02:42:05 PM PDT 24
Finished Jun 06 02:42:12 PM PDT 24
Peak memory 232728 kb
Host smart-54804fce-b683-480a-af4e-0dd64a54d63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731744820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1731744820
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3597756189
Short name T527
Test name
Test status
Simulation time 404246931 ps
CPU time 2.43 seconds
Started Jun 06 02:42:05 PM PDT 24
Finished Jun 06 02:42:09 PM PDT 24
Peak memory 224444 kb
Host smart-d031c779-2d57-4be2-9058-7d9f136577c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597756189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3597756189
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.4176809607
Short name T398
Test name
Test status
Simulation time 833371857 ps
CPU time 11.07 seconds
Started Jun 06 02:42:11 PM PDT 24
Finished Jun 06 02:42:24 PM PDT 24
Peak memory 219180 kb
Host smart-049f6295-d263-40d9-8323-760fab753d7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4176809607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.4176809607
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.420658027
Short name T153
Test name
Test status
Simulation time 113863709297 ps
CPU time 306.05 seconds
Started Jun 06 02:42:06 PM PDT 24
Finished Jun 06 02:47:14 PM PDT 24
Peak memory 250612 kb
Host smart-cbedeb74-7a64-4f71-98ef-349b010a9ee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420658027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.420658027
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.4266272225
Short name T503
Test name
Test status
Simulation time 4012067330 ps
CPU time 11.96 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:42:23 PM PDT 24
Peak memory 217752 kb
Host smart-e6cb137f-3b18-437d-8abc-41e7aa85a7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266272225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.4266272225
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2061312091
Short name T801
Test name
Test status
Simulation time 18666510422 ps
CPU time 8.03 seconds
Started Jun 06 02:42:06 PM PDT 24
Finished Jun 06 02:42:16 PM PDT 24
Peak memory 216360 kb
Host smart-fdf3bd11-85ee-4973-ab50-b2c645705b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061312091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2061312091
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.4107795365
Short name T44
Test name
Test status
Simulation time 76185409 ps
CPU time 1.05 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:42:11 PM PDT 24
Peak memory 207720 kb
Host smart-ed4854e8-69e1-4b44-a55e-775d8acdf1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107795365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.4107795365
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.322480073
Short name T524
Test name
Test status
Simulation time 18040481 ps
CPU time 0.68 seconds
Started Jun 06 02:42:10 PM PDT 24
Finished Jun 06 02:42:13 PM PDT 24
Peak memory 205356 kb
Host smart-be073f48-aa89-4e0f-8c3e-7d00777a31b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322480073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.322480073
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.4214493197
Short name T580
Test name
Test status
Simulation time 5488779871 ps
CPU time 11.08 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:42:22 PM PDT 24
Peak memory 230348 kb
Host smart-a1dc0c0a-b12c-4f30-b29e-d61dc72bc5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214493197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.4214493197
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2897724386
Short name T61
Test name
Test status
Simulation time 36871557 ps
CPU time 0.78 seconds
Started Jun 06 02:42:10 PM PDT 24
Finished Jun 06 02:42:13 PM PDT 24
Peak memory 204860 kb
Host smart-405dff07-7aac-44fc-b679-998789d3cd65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897724386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
897724386
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1614617855
Short name T296
Test name
Test status
Simulation time 1419998429 ps
CPU time 5.76 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:42:15 PM PDT 24
Peak memory 232724 kb
Host smart-48054b38-7e8d-4d6d-a3e0-ec19e7bf1076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614617855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1614617855
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.149764832
Short name T591
Test name
Test status
Simulation time 19209905 ps
CPU time 0.77 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:42:10 PM PDT 24
Peak memory 205608 kb
Host smart-13b5685d-54ed-4525-aea6-516b9e0087bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149764832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.149764832
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3481930287
Short name T511
Test name
Test status
Simulation time 926620707 ps
CPU time 20.8 seconds
Started Jun 06 02:42:10 PM PDT 24
Finished Jun 06 02:42:33 PM PDT 24
Peak memory 257124 kb
Host smart-6051311a-0d59-44d5-a03a-936e9b73390e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481930287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3481930287
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3724921918
Short name T22
Test name
Test status
Simulation time 116373109500 ps
CPU time 261.2 seconds
Started Jun 06 02:42:06 PM PDT 24
Finished Jun 06 02:46:29 PM PDT 24
Peak memory 273332 kb
Host smart-652dfe88-e738-4eeb-9f6f-4d8c257bc49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724921918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3724921918
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2464164513
Short name T320
Test name
Test status
Simulation time 143415967 ps
CPU time 5.92 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:42:16 PM PDT 24
Peak memory 232756 kb
Host smart-0be9333b-efa5-49ab-a059-be80bf62dd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464164513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2464164513
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3877057568
Short name T636
Test name
Test status
Simulation time 2151148604 ps
CPU time 8.78 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:42:18 PM PDT 24
Peak memory 224572 kb
Host smart-0dbf2a37-c000-4777-8214-e64d4caab75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877057568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3877057568
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3523649728
Short name T716
Test name
Test status
Simulation time 31118811 ps
CPU time 2.03 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:42:11 PM PDT 24
Peak memory 224496 kb
Host smart-4c16890a-6f61-4472-b127-69964cfab280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523649728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3523649728
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.4155024087
Short name T482
Test name
Test status
Simulation time 28530821 ps
CPU time 1.02 seconds
Started Jun 06 02:42:11 PM PDT 24
Finished Jun 06 02:42:14 PM PDT 24
Peak memory 217752 kb
Host smart-ddc1545c-48cf-4ea2-8494-e53592f6a7f5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155024087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.4155024087
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.587190126
Short name T513
Test name
Test status
Simulation time 94659607 ps
CPU time 2.07 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:42:12 PM PDT 24
Peak memory 218412 kb
Host smart-8a5dc615-0d13-4e23-a627-88176f3028bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587190126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
587190126
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.4287881281
Short name T279
Test name
Test status
Simulation time 8475137158 ps
CPU time 12.52 seconds
Started Jun 06 02:42:16 PM PDT 24
Finished Jun 06 02:42:30 PM PDT 24
Peak memory 224616 kb
Host smart-71c0c039-c9bd-43e0-b883-2d1f9175d060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287881281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.4287881281
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1365021252
Short name T443
Test name
Test status
Simulation time 2672970594 ps
CPU time 8.76 seconds
Started Jun 06 02:42:09 PM PDT 24
Finished Jun 06 02:42:20 PM PDT 24
Peak memory 220348 kb
Host smart-14e023bf-e227-4e55-a75e-e85bf46b2fad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1365021252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1365021252
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3278757418
Short name T879
Test name
Test status
Simulation time 3252221084 ps
CPU time 6.31 seconds
Started Jun 06 02:42:09 PM PDT 24
Finished Jun 06 02:42:18 PM PDT 24
Peak memory 216576 kb
Host smart-4d5527f7-c7a7-4c8a-88ed-83e160333573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278757418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3278757418
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2206417601
Short name T630
Test name
Test status
Simulation time 9300946466 ps
CPU time 10.1 seconds
Started Jun 06 02:42:10 PM PDT 24
Finished Jun 06 02:42:23 PM PDT 24
Peak memory 216288 kb
Host smart-b22d46e4-d795-4d2c-aa94-d47b71f9a8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206417601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2206417601
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3331828132
Short name T565
Test name
Test status
Simulation time 504141451 ps
CPU time 2 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:42:13 PM PDT 24
Peak memory 216584 kb
Host smart-ac738dab-37df-42dc-9a32-dc4e7e85bcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331828132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3331828132
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3543689597
Short name T445
Test name
Test status
Simulation time 51813950 ps
CPU time 0.82 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:42:11 PM PDT 24
Peak memory 205968 kb
Host smart-6fd46bfd-cae9-4372-8acd-86b50fde0caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543689597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3543689597
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1333030372
Short name T781
Test name
Test status
Simulation time 40611916 ps
CPU time 2.47 seconds
Started Jun 06 02:42:11 PM PDT 24
Finished Jun 06 02:42:16 PM PDT 24
Peak memory 224288 kb
Host smart-fe65c7d0-a0dd-4348-8dd2-afb6a08f5cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333030372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1333030372
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2311376093
Short name T839
Test name
Test status
Simulation time 139367398 ps
CPU time 0.7 seconds
Started Jun 06 02:42:29 PM PDT 24
Finished Jun 06 02:42:32 PM PDT 24
Peak memory 205136 kb
Host smart-d711ce02-3f7f-4cf4-a0dd-f7e8cfe9c4c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311376093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
311376093
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2869736997
Short name T737
Test name
Test status
Simulation time 196952739 ps
CPU time 2.45 seconds
Started Jun 06 02:42:10 PM PDT 24
Finished Jun 06 02:42:15 PM PDT 24
Peak memory 232668 kb
Host smart-f55b6cf9-d09c-47df-aa31-1a5b972b124c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869736997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2869736997
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.486774610
Short name T549
Test name
Test status
Simulation time 46291875 ps
CPU time 0.77 seconds
Started Jun 06 02:42:10 PM PDT 24
Finished Jun 06 02:42:13 PM PDT 24
Peak memory 205408 kb
Host smart-3daefefb-09a4-4d68-8e12-3aebd11ca066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486774610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.486774610
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3341649250
Short name T273
Test name
Test status
Simulation time 43410459665 ps
CPU time 61.1 seconds
Started Jun 06 02:42:19 PM PDT 24
Finished Jun 06 02:43:22 PM PDT 24
Peak memory 238604 kb
Host smart-9a2a7bfd-7cd5-47cd-9aa9-e76bc9b756f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341649250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3341649250
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2337223358
Short name T16
Test name
Test status
Simulation time 17843694708 ps
CPU time 53.52 seconds
Started Jun 06 02:42:17 PM PDT 24
Finished Jun 06 02:43:13 PM PDT 24
Peak memory 241108 kb
Host smart-0cef43b6-742c-403d-a760-7685f67db455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337223358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2337223358
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.529756053
Short name T948
Test name
Test status
Simulation time 16466877025 ps
CPU time 161.56 seconds
Started Jun 06 02:42:19 PM PDT 24
Finished Jun 06 02:45:03 PM PDT 24
Peak memory 252384 kb
Host smart-e40a4939-cedc-4c5c-85e4-9b18722dc25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529756053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
529756053
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.372135837
Short name T463
Test name
Test status
Simulation time 1937465583 ps
CPU time 11.24 seconds
Started Jun 06 02:42:17 PM PDT 24
Finished Jun 06 02:42:31 PM PDT 24
Peak memory 224488 kb
Host smart-4b72aee5-6095-49df-87f1-e7fa303086c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372135837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.372135837
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1481325656
Short name T286
Test name
Test status
Simulation time 749974952 ps
CPU time 4.97 seconds
Started Jun 06 02:42:11 PM PDT 24
Finished Jun 06 02:42:18 PM PDT 24
Peak memory 232716 kb
Host smart-6530589e-bdfe-41ad-bdd0-6ec05bf551a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481325656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1481325656
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1920523947
Short name T705
Test name
Test status
Simulation time 5878712198 ps
CPU time 53.23 seconds
Started Jun 06 02:42:04 PM PDT 24
Finished Jun 06 02:43:00 PM PDT 24
Peak memory 240384 kb
Host smart-edafab95-ca71-494e-b51c-3e3a343a0ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920523947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1920523947
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.76386891
Short name T400
Test name
Test status
Simulation time 164355268 ps
CPU time 0.97 seconds
Started Jun 06 02:42:09 PM PDT 24
Finished Jun 06 02:42:13 PM PDT 24
Peak memory 217700 kb
Host smart-62c7770e-1bd1-4f42-b474-21d8aa84a8c8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76386891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.76386891
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1407433355
Short name T169
Test name
Test status
Simulation time 4099669053 ps
CPU time 13.73 seconds
Started Jun 06 02:42:08 PM PDT 24
Finished Jun 06 02:42:23 PM PDT 24
Peak memory 224396 kb
Host smart-0d2521b1-9cc5-4e10-aaf9-421268e70685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407433355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1407433355
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2693315738
Short name T651
Test name
Test status
Simulation time 2099838277 ps
CPU time 3.92 seconds
Started Jun 06 02:42:09 PM PDT 24
Finished Jun 06 02:42:16 PM PDT 24
Peak memory 224544 kb
Host smart-1dc11f51-dee7-410d-b25d-924ab96eb7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693315738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2693315738
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3701653166
Short name T399
Test name
Test status
Simulation time 109684525 ps
CPU time 3.63 seconds
Started Jun 06 02:42:27 PM PDT 24
Finished Jun 06 02:42:32 PM PDT 24
Peak memory 222380 kb
Host smart-b2df05a8-cb1b-404d-88c0-6071ddff4c59
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3701653166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3701653166
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1536128665
Short name T465
Test name
Test status
Simulation time 74617152 ps
CPU time 0.93 seconds
Started Jun 06 02:42:17 PM PDT 24
Finished Jun 06 02:42:21 PM PDT 24
Peak memory 205868 kb
Host smart-f68cde00-f8af-4a9b-bd77-f8afde959389
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536128665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1536128665
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.460874931
Short name T504
Test name
Test status
Simulation time 5089304662 ps
CPU time 20.67 seconds
Started Jun 06 02:42:09 PM PDT 24
Finished Jun 06 02:42:32 PM PDT 24
Peak memory 217612 kb
Host smart-0c3a3702-4bc4-4de7-b608-745aaa7c1c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460874931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.460874931
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2632745774
Short name T907
Test name
Test status
Simulation time 751221304 ps
CPU time 5.39 seconds
Started Jun 06 02:42:10 PM PDT 24
Finished Jun 06 02:42:18 PM PDT 24
Peak memory 216252 kb
Host smart-eab82104-aa59-482b-bd40-51b5beed668a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632745774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2632745774
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.966618374
Short name T840
Test name
Test status
Simulation time 435001579 ps
CPU time 3.72 seconds
Started Jun 06 02:42:07 PM PDT 24
Finished Jun 06 02:42:13 PM PDT 24
Peak memory 216276 kb
Host smart-271cc28c-74d2-4b90-938c-355360e95964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966618374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.966618374
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1490823289
Short name T637
Test name
Test status
Simulation time 81364947 ps
CPU time 0.83 seconds
Started Jun 06 02:42:04 PM PDT 24
Finished Jun 06 02:42:07 PM PDT 24
Peak memory 205764 kb
Host smart-32efd306-01fd-426e-b984-fce12e184491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490823289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1490823289
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2607305695
Short name T210
Test name
Test status
Simulation time 4381046148 ps
CPU time 5.05 seconds
Started Jun 06 02:42:10 PM PDT 24
Finished Jun 06 02:42:18 PM PDT 24
Peak memory 224524 kb
Host smart-baee68a1-ff60-447c-a8f8-f333d0b8ca82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607305695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2607305695
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1100437053
Short name T736
Test name
Test status
Simulation time 37637729 ps
CPU time 0.7 seconds
Started Jun 06 02:42:24 PM PDT 24
Finished Jun 06 02:42:26 PM PDT 24
Peak memory 204572 kb
Host smart-5e31ec95-3c4d-4ada-8b5c-3a19174078b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100437053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
100437053
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3210276214
Short name T79
Test name
Test status
Simulation time 306283427 ps
CPU time 2.37 seconds
Started Jun 06 02:42:19 PM PDT 24
Finished Jun 06 02:42:24 PM PDT 24
Peak memory 232684 kb
Host smart-59ae02d5-03c1-46a2-985d-0be403074385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210276214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3210276214
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1473888078
Short name T657
Test name
Test status
Simulation time 32273262 ps
CPU time 0.8 seconds
Started Jun 06 02:42:22 PM PDT 24
Finished Jun 06 02:42:24 PM PDT 24
Peak memory 206488 kb
Host smart-f1a30148-0c7d-4cee-9837-49a6a72ad819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473888078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1473888078
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.290214144
Short name T230
Test name
Test status
Simulation time 10244700941 ps
CPU time 110.16 seconds
Started Jun 06 02:42:19 PM PDT 24
Finished Jun 06 02:44:11 PM PDT 24
Peak memory 249164 kb
Host smart-e3d98c2e-454a-4357-ad59-2c9d180353af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290214144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.290214144
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3870033674
Short name T473
Test name
Test status
Simulation time 16877655246 ps
CPU time 71.68 seconds
Started Jun 06 02:42:18 PM PDT 24
Finished Jun 06 02:43:32 PM PDT 24
Peak memory 249752 kb
Host smart-5e8a3ba8-421b-4bc4-807e-99747c69ba4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870033674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3870033674
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2429068614
Short name T477
Test name
Test status
Simulation time 29157006583 ps
CPU time 127.06 seconds
Started Jun 06 02:42:20 PM PDT 24
Finished Jun 06 02:44:29 PM PDT 24
Peak memory 254908 kb
Host smart-790a7876-c182-4d7c-a803-507964efe93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429068614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2429068614
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3450946585
Short name T747
Test name
Test status
Simulation time 1300380093 ps
CPU time 11.12 seconds
Started Jun 06 02:42:20 PM PDT 24
Finished Jun 06 02:42:33 PM PDT 24
Peak memory 240760 kb
Host smart-e8f92a92-e835-4fcb-bf9c-5d5f0956c181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450946585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3450946585
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1723790714
Short name T32
Test name
Test status
Simulation time 830348861 ps
CPU time 8.66 seconds
Started Jun 06 02:42:17 PM PDT 24
Finished Jun 06 02:42:28 PM PDT 24
Peak memory 219544 kb
Host smart-2606edf3-1d5b-4fdb-a29a-1218203e2426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723790714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1723790714
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3591108730
Short name T307
Test name
Test status
Simulation time 5645338327 ps
CPU time 14.48 seconds
Started Jun 06 02:42:19 PM PDT 24
Finished Jun 06 02:42:36 PM PDT 24
Peak memory 224576 kb
Host smart-e1e6331d-02fe-4ed4-9396-320467e9de74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591108730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3591108730
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.4263707267
Short name T530
Test name
Test status
Simulation time 31696201 ps
CPU time 1.05 seconds
Started Jun 06 02:42:19 PM PDT 24
Finished Jun 06 02:42:22 PM PDT 24
Peak memory 217752 kb
Host smart-e95e88a6-9b03-48a0-bee9-546468ba9416
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263707267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.4263707267
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2158724322
Short name T246
Test name
Test status
Simulation time 144118415 ps
CPU time 5.03 seconds
Started Jun 06 02:42:19 PM PDT 24
Finished Jun 06 02:42:26 PM PDT 24
Peak memory 232712 kb
Host smart-73909242-eb3d-4be4-989e-e0a297bb70a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158724322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2158724322
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3253661107
Short name T175
Test name
Test status
Simulation time 3010110190 ps
CPU time 4.23 seconds
Started Jun 06 02:42:12 PM PDT 24
Finished Jun 06 02:42:18 PM PDT 24
Peak memory 224572 kb
Host smart-8a2dc05a-be86-4088-97ea-50dacc6bfc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253661107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3253661107
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.81195963
Short name T763
Test name
Test status
Simulation time 196471940 ps
CPU time 4.07 seconds
Started Jun 06 02:42:22 PM PDT 24
Finished Jun 06 02:42:28 PM PDT 24
Peak memory 220164 kb
Host smart-9ed5348b-1445-4a2b-a23a-cf9e48d5e466
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=81195963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct
.81195963
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.29415695
Short name T239
Test name
Test status
Simulation time 76636410551 ps
CPU time 547.09 seconds
Started Jun 06 02:42:16 PM PDT 24
Finished Jun 06 02:51:24 PM PDT 24
Peak memory 265996 kb
Host smart-54a92a41-9f45-41ba-bc42-b8d2d996d65f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29415695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_
all.29415695
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.672808822
Short name T336
Test name
Test status
Simulation time 8088122547 ps
CPU time 12.64 seconds
Started Jun 06 02:42:12 PM PDT 24
Finished Jun 06 02:42:32 PM PDT 24
Peak memory 216348 kb
Host smart-1cf8f4f5-867f-424c-9c09-882c1ceb868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672808822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.672808822
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1941800353
Short name T442
Test name
Test status
Simulation time 2660437445 ps
CPU time 2.93 seconds
Started Jun 06 02:42:12 PM PDT 24
Finished Jun 06 02:42:17 PM PDT 24
Peak memory 216328 kb
Host smart-7133531a-eac9-4e7c-aa60-7605e1b43d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941800353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1941800353
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.4017361438
Short name T128
Test name
Test status
Simulation time 252451002 ps
CPU time 2.49 seconds
Started Jun 06 02:42:37 PM PDT 24
Finished Jun 06 02:42:42 PM PDT 24
Peak memory 216292 kb
Host smart-d5fe50f5-a88e-4ebb-9920-f4eeb9293216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017361438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.4017361438
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2623030632
Short name T375
Test name
Test status
Simulation time 75107021 ps
CPU time 0.79 seconds
Started Jun 06 02:42:35 PM PDT 24
Finished Jun 06 02:42:39 PM PDT 24
Peak memory 205724 kb
Host smart-02ad5a75-6cf4-4b8d-a971-f4122fb9bd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623030632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2623030632
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3098728339
Short name T740
Test name
Test status
Simulation time 20877441092 ps
CPU time 17.56 seconds
Started Jun 06 02:42:17 PM PDT 24
Finished Jun 06 02:42:37 PM PDT 24
Peak memory 234608 kb
Host smart-ce0d4a5a-8852-43a9-a71a-2c639c7249d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098728339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3098728339
Directory /workspace/9.spi_device_upload/latest
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