Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2689086	1			T1	1		T2	1		T3	1
all_values[1]	2689086	1			T1	1		T2	1		T3	1
all_values[2]	2689086	1			T1	1		T2	1		T3	1
all_values[3]	2689086	1			T1	1		T2	1		T3	1
all_values[4]	2689086	1			T1	1		T2	1		T3	1
all_values[5]	2689086	1			T1	1		T2	1		T3	1
all_values[6]	2689086	1			T1	1		T2	1		T3	1
all_values[7]	2689086	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20584666

1

T1

8

T2

8

T3

8

auto[1]

928022

1

T69

45

T32

44

T38

124148

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21490205

1

T1

8

T2

8

T3

8

auto[1]

22483

1

T13

6

T14

300

T20

38

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2583794	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	11566	1			T14	176		T20	38		T21	33
all_values[0]	auto[1]	auto[0]	93041	1			T69	3		T32	3		T38	6
all_values[0]	auto[1]	auto[1]	685	1			T69	4		T32	2		T38	2
all_values[1]	auto[0]	auto[0]	2545382	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	5325	1			T14	92		T21	33		T31	69
all_values[1]	auto[1]	auto[0]	137692	1			T69	1		T32	4		T38	7
all_values[1]	auto[1]	auto[1]	687	1			T32	3		T38	6		T42	3
all_values[2]	auto[0]	auto[0]	2607313	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	1921	1			T14	32		T69	2		T31	56
all_values[2]	auto[1]	auto[0]	79555	1			T69	8		T32	3		T38	5
all_values[2]	auto[1]	auto[1]	297	1			T32	1		T38	6		T71	1
all_values[3]	auto[0]	auto[0]	2568940	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	190	1			T69	1		T32	1		T89	4
all_values[3]	auto[1]	auto[0]	119771	1			T69	4		T32	4		T38	31021
all_values[3]	auto[1]	auto[1]	185	1			T69	5		T32	7		T38	5
all_values[4]	auto[0]	auto[0]	2591001	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	187	1			T69	1		T32	5		T38	6
all_values[4]	auto[1]	auto[0]	97722	1			T69	1		T32	4		T38	31022
all_values[4]	auto[1]	auto[1]	176	1			T69	2		T38	5		T42	3
all_values[5]	auto[0]	auto[0]	2555011	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	314	1			T13	6		T69	1		T148	5
all_values[5]	auto[1]	auto[0]	133578	1			T69	6		T32	4		T38	7
all_values[5]	auto[1]	auto[1]	183	1			T69	2		T32	2		T38	7
all_values[6]	auto[0]	auto[0]	2601401	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	197	1			T69	2		T32	4		T38	7
all_values[6]	auto[1]	auto[0]	87294	1			T69	1		T32	1		T38	31018
all_values[6]	auto[1]	auto[1]	194	1			T69	2		T32	4		T38	6
all_values[7]	auto[0]	auto[0]	2511927	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	197	1			T32	3		T38	4		T71	2
all_values[7]	auto[1]	auto[0]	176783	1			T69	2		T32	1		T38	31018
all_values[7]	auto[1]	auto[1]	179	1			T69	4		T32	1		T38	7