Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33513	1			T1	6		T2	2		T4	14
auto[SpiFlashAddrCfg]	6653	1			T2	2		T11	2		T33	10
auto[SpiFlashAddr3b]	8219	1			T2	4		T4	6		T12	2
auto[SpiFlashAddr4b]	6477	1			T4	4		T12	1		T14	51

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30706

1

T1

6

T2

8

T11

10

auto[1]

24156

1

T4

24

T33

16

T14

100

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29838

1

T1

6

T2

2

T4

12

auto[1]

25024

1

T2

6

T4

12

T11

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37714	1			T1	6		T2	6		T4	8
values[1]	942	1			T4	2		T14	6		T20	2
values[2]	1341	1			T14	6		T20	5		T21	5
values[3]	1198	1			T2	2		T4	2		T14	9
values[4]	1273	1			T4	2		T33	2		T14	6
values[5]	1201	1			T11	2		T14	5		T20	5
values[6]	1350	1			T4	4		T12	1		T14	9
values[7]	1342	1			T14	5		T20	5		T21	6
values[8]	8501	1			T4	6		T11	2		T12	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28388

1

T1

6

T2

8

T4

24

auto[1]

26474

1

T12

3

T14

249

T20

143

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

52981

1

T1

6

T2

8

T4

24

write

1881

1

T14

16

T20

7

T21

8

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

17297

1

T1

6

T2

2

T4

8

valids[0x1]

37565

1

T2

6

T4

16

T11

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1345	1			T2	2		T11	2		T14	3
internal_process_ops[0x5a]	1409	1			T2	4		T14	10		T20	6
internal_process_ops[0x05]	21204	1			T4	6		T14	52		T52	6
internal_process_ops[0x35]	1429	1			T4	4		T11	2		T14	9
internal_process_ops[0x15]	1400	1			T2	2		T11	2		T14	7
internal_process_ops[0x03]	920	1			T12	1		T14	3		T21	2
internal_process_ops[0x0b]	986	1			T33	4		T14	2		T20	1
internal_process_ops[0x3b]	965	1			T33	2		T14	1		T21	4
internal_process_ops[0x6b]	871	1			T4	2		T33	4		T14	1
internal_process_ops[0xbb]	970	1			T11	2		T12	2		T14	2
internal_process_ops[0xeb]	929	1			T4	2		T14	3		T20	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53956

1

T1

6

T2

8

T4

24

auto[1]

906

1

T14

8

T20

2

T21

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52944

1

T1

6

T2

8

T4

24

auto[1]

1918

1

T14

11

T20

2

T21

3

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9670

1

T1

6

T2

2

T11

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6325

1

T4

14

T33

2

T21

15

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1939

1

T2

2

T11

2

T21

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1702

1

T33

10

T35

8

T21

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2308

1

T2

4

T21

12

T36

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2089

1

T4

6

T33

4

T35

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1763

1

T21

4

T149

2

T31

22

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1609

1

T4

4

T21

10

T44

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

59

1

T31

2

T32

2

T37

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

47

1

T32

3

T23

2

T42

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

57

1

T31

1

T32

3

T23

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

65

1

T23

1

T37

1

T39

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

74

1

T32

2

T23

3

T37

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

53

1

T23

2

T37

1

T38

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

66

1

T21

2

T31

1

T23

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

80

1

T21

3

T31

3

T150

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

71

1

T36

4

T31

1

T23

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

46

1

T37

1

T41

2

T151

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

53

1

T32

1

T23

3

T37

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

81

1

T31

1

T37

3

T150

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

53

1

T31

1

T37

3

T40

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

51

1

T152

1

T83

1

T153

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

69

1

T31

1

T23

1

T38

7

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

58

1

T21

3

T31

4

T32

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9842

1

T14

87

T20

44

T31

91

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7249

1

T14

31

T20

18

T31

204

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1282

1

T14

12

T20

20

T31

31

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1226

1

T14

12

T20

12

T31

21

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1702

1

T12

2

T14

25

T20

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1644

1

T14

19

T20

9

T31

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1330

1

T12

1

T14

22

T20

11

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1301

1

T14

25

T20

14

T31

20

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

61

1

T14

1

T20

4

T65

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

34

1

T14

1

T31

3

T65

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

49

1

T20

1

T65

3

T83

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

55

1

T31

1

T66

2

T154

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

66

1

T66

1

T154

1

T155

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

56

1

T14

1

T24

2

T155

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

63

1

T14

4

T65

5

T156

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

46

1

T14

2

T20

2

T154

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

53

1

T31

2

T65

1

T66

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

60

1

T66

5

T24

3

T156

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

54

1

T14

1

T24

3

T154

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

58

1

T14

2

T24

2

T154

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

39

1

T66

1

T157

1

T58

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

47

1

T31

2

T66

1

T24

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

88

1

T14

2

T24

2

T156

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

69

1

T14

2

T31

1

T65

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3882	1			T1	6		T35	2		T21	15
auto[0]	values[0]	valids[0x1]	14661	1			T2	6		T4	8		T11	6
auto[0]	values[1]	valids[0x1]	489	1			T4	2		T31	7		T32	10
auto[0]	values[2]	valids[0x0]	507	1			T21	2		T31	6		T32	8
auto[0]	values[2]	valids[0x1]	294	1			T21	3		T31	6		T32	5
auto[0]	values[3]	valids[0x0]	447	1			T2	2		T4	2		T21	2
auto[0]	values[3]	valids[0x1]	259	1			T44	4		T31	6		T32	3
auto[0]	values[4]	valids[0x0]	462	1			T4	2		T33	2		T31	9
auto[0]	values[4]	valids[0x1]	312	1			T31	3		T32	3		T23	1
auto[0]	values[5]	valids[0x0]	399	1			T21	3		T44	2		T149	2
auto[0]	values[5]	valids[0x1]	265	1			T11	2		T46	4		T31	3
auto[0]	values[6]	valids[0x0]	521	1			T4	4		T35	2		T21	4
auto[0]	values[6]	valids[0x1]	289	1			T31	2		T32	7		T23	7
auto[0]	values[7]	valids[0x0]	486	1			T21	4		T31	5		T32	4
auto[0]	values[7]	valids[0x1]	286	1			T21	2		T48	2		T31	1
auto[0]	values[8]	valids[0x0]	3047	1			T11	2		T33	8		T21	11
auto[0]	values[8]	valids[0x1]	1782	1			T4	6		T33	2		T21	9
auto[1]	values[0]	valids[0x0]	3634	1			T14	39		T20	30		T31	43
auto[1]	values[0]	valids[0x1]	15537	1			T14	98		T20	50		T31	279
auto[1]	values[1]	valids[0x1]	453	1			T14	6		T20	2		T31	9
auto[1]	values[2]	valids[0x0]	310	1			T14	1		T20	3		T31	3
auto[1]	values[2]	valids[0x1]	230	1			T14	5		T20	2		T31	1
auto[1]	values[3]	valids[0x0]	274	1			T14	6		T20	3		T65	5
auto[1]	values[3]	valids[0x1]	218	1			T14	3		T20	1		T31	1
auto[1]	values[4]	valids[0x0]	264	1			T14	4		T31	8		T65	4
auto[1]	values[4]	valids[0x1]	235	1			T14	2		T65	7		T89	1
auto[1]	values[5]	valids[0x0]	294	1			T14	2		T20	5		T31	2
auto[1]	values[5]	valids[0x1]	243	1			T14	3		T31	1		T65	3
auto[1]	values[6]	valids[0x0]	293	1			T14	4		T20	6		T31	6
auto[1]	values[6]	valids[0x1]	247	1			T12	1		T14	5		T20	4
auto[1]	values[7]	valids[0x0]	338	1			T14	4		T20	1		T31	8
auto[1]	values[7]	valids[0x1]	232	1			T14	1		T20	4		T31	4
auto[1]	values[8]	valids[0x0]	2139	1			T12	2		T14	38		T20	17
auto[1]	values[8]	valids[0x1]	1533	1			T14	28		T20	15		T31	24