Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3141010

1

T1

106

T2

60574

T4

1

auto[1]

19780

1

T14

49

T20

3

T21

10

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

952785

1

T1

106

T2

60062

T4

1

auto[1]

2208005

1

T2

512

T14

11203

T20

11303

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	572821	1			T1	13		T2	2779		T4	1
auto[524288:1048575]	363450	1			T2	12440		T12	3		T14	2786
auto[1048576:1572863]	332548	1			T1	25		T2	9338		T9	1
auto[1572864:2097151]	394498	1			T2	14168		T9	1		T12	913
auto[2097152:2621439]	369437	1			T1	48		T12	231		T14	2688
auto[2621440:3145727]	367728	1			T1	20		T2	13852		T9	8
auto[3145728:3670015]	367847	1			T2	7997		T12	879		T14	768
auto[3670016:4194303]	392461	1			T12	1331		T14	273		T51	418

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2228283

1

T1

20

T2

554

T4

1

auto[1]

932507

1

T1

86

T2

60020

T5

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2767042

1

T1

106

T2

60574

T4

1

auto[1]

393748

1

T14

288

T20

2509

T21

13

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	201510	1			T1	13		T2	2524		T4	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	309124	1			T2	255		T20	5175		T21	256
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	130815	1			T2	12185		T12	3		T14	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	189391	1			T2	255		T14	2782		T20	1401
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	101369	1			T1	25		T2	9338		T9	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	204056	1			T14	3658		T20	1173		T21	1944
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	110326	1			T2	14166		T9	1		T12	913
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	220538	1			T2	2		T14	128		T20	206
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	71122	1			T1	48		T12	231		T14	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	248421	1			T14	2673		T31	6797		T32	1954
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	124641	1			T1	20		T2	13852		T9	8
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	196916	1			T14	648		T20	460		T31	3175
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	115579	1			T2	7997		T12	879		T14	8
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	188629	1			T14	758		T20	256		T31	3205
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	84742	1			T12	1331		T14	3		T51	418
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	254024	1			T14	256		T20	128		T31	1257
auto[0]	auto[1]	auto[0:524287]	auto[0]	2820	1			T14	1		T31	2		T23	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	56729	1			T31	768		T32	2013		T23	2958
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	979	1			T14	1		T20	2		T31	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	40254	1			T20	2502		T31	129		T65	513
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1132	1			T14	5		T20	2		T21	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	23703	1			T14	1		T20	1		T21	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	370	1			T31	1		T32	4		T23	11
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	60556	1			T32	2835		T23	136		T37	3234
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	501	1			T14	1		T20	1		T31	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	46830	1			T31	4		T23	2		T37	2741
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	918	1			T14	2		T31	6		T23	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	42873	1			T14	256		T31	770		T37	4319
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2635	1			T14	2		T31	8		T37	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	58111	1			T31	4320		T66	1		T41	513
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1404	1			T14	6		T31	2		T23	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	49992	1			T14	5		T31	257		T23	2063
auto[1]	auto[0]	auto[0:524287]	auto[0]	216	1			T31	2		T32	2		T37	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	1814	1			T31	27		T32	20		T37	13
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	171	1			T20	1		T31	2		T37	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1417	1			T20	1		T31	38		T38	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	205	1			T14	4		T21	1		T31	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1747	1			T14	12		T21	1		T31	29
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	193	1			T31	3		T32	2		T66	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1838	1			T31	82		T32	4		T66	25
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	187	1			T14	2		T31	5		T32	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1923	1			T14	9		T31	85		T32	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	190	1			T14	3		T31	1		T37	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1875	1			T14	11		T31	18		T37	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	197	1			T31	4		T37	2		T65	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2091	1			T31	15		T37	63		T65	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	184	1			T31	1		T37	5		T39	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1591	1			T31	2		T37	47		T39	33
auto[1]	auto[1]	auto[0:524287]	auto[0]	49	1			T38	3		T39	2		T41	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	559	1			T38	3		T39	38		T83	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	43	1			T31	1		T65	1		T38	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	380	1			T31	38		T152	2		T154	16
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	37	1			T14	1		T20	1		T21	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	299	1			T14	4		T21	6		T31	14
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	64	1			T23	2		T37	2		T38	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	613	1			T23	12		T37	22		T38	5
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	44	1			T37	1		T40	2		T24	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	409	1			T37	5		T40	2		T161	18
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	38	1			T31	2		T65	1		T154	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	277	1			T65	2		T154	7		T84	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	54	1			T31	1		T66	1		T41	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	551	1			T31	3		T154	15		T83	32
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	50	1			T14	1		T31	1		T23	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	474	1			T14	2		T31	9		T23	7

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1827337	1			T1	20		T2	554		T4	1
auto[0]	auto[0]	auto[1]	923866	1			T1	86		T2	60020		T5	3
auto[0]	auto[1]	auto[0]	381495	1			T14	280		T20	2508		T21	5
auto[0]	auto[1]	auto[1]	8312	1			T31	3		T37	2		T154	3
auto[1]	auto[0]	auto[0]	15566	1			T14	38		T20	2		T21	2
auto[1]	auto[0]	auto[1]	273	1			T14	3		T31	1		T32	3
auto[1]	auto[1]	auto[0]	3885	1			T14	8		T20	1		T21	8
auto[1]	auto[1]	auto[1]	56	1			T38	1		T66	1		T39	2