Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16134

1

T1

6

T2

8

T11

10

auto[1]

12254

1

T4

24

T33

16

T35

10

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3369	1			T2	8		T11	10		T31	20
values[1]	4005	1			T44	20		T36	12		T31	106
values[2]	3700	1			T51	4		T46	14		T149	4
values[3]	3804	1			T1	6		T4	24		T33	16
values[4]	3435	1			T21	20		T48	2		T32	21
values[5]	3571	1			T31	58		T23	29		T37	20
values[6]	3332	1			T21	20		T31	113		T32	40
values[7]	3172	1			T21	30		T31	20		T32	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3428	1			T2	8		T36	12		T31	106
values[1]	3699	1			T21	40		T44	20		T31	108
values[2]	3741	1			T35	10		T51	4		T149	4
values[3]	3675	1			T23	20		T37	131		T38	28
values[4]	3374	1			T21	30		T48	2		T31	20
values[5]	3798	1			T52	14		T21	20		T46	14
values[6]	3854	1			T4	24		T11	10		T33	16
values[7]	2819	1			T1	6		T31	45		T32	44

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	208	1			T2	8		T268	2		T58	10
auto[0]	values[0]	values[1]	211	1			T31	11		T42	16		T84	17
auto[0]	values[0]	values[2]	147	1			T84	15		T53	18		T259	14
auto[0]	values[0]	values[3]	236	1			T184	2		T144	13		T255	18
auto[0]	values[0]	values[4]	315	1			T23	14		T49	18		T152	20
auto[0]	values[0]	values[5]	341	1			T171	22		T152	16		T243	4
auto[0]	values[0]	values[6]	392	1			T11	10		T37	102		T38	20
auto[0]	values[0]	values[7]	169	1			T23	22		T166	11		T232	10
auto[0]	values[1]	values[0]	497	1			T36	12		T31	40		T84	13
auto[0]	values[1]	values[1]	239	1			T31	42		T23	17		T152	11
auto[0]	values[1]	values[2]	363	1			T23	12		T37	15		T227	20
auto[0]	values[1]	values[3]	329	1			T38	4		T153	23		T169	17
auto[0]	values[1]	values[4]	251	1			T41	19		T84	29		T83	24
auto[0]	values[1]	values[5]	367	1			T153	14		T167	8		T232	12
auto[0]	values[1]	values[6]	190	1			T191	6		T32	10		T162	13
auto[0]	values[1]	values[7]	114	1			T84	13		T64	10		T144	15
auto[0]	values[2]	values[0]	183	1			T41	13		T83	22		T153	11
auto[0]	values[2]	values[1]	241	1			T32	11		T82	22		T39	10
auto[0]	values[2]	values[2]	593	1			T51	4		T149	4		T160	9
auto[0]	values[2]	values[3]	223	1			T153	11		T58	15		T227	7
auto[0]	values[2]	values[4]	152	1			T23	11		T158	2		T269	7
auto[0]	values[2]	values[5]	296	1			T150	11		T38	11		T41	10
auto[0]	values[2]	values[6]	244	1			T32	17		T83	11		T64	9
auto[0]	values[2]	values[7]	148	1			T32	18		T80	10		T232	7
auto[0]	values[3]	values[0]	244	1			T32	11		T37	13		T188	4
auto[0]	values[3]	values[1]	329	1			T21	12		T31	15		T71	11
auto[0]	values[3]	values[2]	209	1			T77	2		T153	65		T227	11
auto[0]	values[3]	values[3]	144	1			T152	27		T180	12		T168	13
auto[0]	values[3]	values[4]	323	1			T176	6		T160	11		T53	15
auto[0]	values[3]	values[5]	189	1			T52	14		T31	9		T37	9
auto[0]	values[3]	values[6]	390	1			T23	16		T37	16		T41	7
auto[0]	values[3]	values[7]	276	1			T1	6		T31	9		T32	9
auto[0]	values[4]	values[0]	66	1			T40	10		T42	11		T182	2
auto[0]	values[4]	values[1]	251	1			T23	8		T152	12		T58	10
auto[0]	values[4]	values[2]	252	1			T23	7		T37	26		T41	8
auto[0]	values[4]	values[3]	392	1			T23	14		T37	103		T40	12
auto[0]	values[4]	values[4]	243	1			T48	2		T38	10		T42	9
auto[0]	values[4]	values[5]	194	1			T21	13		T38	13		T167	17
auto[0]	values[4]	values[6]	239	1			T32	15		T40	30		T152	22
auto[0]	values[4]	values[7]	197	1			T150	10		T40	10		T152	22
auto[0]	values[5]	values[0]	326	1			T31	11		T37	14		T42	12
auto[0]	values[5]	values[1]	187	1			T83	7		T153	11		T64	11
auto[0]	values[5]	values[2]	342	1			T40	17		T41	7		T153	16
auto[0]	values[5]	values[3]	252	1			T39	52		T84	13		T253	6
auto[0]	values[5]	values[4]	273	1			T23	22		T40	15		T152	25
auto[0]	values[5]	values[5]	234	1			T42	11		T159	4		T84	11
auto[0]	values[5]	values[6]	166	1			T153	17		T246	20		T270	8
auto[0]	values[5]	values[7]	156	1			T38	12		T41	14		T90	12
auto[0]	values[6]	values[0]	187	1			T32	12		T38	13		T151	8
auto[0]	values[6]	values[1]	182	1			T21	12		T39	12		T84	13
auto[0]	values[6]	values[2]	203	1			T31	7		T32	9		T37	16
auto[0]	values[6]	values[3]	284	1			T175	16		T153	45		T64	16
auto[0]	values[6]	values[4]	196	1			T31	10		T38	12		T180	6
auto[0]	values[6]	values[5]	139	1			T31	9		T84	14		T83	13
auto[0]	values[6]	values[6]	263	1			T39	29		T40	15		T41	17
auto[0]	values[6]	values[7]	308	1			T31	12		T163	14		T40	27
auto[0]	values[7]	values[0]	173	1			T40	10		T53	19		T271	18
auto[0]	values[7]	values[1]	343	1			T32	9		T272	150		T204	23
auto[0]	values[7]	values[2]	148	1			T31	10		T37	12		T56	18
auto[0]	values[7]	values[3]	340	1			T84	6		T153	17		T164	96
auto[0]	values[7]	values[4]	194	1			T21	8		T151	14		T164	10
auto[0]	values[7]	values[5]	351	1			T41	24		T153	12		T53	8
auto[0]	values[7]	values[6]	216	1			T41	14		T273	14		T227	11
auto[0]	values[7]	values[7]	284	1			T23	32		T152	31		T180	5
auto[1]	values[0]	values[0]	238	1			T58	18		T180	9		T144	16
auto[1]	values[0]	values[1]	165	1			T31	9		T42	5		T84	12
auto[1]	values[0]	values[2]	66	1			T84	8		T53	3		T259	6
auto[1]	values[0]	values[3]	275	1			T144	11		T232	21		T259	9
auto[1]	values[0]	values[4]	181	1			T23	8		T84	28		T64	14
auto[1]	values[0]	values[5]	107	1			T152	4		T227	9		T162	11
auto[1]	values[0]	values[6]	229	1			T37	10		T38	9		T178	20
auto[1]	values[0]	values[7]	89	1			T23	7		T166	9		T232	13
auto[1]	values[1]	values[0]	149	1			T31	8		T84	7		T64	17
auto[1]	values[1]	values[1]	397	1			T44	20		T31	16		T23	3
auto[1]	values[1]	values[2]	128	1			T23	8		T37	5		T227	29
auto[1]	values[1]	values[3]	237	1			T38	24		T153	14		T169	60
auto[1]	values[1]	values[4]	172	1			T41	26		T84	11		T83	9
auto[1]	values[1]	values[5]	256	1			T153	7		T167	12		T274	16
auto[1]	values[1]	values[6]	233	1			T32	10		T162	7		T169	5
auto[1]	values[1]	values[7]	83	1			T194	8		T84	12		T64	10
auto[1]	values[2]	values[0]	136	1			T41	10		T83	6		T153	9
auto[1]	values[2]	values[1]	207	1			T32	31		T39	82		T40	4
auto[1]	values[2]	values[2]	202	1			T160	11		T153	17		T167	10
auto[1]	values[2]	values[3]	194	1			T153	11		T58	5		T227	13
auto[1]	values[2]	values[4]	79	1			T23	9		T269	13		T217	6
auto[1]	values[2]	values[5]	283	1			T46	14		T150	9		T38	9
auto[1]	values[2]	values[6]	357	1			T32	3		T83	33		T64	11
auto[1]	values[2]	values[7]	162	1			T32	6		T232	18		T204	5
auto[1]	values[3]	values[0]	201	1			T32	13		T37	22		T40	8
auto[1]	values[3]	values[1]	185	1			T21	8		T31	15		T71	16
auto[1]	values[3]	values[2]	255	1			T35	10		T153	3		T227	13
auto[1]	values[3]	values[3]	99	1			T152	28		T180	10		T168	7
auto[1]	values[3]	values[4]	295	1			T160	9		T53	7		T64	7
auto[1]	values[3]	values[5]	252	1			T31	56		T37	11		T83	11
auto[1]	values[3]	values[6]	210	1			T4	24		T33	16		T23	4
auto[1]	values[3]	values[7]	203	1			T31	16		T32	11		T83	31
auto[1]	values[4]	values[0]	68	1			T40	10		T42	9		T129	8
auto[1]	values[4]	values[1]	293	1			T23	12		T152	8		T58	26
auto[1]	values[4]	values[2]	252	1			T23	14		T37	23		T41	14
auto[1]	values[4]	values[3]	189	1			T23	6		T37	28		T40	12
auto[1]	values[4]	values[4]	146	1			T38	10		T42	11		T152	10
auto[1]	values[4]	values[5]	238	1			T21	7		T38	11		T167	7
auto[1]	values[4]	values[6]	217	1			T32	6		T40	38		T152	10
auto[1]	values[4]	values[7]	198	1			T150	10		T40	12		T181	6
auto[1]	values[5]	values[0]	478	1			T31	47		T37	6		T42	8
auto[1]	values[5]	values[1]	238	1			T83	13		T153	9		T64	9
auto[1]	values[5]	values[2]	155	1			T40	5		T41	13		T153	11
auto[1]	values[5]	values[3]	187	1			T39	2		T84	7		T207	15
auto[1]	values[5]	values[4]	124	1			T23	7		T40	8		T152	17
auto[1]	values[5]	values[5]	197	1			T42	9		T84	9		T173	12
auto[1]	values[5]	values[6]	115	1			T153	3		T193	8		T224	16
auto[1]	values[5]	values[7]	141	1			T38	8		T41	9		T164	8
auto[1]	values[6]	values[0]	196	1			T32	8		T38	7		T151	15
auto[1]	values[6]	values[1]	133	1			T21	8		T39	62		T84	7
auto[1]	values[6]	values[2]	206	1			T31	13		T32	11		T37	12
auto[1]	values[6]	values[3]	129	1			T153	9		T64	10		T187	12
auto[1]	values[6]	values[4]	300	1			T31	10		T38	22		T180	14
auto[1]	values[6]	values[5]	180	1			T31	44		T84	7		T83	12
auto[1]	values[6]	values[6]	233	1			T39	11		T40	9		T41	4
auto[1]	values[6]	values[7]	193	1			T31	8		T40	14		T84	7
auto[1]	values[7]	values[0]	78	1			T40	10		T53	7		T275	12
auto[1]	values[7]	values[1]	98	1			T32	11		T204	9		T218	8
auto[1]	values[7]	values[2]	220	1			T31	10		T37	26		T201	14
auto[1]	values[7]	values[3]	165	1			T84	14		T153	3		T164	13
auto[1]	values[7]	values[4]	130	1			T21	22		T151	10		T164	10
auto[1]	values[7]	values[5]	174	1			T41	17		T153	19		T53	12
auto[1]	values[7]	values[6]	160	1			T41	6		T227	9		T164	27
auto[1]	values[7]	values[7]	98	1			T23	5		T152	7		T180	15