Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2689086	1			T1	1		T2	1		T3	1
all_pins[1]	2689086	1			T1	1		T2	1		T3	1
all_pins[2]	2689086	1			T1	1		T2	1		T3	1
all_pins[3]	2689086	1			T1	1		T2	1		T3	1
all_pins[4]	2689086	1			T1	1		T2	1		T3	1
all_pins[5]	2689086	1			T1	1		T2	1		T3	1
all_pins[6]	2689086	1			T1	1		T2	1		T3	1
all_pins[7]	2689086	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21421512	1			T1	8		T2	8		T3	8
values[0x1]	91176	1			T69	19		T32	20		T38	31043
transitions[0x0=>0x1]	90020	1			T69	14		T32	17		T38	31032
transitions[0x1=>0x0]	90032	1			T69	14		T32	17		T38	31032

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2688358	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	728	1			T69	4		T32	2		T38	2
all_pins[0]	transitions[0x0=>0x1]	418	1			T69	4		T32	1		T38	1
all_pins[0]	transitions[0x1=>0x0]	415	1			T32	2		T38	5		T42	3
all_pins[1]	values[0x0]	2688361	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	725	1			T32	3		T38	6		T42	3
all_pins[1]	transitions[0x0=>0x1]	580	1			T32	3		T38	5		T42	2
all_pins[1]	transitions[0x1=>0x0]	163	1			T32	1		T38	5		T71	1
all_pins[2]	values[0x0]	2688778	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	308	1			T32	1		T38	6		T71	1
all_pins[2]	transitions[0x0=>0x1]	256	1			T32	1		T38	6		T71	1
all_pins[2]	transitions[0x1=>0x0]	133	1			T69	5		T32	7		T38	5
all_pins[3]	values[0x0]	2688901	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	185	1			T69	5		T32	7		T38	5
all_pins[3]	transitions[0x0=>0x1]	137	1			T69	3		T32	7		T38	5
all_pins[3]	transitions[0x1=>0x0]	128	1			T38	5		T42	3		T83	4
all_pins[4]	values[0x0]	2688910	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	176	1			T69	2		T38	5		T42	3
all_pins[4]	transitions[0x0=>0x1]	141	1			T69	2		T38	3		T42	2
all_pins[4]	transitions[0x1=>0x0]	1721	1			T69	2		T32	2		T38	5
all_pins[5]	values[0x0]	2687330	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	1756	1			T69	2		T32	2		T38	7
all_pins[5]	transitions[0x0=>0x1]	1295	1			T69	1		T32	1		T38	5
all_pins[5]	transitions[0x1=>0x0]	86658	1			T69	1		T32	3		T38	31003
all_pins[6]	values[0x0]	2601967	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	87119	1			T69	2		T32	4		T38	31005
all_pins[6]	transitions[0x0=>0x1]	87071	1			T69	2		T32	3		T38	31002
all_pins[6]	transitions[0x1=>0x0]	131	1			T69	4		T38	4		T42	2
all_pins[7]	values[0x0]	2688907	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	179	1			T69	4		T32	1		T38	7
all_pins[7]	transitions[0x0=>0x1]	122	1			T69	2		T32	1		T38	5
all_pins[7]	transitions[0x1=>0x0]	683	1			T69	2		T32	2		T42	2