Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	343	1			T21	1		T31	8		T23	1
auto[ReadAddrCrossIntoMailbox]	294	1			T31	5		T32	4		T23	1
auto[ReadAddrCrossOutOfMailbox]	282	1			T31	14		T32	1		T23	2
auto[ReadAddrCrossAllMailbox]	217	1			T31	7		T23	4		T37	5
auto[ReadAddrOutsideMailbox]	3100	1			T4	4		T11	2		T33	10

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2065

1

T4

2

T11

1

T33

5

auto[1]

2171

1

T4

2

T11

1

T33

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	705	1			T21	2		T31	14		T191	2
read_ops[0x0b]	736	1			T33	4		T21	1		T31	13
read_ops[0x3b]	731	1			T33	2		T21	4		T44	2
read_ops[0x6b]	640	1			T4	2		T33	4		T21	4
read_ops[0xbb]	721	1			T11	2		T21	1		T31	9
read_ops[0xeb]	703	1			T4	2		T21	2		T31	11

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T159	2		T227	1		T180	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T31	1		T150	1		T40	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T84	1		T83	1		T64	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T32	1		T40	1		T160	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T31	2		T38	1		T167	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T37	1		T83	1		T227	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T23	2		T160	1		T84	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T31	1		T227	1		T193	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	250	1			T21	1		T31	8		T191	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	252	1			T21	1		T31	2		T191	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T37	2		T152	1		T160	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T31	2		T38	1		T71	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T31	1		T37	1		T38	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T41	1		T64	2		T164	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T31	1		T23	1		T84	3
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T23	1		T41	1		T71	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T31	1		T84	1		T168	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T37	1		T42	1		T160	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	258	1			T33	2		T21	1		T31	6
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	297	1			T33	2		T31	2		T32	9
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T21	1		T31	2		T23	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T38	1		T71	1		T42	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T23	1		T84	1		T83	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T31	2		T32	1		T40	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T31	3		T37	1		T38	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T31	4		T152	1		T160	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T40	2		T41	1		T84	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T31	1		T37	2		T84	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	267	1			T33	1		T21	1		T44	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	270	1			T33	1		T21	2		T44	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T64	1		T262	2		T164	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T40	1		T152	1		T262	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T32	1		T37	2		T152	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T32	1		T84	1		T53	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T37	1		T153	1		T167	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T31	1		T160	1		T84	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T150	1		T84	1		T59	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T31	1		T84	1		T53	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	235	1			T4	1		T33	2		T21	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	248	1			T4	1		T33	2		T21	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T31	2		T38	1		T184	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T184	1		T41	1		T84	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T31	1		T37	1		T150	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T37	1		T40	1		T41	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T31	2		T40	1		T41	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T38	2		T153	1		T59	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T23	2		T84	1		T83	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T31	1		T37	1		T227	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	237	1			T11	1		T31	2		T32	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	276	1			T11	1		T21	1		T31	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T31	1		T84	1		T53	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T37	1		T38	1		T40	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T31	1		T37	1		T40	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T40	2		T83	1		T53	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T31	1		T37	1		T84	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T32	1		T40	1		T41	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T31	1		T37	1		T64	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T31	1		T40	1		T41	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	262	1			T4	1		T21	1		T31	6
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	248	1			T4	1		T21	1		T191	2