Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3087	1			T36	12		T31	20		T77	2
values[1]	3808	1			T51	4		T149	4		T23	37
values[2]	2883	1			T4	24		T31	20		T32	62
values[3]	3403	1			T21	30		T31	20		T37	222
values[4]	3719	1			T35	10		T46	14		T31	38
values[5]	3450	1			T2	8		T52	14		T21	20
values[6]	3522	1			T11	10		T21	40		T44	20
values[7]	4516	1			T1	6		T33	16		T48	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3205	1			T33	16		T51	4		T149	4
values[1]	4114	1			T31	20		T32	66		T80	10
values[2]	3631	1			T4	24		T52	14		T21	20
values[3]	3573	1			T2	8		T11	10		T21	20
values[4]	3847	1			T21	20		T31	153		T23	37
values[5]	3028	1			T46	14		T31	20		T32	40
values[6]	4042	1			T1	6		T35	10		T48	2
values[7]	2948	1			T21	30		T31	65		T23	42

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27907

1

T1

6

T2

8

T4

24

auto[1]

481

1

T21

6

T31

8

T32

5

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[5]]	[values[0]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	392	1			T32	20		T158	2		T151	25
auto[0]	values[0]	values[1]	354	1			T151	19		T152	37		T159	4
auto[0]	values[0]	values[2]	264	1			T77	2		T150	20		T59	20
auto[0]	values[0]	values[3]	352	1			T36	12		T41	21		T160	17
auto[0]	values[0]	values[4]	401	1			T31	19		T91	14		T161	58
auto[0]	values[0]	values[5]	397	1			T41	21		T42	20		T162	20
auto[0]	values[0]	values[6]	538	1			T38	44		T39	73		T160	20
auto[0]	values[0]	values[7]	348	1			T38	20		T40	19		T41	23
auto[0]	values[1]	values[0]	559	1			T51	4		T149	4		T38	27
auto[0]	values[1]	values[1]	375	1			T37	21		T40	22		T41	20
auto[0]	values[1]	values[2]	358	1			T163	14		T64	26		T164	54
auto[0]	values[1]	values[3]	425	1			T41	21		T153	25		T164	58
auto[0]	values[1]	values[4]	664	1			T23	35		T152	24		T53	23
auto[0]	values[1]	values[5]	275	1			T40	24		T144	19		T165	22
auto[0]	values[1]	values[6]	684	1			T166	20		T84	20		T58	47
auto[0]	values[1]	values[7]	374	1			T153	20		T167	24		T168	25
auto[0]	values[2]	values[0]	125	1			T168	20		T169	20		T170	4
auto[0]	values[2]	values[1]	356	1			T31	20		T32	42		T80	10
auto[0]	values[2]	values[2]	329	1			T4	24		T160	20		T83	33
auto[0]	values[2]	values[3]	390	1			T32	20		T150	18		T38	34
auto[0]	values[2]	values[4]	443	1			T39	91		T92	4		T153	73
auto[0]	values[2]	values[5]	422	1			T37	20		T171	22		T151	22
auto[0]	values[2]	values[6]	504	1			T38	20		T83	20		T64	20
auto[0]	values[2]	values[7]	272	1			T23	20		T172	8		T162	72
auto[0]	values[3]	values[0]	224	1			T40	21		T84	21		T153	20
auto[0]	values[3]	values[1]	386	1			T153	20		T173	25		T162	20
auto[0]	values[3]	values[2]	614	1			T37	109		T174	18		T84	20
auto[0]	values[3]	values[3]	535	1			T37	68		T175	16		T39	20
auto[0]	values[3]	values[4]	504	1			T31	17		T39	53		T90	12
auto[0]	values[3]	values[5]	528	1			T37	20		T41	20		T176	6
auto[0]	values[3]	values[6]	318	1			T37	20		T71	27		T83	44
auto[0]	values[3]	values[7]	224	1			T21	27		T152	31		T177	6
auto[0]	values[4]	values[0]	365	1			T31	38		T23	20		T40	20
auto[0]	values[4]	values[1]	825	1			T32	20		T23	20		T178	20
auto[0]	values[4]	values[2]	393	1			T37	26		T41	20		T84	22
auto[0]	values[4]	values[3]	557	1			T84	20		T179	18		T180	23
auto[0]	values[4]	values[4]	284	1			T40	22		T144	24		T162	60
auto[0]	values[4]	values[5]	270	1			T46	14		T32	20		T23	20
auto[0]	values[4]	values[6]	527	1			T35	10		T23	27		T41	24
auto[0]	values[4]	values[7]	422	1			T23	21		T152	20		T84	92
auto[0]	values[5]	values[0]	365	1			T41	21		T181	6		T152	20
auto[0]	values[5]	values[1]	649	1			T37	23		T152	20		T153	70
auto[0]	values[5]	values[2]	401	1			T52	14		T21	18		T31	30
auto[0]	values[5]	values[3]	350	1			T2	8		T40	24		T182	2
auto[0]	values[5]	values[4]	367	1			T40	21		T84	18		T183	18
auto[0]	values[5]	values[5]	308	1			T32	20		T151	42		T166	20
auto[0]	values[5]	values[6]	531	1			T23	49		T41	20		T83	22
auto[0]	values[5]	values[7]	413	1			T31	64		T184	2		T42	20
auto[0]	values[6]	values[0]	559	1			T39	20		T40	20		T185	18
auto[0]	values[6]	values[1]	297	1			T40	45		T151	24		T153	22
auto[0]	values[6]	values[2]	463	1			T44	20		T31	56		T83	38
auto[0]	values[6]	values[3]	370	1			T11	10		T21	19		T37	28
auto[0]	values[6]	values[4]	427	1			T21	20		T31	44		T186	4
auto[0]	values[6]	values[5]	391	1			T167	20		T164	20		T169	20
auto[0]	values[6]	values[6]	498	1			T32	44		T23	20		T187	12
auto[0]	values[6]	values[7]	474	1			T37	34		T40	20		T63	35
auto[0]	values[7]	values[0]	579	1			T33	16		T42	19		T152	20
auto[0]	values[7]	values[1]	791	1			T188	4		T189	4		T64	29
auto[0]	values[7]	values[2]	756	1			T31	53		T37	38		T190	24
auto[0]	values[7]	values[3]	531	1			T191	6		T32	20		T42	20
auto[0]	values[7]	values[4]	687	1			T31	68		T37	26		T49	18
auto[0]	values[7]	values[5]	382	1			T31	20		T192	20		T193	20
auto[0]	values[7]	values[6]	364	1			T1	6		T48	2		T32	20
auto[0]	values[7]	values[7]	377	1			T194	8		T153	20		T192	106
auto[1]	values[0]	values[0]	5	1			T55	1		T195	2		T129	2
auto[1]	values[0]	values[1]	2	1			T151	1		T152	1		-	-
auto[1]	values[0]	values[2]	3	1			T196	3		-	-		-	-
auto[1]	values[0]	values[3]	3	1			T160	3		-	-		-	-
auto[1]	values[0]	values[4]	4	1			T31	1		T197	1		T198	2
auto[1]	values[0]	values[5]	10	1			T41	1		T199	2		T200	6
auto[1]	values[0]	values[6]	9	1			T39	1		T201	2		T202	2
auto[1]	values[0]	values[7]	5	1			T40	1		T153	2		T129	1
auto[1]	values[1]	values[0]	9	1			T38	1		T84	3		T203	1
auto[1]	values[1]	values[1]	11	1			T40	1		T42	1		T153	3
auto[1]	values[1]	values[2]	8	1			T164	4		T204	1		T199	1
auto[1]	values[1]	values[3]	19	1			T41	2		T153	1		T164	4
auto[1]	values[1]	values[4]	20	1			T23	2		T53	1		T162	5
auto[1]	values[1]	values[5]	10	1			T40	1		T144	1		T126	2
auto[1]	values[1]	values[6]	7	1			T58	1		T205	2		T206	1
auto[1]	values[1]	values[7]	10	1			T207	1		T196	4		T208	1
auto[1]	values[2]	values[0]	1	1			T209	1		-	-		-	-
auto[1]	values[2]	values[1]	5	1			T152	3		T199	1		T208	1
auto[1]	values[2]	values[2]	4	1			T168	4		-	-		-	-
auto[1]	values[2]	values[3]	9	1			T150	2		T210	2		T211	2
auto[1]	values[2]	values[4]	6	1			T39	1		T153	1		T212	4
auto[1]	values[2]	values[5]	5	1			T84	1		T53	2		T196	1
auto[1]	values[2]	values[6]	8	1			T207	3		T213	2		T214	1
auto[1]	values[2]	values[7]	4	1			T215	1		T130	3		-	-
auto[1]	values[3]	values[0]	5	1			T40	1		T162	2		T216	1
auto[1]	values[3]	values[1]	16	1			T173	1		T217	2		T218	1
auto[1]	values[3]	values[2]	8	1			T37	3		T83	3		T193	1
auto[1]	values[3]	values[3]	7	1			T37	2		T151	2		T193	1
auto[1]	values[3]	values[4]	13	1			T31	3		T39	1		T218	1
auto[1]	values[3]	values[5]	15	1			T83	3		T144	1		T217	2
auto[1]	values[3]	values[6]	2	1			T164	1		T211	1		-	-
auto[1]	values[3]	values[7]	4	1			T21	3		T126	1		-	-
auto[1]	values[4]	values[0]	1	1			T197	1		-	-		-	-
auto[1]	values[4]	values[1]	26	1			T32	4		T23	1		T58	2
auto[1]	values[4]	values[2]	9	1			T84	1		T219	1		T195	3
auto[1]	values[4]	values[3]	8	1			T179	2		T220	2		T202	1
auto[1]	values[4]	values[4]	6	1			T40	1		T162	1		T201	2
auto[1]	values[4]	values[5]	4	1			T179	3		T221	1		-	-
auto[1]	values[4]	values[6]	18	1			T23	2		T41	1		T84	1
auto[1]	values[4]	values[7]	4	1			T23	1		T84	1		T53	1
auto[1]	values[5]	values[1]	10	1			T153	2		T217	3		T199	2
auto[1]	values[5]	values[2]	12	1			T21	2		T160	3		T203	2
auto[1]	values[5]	values[3]	6	1			T55	1		T222	1		T212	1
auto[1]	values[5]	values[4]	8	1			T40	1		T84	2		T223	1
auto[1]	values[5]	values[5]	7	1			T151	1		T166	1		T53	2
auto[1]	values[5]	values[6]	16	1			T83	1		T168	6		T224	3
auto[1]	values[5]	values[7]	7	1			T31	1		T153	2		T225	4
auto[1]	values[6]	values[0]	4	1			T152	1		T162	1		T218	1
auto[1]	values[6]	values[1]	3	1			T126	1		T208	1		T226	1
auto[1]	values[6]	values[2]	7	1			T31	2		T53	2		T64	1
auto[1]	values[6]	values[3]	8	1			T21	1		T227	3		T168	2
auto[1]	values[6]	values[4]	3	1			T31	1		T201	1		T228	1
auto[1]	values[6]	values[5]	2	1			T229	2		-	-		-	-
auto[1]	values[6]	values[6]	13	1			T164	1		T202	1		T219	4
auto[1]	values[6]	values[7]	3	1			T37	1		T227	1		T196	1
auto[1]	values[7]	values[0]	12	1			T42	2		T53	1		T203	1
auto[1]	values[7]	values[1]	8	1			T230	2		T216	5		T231	1
auto[1]	values[7]	values[2]	2	1			T144	2		-	-		-	-
auto[1]	values[7]	values[3]	3	1			T232	3		-	-		-	-
auto[1]	values[7]	values[4]	10	1			T153	3		T168	3		T126	1
auto[1]	values[7]	values[5]	2	1			T193	1		T233	1		-	-
auto[1]	values[7]	values[6]	5	1			T32	1		T38	2		T162	1
auto[1]	values[7]	values[7]	7	1			T192	2		T203	2		T220	1