Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1789

1

T3

6

T14

8

T15

1

auto[1]

1766

1

T3

7

T14

7

T15

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1883

1

T14

11

T15

7

T20

10

auto[1]

1672

1

T3

13

T14

4

T16

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2806

1

T3

13

T14

9

T15

6

auto[1]

749

1

T14

6

T15

1

T20

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	704	1			T3	3		T14	6		T15	2
valid[1]	715	1			T3	3		T14	5		T15	2
valid[2]	704	1			T3	2		T14	2		T17	2
valid[3]	750	1			T3	2		T14	1		T15	3
valid[4]	682	1			T3	3		T14	1		T16	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	123	1			T21	1		T31	4		T23	1
auto[0]	auto[0]	valid[0]	auto[1]	159	1			T14	3		T22	1		T295	1
auto[0]	auto[0]	valid[1]	auto[0]	122	1			T14	1		T20	3		T21	3
auto[0]	auto[0]	valid[1]	auto[1]	154	1			T3	3		T14	1		T16	1
auto[0]	auto[0]	valid[2]	auto[0]	116	1			T30	1		T31	1		T23	1
auto[0]	auto[0]	valid[2]	auto[1]	162	1			T3	1		T17	1		T296	1
auto[0]	auto[0]	valid[3]	auto[0]	128	1			T15	1		T20	1		T21	3
auto[0]	auto[0]	valid[3]	auto[1]	183	1			T17	1		T65	1		T296	1
auto[0]	auto[0]	valid[4]	auto[0]	101	1			T21	1		T30	1		T31	1
auto[0]	auto[0]	valid[4]	auto[1]	160	1			T3	2		T16	1		T78	4
auto[0]	auto[1]	valid[0]	auto[0]	108	1			T14	1		T15	2		T20	2
auto[0]	auto[1]	valid[0]	auto[1]	176	1			T3	3		T16	1		T78	1
auto[0]	auto[1]	valid[1]	auto[0]	110	1			T14	2		T15	1		T20	1
auto[0]	auto[1]	valid[1]	auto[1]	179	1			T16	2		T17	2		T29	1
auto[0]	auto[1]	valid[2]	auto[0]	108	1			T14	1		T29	1		T31	1
auto[0]	auto[1]	valid[2]	auto[1]	161	1			T3	1		T17	1		T31	1
auto[0]	auto[1]	valid[3]	auto[0]	120	1			T15	2		T20	1		T21	3
auto[0]	auto[1]	valid[3]	auto[1]	170	1			T3	2		T16	3		T40	1
auto[0]	auto[1]	valid[4]	auto[0]	98	1			T21	1		T22	1		T29	1
auto[0]	auto[1]	valid[4]	auto[1]	168	1			T3	1		T16	1		T17	2
auto[1]	auto[0]	valid[0]	auto[0]	61	1			T14	1		T21	1		T29	1
auto[1]	auto[0]	valid[1]	auto[0]	78	1			T14	1		T20	1		T22	1
auto[1]	auto[0]	valid[2]	auto[0]	81	1			T22	1		T37	1		T65	1
auto[1]	auto[0]	valid[3]	auto[0]	74	1			T14	1		T30	1		T31	2
auto[1]	auto[0]	valid[4]	auto[0]	87	1			T29	1		T65	1		T292	1
auto[1]	auto[1]	valid[0]	auto[0]	77	1			T14	1		T20	1		T30	1
auto[1]	auto[1]	valid[1]	auto[0]	72	1			T15	1		T22	1		T29	2
auto[1]	auto[1]	valid[2]	auto[0]	76	1			T14	1		T21	1		T29	1
auto[1]	auto[1]	valid[3]	auto[0]	75	1			T22	1		T29	1		T65	2
auto[1]	auto[1]	valid[4]	auto[0]	68	1			T14	1		T31	2		T32	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal