Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	773	1			T69	8		T32	10		T38	21
all_values[1]	773	1			T69	8		T32	10		T38	21
all_values[2]	773	1			T69	8		T32	10		T38	21
all_values[3]	773	1			T69	8		T32	10		T38	21
all_values[4]	773	1			T69	8		T32	10		T38	21
all_values[5]	773	1			T69	8		T32	10		T38	21
all_values[6]	773	1			T69	8		T32	10		T38	21
all_values[7]	773	1			T69	8		T32	10		T38	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3260

1

T69

36

T32

33

T38

89

auto[1]

2924

1

T69

28

T32

47

T38

79

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2412

1

T69

31

T32

28

T38

64

auto[1]

3772

1

T69

33

T32

52

T38

104

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3522

1

T69

42

T32

48

T38

93

auto[1]

2662

1

T69

22

T32

32

T38

75

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	132	1			T69	1		T38	6		T71	3
all_values[0]	auto[0]	auto[0]	auto[1]	86	1			T32	2		T38	2		T42	1
all_values[0]	auto[0]	auto[1]	auto[0]	122	1			T32	2		T38	6		T42	1
all_values[0]	auto[0]	auto[1]	auto[1]	87	1			T69	2		T32	2		T42	2
all_values[0]	auto[1]	auto[0]	auto[1]	185	1			T69	1		T32	3		T38	6
all_values[0]	auto[1]	auto[1]	auto[1]	161	1			T69	4		T32	1		T38	1
all_values[1]	auto[0]	auto[0]	auto[0]	149	1			T69	5		T32	1		T38	2
all_values[1]	auto[0]	auto[0]	auto[1]	75	1			T32	2		T38	2		T71	1
all_values[1]	auto[0]	auto[1]	auto[0]	182	1			T69	2		T32	2		T38	3
all_values[1]	auto[0]	auto[1]	auto[1]	70	1			T32	2		T38	4		T83	2
all_values[1]	auto[1]	auto[0]	auto[1]	158	1			T69	1		T32	2		T38	5
all_values[1]	auto[1]	auto[1]	auto[1]	139	1			T32	1		T38	5		T42	3
all_values[2]	auto[0]	auto[0]	auto[0]	137	1			T69	1		T32	2		T38	5
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T69	2		T32	1		T38	3
all_values[2]	auto[0]	auto[1]	auto[0]	115	1			T69	4		T32	2		T38	3
all_values[2]	auto[0]	auto[1]	auto[1]	91	1			T32	1		T38	2		T42	1
all_values[2]	auto[1]	auto[0]	auto[1]	199	1			T69	1		T32	2		T38	5
all_values[2]	auto[1]	auto[1]	auto[1]	153	1			T32	2		T38	3		T71	1
all_values[3]	auto[0]	auto[0]	auto[0]	139	1			T38	5		T42	1		T83	3
all_values[3]	auto[0]	auto[0]	auto[1]	74	1			T38	1		T42	1		T83	2
all_values[3]	auto[0]	auto[1]	auto[0]	159	1			T69	1		T32	1		T38	6
all_values[3]	auto[0]	auto[1]	auto[1]	67	1			T69	1		T32	3		T38	1
all_values[3]	auto[1]	auto[0]	auto[1]	158	1			T69	3		T38	3		T71	1
all_values[3]	auto[1]	auto[1]	auto[1]	176	1			T69	3		T32	6		T38	5
all_values[4]	auto[0]	auto[0]	auto[0]	169	1			T69	4		T32	1		T38	2
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T32	2		T38	1		T71	1
all_values[4]	auto[0]	auto[1]	auto[0]	127	1			T32	3		T38	4		T42	1
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T69	1		T32	1		T38	4
all_values[4]	auto[1]	auto[0]	auto[1]	181	1			T69	3		T32	2		T38	5
all_values[4]	auto[1]	auto[1]	auto[1]	141	1			T32	1		T38	5		T42	1
all_values[5]	auto[0]	auto[0]	auto[0]	220	1			T69	1		T32	3		T38	5
all_values[5]	auto[0]	auto[1]	auto[0]	199	1			T69	4		T32	5		T38	4
all_values[5]	auto[1]	auto[0]	auto[1]	199	1			T69	2		T38	5		T42	4
all_values[5]	auto[1]	auto[1]	auto[1]	155	1			T69	1		T32	2		T38	7
all_values[6]	auto[0]	auto[0]	auto[0]	140	1			T69	4		T38	4		T42	3
all_values[6]	auto[0]	auto[0]	auto[1]	89	1			T69	1		T32	1		T38	3
all_values[6]	auto[0]	auto[1]	auto[0]	121	1			T32	1		T38	2		T71	2
all_values[6]	auto[0]	auto[1]	auto[1]	86	1			T69	2		T32	2		T38	3
all_values[6]	auto[1]	auto[0]	auto[1]	172	1			T32	2		T38	7		T71	2
all_values[6]	auto[1]	auto[1]	auto[1]	165	1			T69	1		T32	4		T38	2
all_values[7]	auto[0]	auto[0]	auto[0]	190	1			T69	4		T32	4		T38	5
all_values[7]	auto[0]	auto[0]	auto[1]	82	1			T32	1		T38	1		T71	1
all_values[7]	auto[0]	auto[1]	auto[0]	111	1			T32	1		T38	2		T83	3
all_values[7]	auto[0]	auto[1]	auto[1]	70	1			T69	2		T38	2		T42	1
all_values[7]	auto[1]	auto[0]	auto[1]	171	1			T69	2		T32	2		T38	6
all_values[7]	auto[1]	auto[1]	auto[1]	149	1			T32	2		T38	5		T42	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal