Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48107

1

T13

12

T14

269

T15

189

auto[1]

17631

1

T3

13

T14

60

T16

131

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48180

1

T3

13

T13

5

T14

229

auto[1]

17558

1

T13

7

T14

100

T15

67

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33611	1			T3	13		T13	7		T14	162
others[1]	5562	1			T14	21		T15	14		T16	12
others[2]	5588	1			T14	33		T15	16		T16	15
others[3]	6486	1			T13	2		T14	29		T15	22
interest[1]	3660	1			T13	1		T14	21		T15	11
interest[4]	21978	1			T3	13		T13	7		T14	101
interest[64]	10831	1			T13	2		T14	63		T15	33

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15470	1			T13	2		T14	82		T15	60
auto[0]	auto[0]	others[1]	2581	1			T14	14		T15	9		T20	5
auto[0]	auto[0]	others[2]	2581	1			T14	14		T15	9		T20	13
auto[0]	auto[0]	others[3]	3029	1			T13	1		T14	16		T15	15
auto[0]	auto[0]	interest[1]	1756	1			T13	1		T14	6		T15	8
auto[0]	auto[0]	interest[4]	10159	1			T13	2		T14	51		T15	39
auto[0]	auto[0]	interest[64]	5132	1			T13	1		T14	37		T15	21
auto[0]	auto[1]	others[0]	9173	1			T3	13		T14	32		T16	66
auto[0]	auto[1]	others[1]	1480	1			T14	2		T16	12		T17	11
auto[0]	auto[1]	others[2]	1458	1			T14	4		T16	15		T17	7
auto[0]	auto[1]	others[3]	1728	1			T14	4		T16	9		T17	7
auto[0]	auto[1]	interest[1]	947	1			T14	6		T16	7		T17	2
auto[0]	auto[1]	interest[4]	6046	1			T3	13		T14	21		T16	41
auto[0]	auto[1]	interest[64]	2845	1			T14	12		T16	22		T17	16
auto[1]	auto[0]	others[0]	8968	1			T13	5		T14	48		T15	33
auto[1]	auto[0]	others[1]	1501	1			T14	5		T15	5		T20	7
auto[1]	auto[0]	others[2]	1549	1			T14	15		T15	7		T20	9
auto[1]	auto[0]	others[3]	1729	1			T13	1		T14	9		T15	7
auto[1]	auto[0]	interest[1]	957	1			T14	9		T15	3		T20	4
auto[1]	auto[0]	interest[4]	5773	1			T13	5		T14	29		T15	21
auto[1]	auto[0]	interest[64]	2854	1			T13	1		T14	14		T15	12

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal