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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.11 98.35 94.19 98.61 89.36 97.23 95.82 99.20


Total test records in report: 1101
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T1011 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.435523267 Jun 07 08:32:04 PM PDT 24 Jun 07 08:32:18 PM PDT 24 48500243 ps
T1012 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.110019769 Jun 07 08:31:58 PM PDT 24 Jun 07 08:32:15 PM PDT 24 66709175 ps
T238 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3056785486 Jun 07 08:31:56 PM PDT 24 Jun 07 08:32:17 PM PDT 24 281451342 ps
T122 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2964989569 Jun 07 08:32:04 PM PDT 24 Jun 07 08:32:17 PM PDT 24 61509467 ps
T1013 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.492695557 Jun 07 08:32:04 PM PDT 24 Jun 07 08:32:20 PM PDT 24 24819156 ps
T1014 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3457447844 Jun 07 08:31:46 PM PDT 24 Jun 07 08:32:03 PM PDT 24 439451316 ps
T1015 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3252074470 Jun 07 08:31:59 PM PDT 24 Jun 07 08:32:13 PM PDT 24 19747471 ps
T123 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1457425776 Jun 07 08:31:57 PM PDT 24 Jun 07 08:32:13 PM PDT 24 267410673 ps
T125 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3404253230 Jun 07 08:31:59 PM PDT 24 Jun 07 08:32:14 PM PDT 24 78210556 ps
T1016 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1913817276 Jun 07 08:31:56 PM PDT 24 Jun 07 08:32:10 PM PDT 24 63765645 ps
T1017 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3852415479 Jun 07 08:31:56 PM PDT 24 Jun 07 08:32:13 PM PDT 24 168668235 ps
T1018 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3779114401 Jun 07 08:32:00 PM PDT 24 Jun 07 08:32:17 PM PDT 24 231502916 ps
T1019 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1466166552 Jun 07 08:31:52 PM PDT 24 Jun 07 08:32:07 PM PDT 24 90190334 ps
T1020 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.746415182 Jun 07 08:32:10 PM PDT 24 Jun 07 08:32:21 PM PDT 24 57397269 ps
T1021 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3519707188 Jun 07 08:31:58 PM PDT 24 Jun 07 08:32:14 PM PDT 24 441695180 ps
T1022 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3055775008 Jun 07 08:31:59 PM PDT 24 Jun 07 08:32:13 PM PDT 24 36020014 ps
T1023 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3063910934 Jun 07 08:31:56 PM PDT 24 Jun 07 08:32:12 PM PDT 24 97836221 ps
T1024 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2821470941 Jun 07 08:31:41 PM PDT 24 Jun 07 08:31:58 PM PDT 24 917902825 ps
T1025 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1367180584 Jun 07 08:31:45 PM PDT 24 Jun 07 08:32:00 PM PDT 24 25774252 ps
T239 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1053110591 Jun 07 08:31:58 PM PDT 24 Jun 07 08:32:25 PM PDT 24 528858407 ps
T1026 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3546036207 Jun 07 08:32:01 PM PDT 24 Jun 07 08:32:16 PM PDT 24 60210834 ps
T1027 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2477661162 Jun 07 08:31:47 PM PDT 24 Jun 07 08:32:04 PM PDT 24 108704827 ps
T1028 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1511174473 Jun 07 08:31:41 PM PDT 24 Jun 07 08:31:56 PM PDT 24 298894983 ps
T1029 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3312065475 Jun 07 08:32:02 PM PDT 24 Jun 07 08:32:18 PM PDT 24 107523742 ps
T1030 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1934280102 Jun 07 08:32:08 PM PDT 24 Jun 07 08:32:20 PM PDT 24 40846084 ps
T236 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1349033503 Jun 07 08:31:58 PM PDT 24 Jun 07 08:32:33 PM PDT 24 4049416092 ps
T1031 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2331882643 Jun 07 08:32:11 PM PDT 24 Jun 07 08:32:22 PM PDT 24 19930147 ps
T1032 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1364552390 Jun 07 08:31:59 PM PDT 24 Jun 07 08:32:16 PM PDT 24 548527900 ps
T1033 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.526761088 Jun 07 08:31:50 PM PDT 24 Jun 07 08:32:41 PM PDT 24 10044299266 ps
T1034 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4069412346 Jun 07 08:32:07 PM PDT 24 Jun 07 08:32:19 PM PDT 24 17636003 ps
T1035 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.691079917 Jun 07 08:31:56 PM PDT 24 Jun 07 08:32:17 PM PDT 24 1436068562 ps
T1036 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2998721179 Jun 07 08:31:41 PM PDT 24 Jun 07 08:31:56 PM PDT 24 62351069 ps
T1037 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.342361102 Jun 07 08:31:47 PM PDT 24 Jun 07 08:32:05 PM PDT 24 308155423 ps
T1038 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.460014307 Jun 07 08:32:21 PM PDT 24 Jun 07 08:32:29 PM PDT 24 23804822 ps
T1039 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1013223661 Jun 07 08:31:43 PM PDT 24 Jun 07 08:32:09 PM PDT 24 993620336 ps
T1040 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1450293594 Jun 07 08:31:42 PM PDT 24 Jun 07 08:32:12 PM PDT 24 635763936 ps
T87 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1097390229 Jun 07 08:31:40 PM PDT 24 Jun 07 08:31:53 PM PDT 24 17900649 ps
T1041 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3642681626 Jun 07 08:32:01 PM PDT 24 Jun 07 08:32:14 PM PDT 24 88367661 ps
T1042 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1665728265 Jun 07 08:31:58 PM PDT 24 Jun 07 08:32:15 PM PDT 24 57668378 ps
T1043 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1040793270 Jun 07 08:32:19 PM PDT 24 Jun 07 08:32:28 PM PDT 24 26886953 ps
T1044 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2746542341 Jun 07 08:32:14 PM PDT 24 Jun 07 08:32:25 PM PDT 24 230230934 ps
T1045 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3661840551 Jun 07 08:32:03 PM PDT 24 Jun 07 08:32:16 PM PDT 24 20398679 ps
T1046 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2937730944 Jun 07 08:31:48 PM PDT 24 Jun 07 08:32:14 PM PDT 24 817786169 ps
T235 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1172499137 Jun 07 08:31:56 PM PDT 24 Jun 07 08:32:13 PM PDT 24 180572143 ps
T1047 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1180899550 Jun 07 08:31:55 PM PDT 24 Jun 07 08:32:09 PM PDT 24 39567970 ps
T1048 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2213255357 Jun 07 08:32:06 PM PDT 24 Jun 07 08:32:18 PM PDT 24 25958419 ps
T237 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2699657826 Jun 07 08:32:01 PM PDT 24 Jun 07 08:32:25 PM PDT 24 391598403 ps
T1049 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.622433439 Jun 07 08:31:40 PM PDT 24 Jun 07 08:31:54 PM PDT 24 64845987 ps
T1050 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.248996284 Jun 07 08:32:03 PM PDT 24 Jun 07 08:32:17 PM PDT 24 44718199 ps
T1051 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3017500977 Jun 07 08:31:58 PM PDT 24 Jun 07 08:32:14 PM PDT 24 125158909 ps
T88 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3847927395 Jun 07 08:31:51 PM PDT 24 Jun 07 08:32:06 PM PDT 24 79497269 ps
T1052 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.416705245 Jun 07 08:32:15 PM PDT 24 Jun 07 08:32:24 PM PDT 24 46035969 ps
T1053 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3514448363 Jun 07 08:32:24 PM PDT 24 Jun 07 08:32:32 PM PDT 24 80988803 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2420362963 Jun 07 08:31:51 PM PDT 24 Jun 07 08:32:06 PM PDT 24 40854749 ps
T1055 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2653798104 Jun 07 08:32:06 PM PDT 24 Jun 07 08:32:18 PM PDT 24 44975531 ps
T1056 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2339188432 Jun 07 08:32:03 PM PDT 24 Jun 07 08:32:16 PM PDT 24 22298532 ps
T1057 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1633286582 Jun 07 08:31:43 PM PDT 24 Jun 07 08:31:59 PM PDT 24 160283012 ps
T1058 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4223053019 Jun 07 08:31:59 PM PDT 24 Jun 07 08:32:14 PM PDT 24 452273185 ps
T1059 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2939865059 Jun 07 08:31:48 PM PDT 24 Jun 07 08:32:26 PM PDT 24 948052237 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4098778832 Jun 07 08:31:48 PM PDT 24 Jun 07 08:32:06 PM PDT 24 208662685 ps
T1061 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3554966265 Jun 07 08:31:57 PM PDT 24 Jun 07 08:32:16 PM PDT 24 1275068233 ps
T1062 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2137901182 Jun 07 08:31:54 PM PDT 24 Jun 07 08:32:26 PM PDT 24 570880597 ps
T1063 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1302554452 Jun 07 08:32:09 PM PDT 24 Jun 07 08:32:21 PM PDT 24 48921115 ps
T1064 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1543939011 Jun 07 08:31:59 PM PDT 24 Jun 07 08:32:32 PM PDT 24 3327752859 ps
T1065 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1121613865 Jun 07 08:31:58 PM PDT 24 Jun 07 08:32:15 PM PDT 24 85862126 ps
T1066 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2551697984 Jun 07 08:31:57 PM PDT 24 Jun 07 08:32:25 PM PDT 24 2540383661 ps
T1067 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1445309020 Jun 07 08:32:24 PM PDT 24 Jun 07 08:32:33 PM PDT 24 301506203 ps
T1068 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4125057978 Jun 07 08:32:05 PM PDT 24 Jun 07 08:32:17 PM PDT 24 11772571 ps
T1069 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3522287432 Jun 07 08:31:57 PM PDT 24 Jun 07 08:32:13 PM PDT 24 265459458 ps
T1070 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.284437172 Jun 07 08:31:49 PM PDT 24 Jun 07 08:32:04 PM PDT 24 43519485 ps
T1071 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1338535466 Jun 07 08:32:04 PM PDT 24 Jun 07 08:32:18 PM PDT 24 88669837 ps
T1072 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1315956069 Jun 07 08:32:04 PM PDT 24 Jun 07 08:32:17 PM PDT 24 99638306 ps
T1073 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2175610448 Jun 07 08:31:47 PM PDT 24 Jun 07 08:32:35 PM PDT 24 3079181521 ps
T1074 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4092980288 Jun 07 08:32:03 PM PDT 24 Jun 07 08:32:16 PM PDT 24 12347936 ps
T1075 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.618440519 Jun 07 08:32:15 PM PDT 24 Jun 07 08:32:25 PM PDT 24 28055254 ps
T1076 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1439763038 Jun 07 08:32:09 PM PDT 24 Jun 07 08:32:20 PM PDT 24 72656833 ps
T1077 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.485239013 Jun 07 08:31:59 PM PDT 24 Jun 07 08:32:13 PM PDT 24 30322906 ps
T1078 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1378527032 Jun 07 08:31:59 PM PDT 24 Jun 07 08:32:24 PM PDT 24 624875576 ps
T1079 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1711024841 Jun 07 08:31:58 PM PDT 24 Jun 07 08:32:15 PM PDT 24 136176357 ps
T1080 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4238935642 Jun 07 08:32:09 PM PDT 24 Jun 07 08:32:23 PM PDT 24 41141552 ps
T1081 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1877648390 Jun 07 08:31:47 PM PDT 24 Jun 07 08:32:02 PM PDT 24 14998925 ps
T1082 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2119831005 Jun 07 08:32:08 PM PDT 24 Jun 07 08:32:21 PM PDT 24 94134980 ps
T1083 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2341106158 Jun 07 08:31:56 PM PDT 24 Jun 07 08:32:23 PM PDT 24 407372704 ps
T1084 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1146291287 Jun 07 08:32:07 PM PDT 24 Jun 07 08:32:19 PM PDT 24 20886125 ps
T1085 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.182611908 Jun 07 08:32:06 PM PDT 24 Jun 07 08:32:18 PM PDT 24 35485517 ps
T1086 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2694025684 Jun 07 08:31:57 PM PDT 24 Jun 07 08:32:11 PM PDT 24 317248536 ps
T1087 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4075642967 Jun 07 08:31:55 PM PDT 24 Jun 07 08:32:12 PM PDT 24 227178458 ps
T1088 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1799320202 Jun 07 08:31:52 PM PDT 24 Jun 07 08:32:08 PM PDT 24 221605526 ps
T1089 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4089681197 Jun 07 08:31:57 PM PDT 24 Jun 07 08:32:14 PM PDT 24 64149754 ps
T1090 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4095463457 Jun 07 08:31:50 PM PDT 24 Jun 07 08:32:06 PM PDT 24 16758383 ps
T1091 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.366136283 Jun 07 08:31:58 PM PDT 24 Jun 07 08:32:11 PM PDT 24 22485615 ps
T1092 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.258119838 Jun 07 08:32:13 PM PDT 24 Jun 07 08:32:23 PM PDT 24 19959170 ps
T1093 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.347197053 Jun 07 08:32:01 PM PDT 24 Jun 07 08:32:16 PM PDT 24 553952651 ps
T1094 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4134488014 Jun 07 08:32:23 PM PDT 24 Jun 07 08:32:31 PM PDT 24 20114032 ps
T1095 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4015697448 Jun 07 08:32:04 PM PDT 24 Jun 07 08:32:17 PM PDT 24 109310339 ps
T1096 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2463851895 Jun 07 08:31:40 PM PDT 24 Jun 07 08:31:52 PM PDT 24 21702992 ps
T1097 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2297643093 Jun 07 08:31:41 PM PDT 24 Jun 07 08:32:10 PM PDT 24 282051596 ps
T1098 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1585740020 Jun 07 08:31:39 PM PDT 24 Jun 07 08:31:51 PM PDT 24 14783756 ps
T1099 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3201857057 Jun 07 08:32:12 PM PDT 24 Jun 07 08:32:22 PM PDT 24 100339439 ps
T1100 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1792327096 Jun 07 08:31:50 PM PDT 24 Jun 07 08:32:06 PM PDT 24 43666685 ps
T1101 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3320625742 Jun 07 08:31:43 PM PDT 24 Jun 07 08:32:00 PM PDT 24 121831896 ps

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2233213523
Short name T6
Test name
Test status
Simulation time 450667075 ps
CPU time 7.1 seconds
Started Jun 07 08:10:41 PM PDT 24
Finished Jun 07 08:10:52 PM PDT 24
Peak memory 222076 kb
Host smart-4dd092ac-0718-4613-a6da-a19949e9b37a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2233213523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2233213523
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.110104941
Short name T31
Test name
Test status
Simulation time 35984896266 ps
CPU time 205.7 seconds
Started Jun 07 08:09:15 PM PDT 24
Finished Jun 07 08:12:47 PM PDT 24
Peak memory 268388 kb
Host smart-7b49b9d1-2d85-49fa-a553-5a0376b82d92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110104941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.110104941
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3633419213
Short name T21
Test name
Test status
Simulation time 13434758202 ps
CPU time 134.85 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:13:40 PM PDT 24
Peak memory 249056 kb
Host smart-7a75eac8-62ac-43cd-87be-b56e4491e622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633419213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3633419213
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2926819134
Short name T38
Test name
Test status
Simulation time 27327391326 ps
CPU time 292.59 seconds
Started Jun 07 08:11:32 PM PDT 24
Finished Jun 07 08:16:26 PM PDT 24
Peak memory 264428 kb
Host smart-1367680e-b7ff-4f3f-9869-9880d03a162c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926819134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2926819134
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1260413886
Short name T98
Test name
Test status
Simulation time 684007555 ps
CPU time 8.43 seconds
Started Jun 07 08:31:54 PM PDT 24
Finished Jun 07 08:32:16 PM PDT 24
Peak memory 216252 kb
Host smart-3d2adb16-c5c9-4504-944e-2507e311c0c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260413886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1260413886
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1217513570
Short name T14
Test name
Test status
Simulation time 24983009960 ps
CPU time 109.19 seconds
Started Jun 07 08:11:10 PM PDT 24
Finished Jun 07 08:13:01 PM PDT 24
Peak memory 254144 kb
Host smart-814d4123-3d84-42a2-b33b-d0eda59ff5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217513570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1217513570
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3999073142
Short name T168
Test name
Test status
Simulation time 50875689734 ps
CPU time 553.59 seconds
Started Jun 07 08:09:47 PM PDT 24
Finished Jun 07 08:19:03 PM PDT 24
Peak memory 272444 kb
Host smart-af802d9b-3bc7-4cc8-933e-ba4cfedec30b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999073142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3999073142
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3575260267
Short name T72
Test name
Test status
Simulation time 30644320 ps
CPU time 0.75 seconds
Started Jun 07 08:09:03 PM PDT 24
Finished Jun 07 08:09:07 PM PDT 24
Peak memory 215956 kb
Host smart-5d3e1837-cfac-44b2-8512-e0485656190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575260267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3575260267
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1723488725
Short name T153
Test name
Test status
Simulation time 87703252593 ps
CPU time 452.36 seconds
Started Jun 07 08:11:08 PM PDT 24
Finished Jun 07 08:18:43 PM PDT 24
Peak memory 273044 kb
Host smart-6e5561ef-8630-43a6-8a38-406064703986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723488725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1723488725
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3399173961
Short name T84
Test name
Test status
Simulation time 13380335558 ps
CPU time 219.44 seconds
Started Jun 07 08:11:29 PM PDT 24
Finished Jun 07 08:15:09 PM PDT 24
Peak memory 272932 kb
Host smart-0853c545-f5c3-4cc8-8be9-b0fa001cda92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399173961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3399173961
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.241689351
Short name T94
Test name
Test status
Simulation time 65916748 ps
CPU time 4.2 seconds
Started Jun 07 08:31:42 PM PDT 24
Finished Jun 07 08:31:59 PM PDT 24
Peak memory 215876 kb
Host smart-3439c317-2340-41b4-930d-71251ab46a46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241689351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.241689351
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4238813539
Short name T2
Test name
Test status
Simulation time 40082811867 ps
CPU time 127.06 seconds
Started Jun 07 08:09:10 PM PDT 24
Finished Jun 07 08:11:19 PM PDT 24
Peak memory 224360 kb
Host smart-8d5b59ca-5da2-40e1-9c24-3391c8cac815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238813539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4238813539
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2807807266
Short name T70
Test name
Test status
Simulation time 111268628 ps
CPU time 0.97 seconds
Started Jun 07 08:09:16 PM PDT 24
Finished Jun 07 08:09:24 PM PDT 24
Peak memory 234012 kb
Host smart-ffb3b406-59e6-437f-960b-5235f271180f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807807266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2807807266
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1008820873
Short name T40
Test name
Test status
Simulation time 87700157548 ps
CPU time 790.86 seconds
Started Jun 07 08:10:58 PM PDT 24
Finished Jun 07 08:24:10 PM PDT 24
Peak memory 273388 kb
Host smart-4bc75200-823b-4bf7-951d-07da286ab91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008820873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1008820873
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1249466245
Short name T23
Test name
Test status
Simulation time 61929454217 ps
CPU time 247.25 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:13:25 PM PDT 24
Peak memory 255956 kb
Host smart-6ef988c8-dd01-4f89-80b1-1c04559cbaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249466245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1249466245
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3216950218
Short name T55
Test name
Test status
Simulation time 82404761580 ps
CPU time 881.44 seconds
Started Jun 07 08:11:28 PM PDT 24
Finished Jun 07 08:26:11 PM PDT 24
Peak memory 289868 kb
Host smart-77983dea-9565-41ff-8fbe-994ad2b1edf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216950218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3216950218
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2429800211
Short name T156
Test name
Test status
Simulation time 97929528500 ps
CPU time 116.96 seconds
Started Jun 07 08:10:09 PM PDT 24
Finished Jun 07 08:12:09 PM PDT 24
Peak memory 255212 kb
Host smart-4d62782a-c97b-459d-a351-66d0d4322f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429800211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2429800211
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2507938518
Short name T113
Test name
Test status
Simulation time 5945648057 ps
CPU time 23.46 seconds
Started Jun 07 08:31:43 PM PDT 24
Finished Jun 07 08:32:20 PM PDT 24
Peak memory 215840 kb
Host smart-5c1bd414-d553-403d-a663-d7045d02225d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507938518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2507938518
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.646460089
Short name T232
Test name
Test status
Simulation time 15210250779 ps
CPU time 149.28 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:11:56 PM PDT 24
Peak memory 253252 kb
Host smart-e9402d83-5e59-4399-89c6-ecf9dd645131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646460089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.646460089
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.4068267704
Short name T28
Test name
Test status
Simulation time 29469284 ps
CPU time 1.05 seconds
Started Jun 07 08:09:19 PM PDT 24
Finished Jun 07 08:09:27 PM PDT 24
Peak memory 217628 kb
Host smart-9c0b4ff1-be6a-4607-bce1-3d26e6cdeb0f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068267704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.4068267704
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.402864409
Short name T218
Test name
Test status
Simulation time 227922106439 ps
CPU time 293.79 seconds
Started Jun 07 08:09:09 PM PDT 24
Finished Jun 07 08:14:04 PM PDT 24
Peak memory 249084 kb
Host smart-9ba8a12c-7097-42e7-922c-ac0c5bfb915f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402864409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.402864409
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.692317831
Short name T199
Test name
Test status
Simulation time 16611452127 ps
CPU time 98.76 seconds
Started Jun 07 08:09:18 PM PDT 24
Finished Jun 07 08:11:04 PM PDT 24
Peak memory 265032 kb
Host smart-1e472509-14a8-40f6-81df-008a9d71d59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692317831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.692317831
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2258258278
Short name T83
Test name
Test status
Simulation time 46168464083 ps
CPU time 215.03 seconds
Started Jun 07 08:09:21 PM PDT 24
Finished Jun 07 08:13:03 PM PDT 24
Peak memory 265388 kb
Host smart-12f7d61a-fdb5-44e4-8777-1c658b1e6bcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258258278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2258258278
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1349033503
Short name T236
Test name
Test status
Simulation time 4049416092 ps
CPU time 22 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:33 PM PDT 24
Peak memory 216284 kb
Host smart-14d2a1c2-0b73-463a-804e-84b26508bfbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349033503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1349033503
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3463913364
Short name T215
Test name
Test status
Simulation time 22798091624 ps
CPU time 101.77 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:11:02 PM PDT 24
Peak memory 267428 kb
Host smart-5cb7bf75-d0f8-45bf-bb2b-5e1ea8ca8eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463913364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3463913364
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1972486219
Short name T89
Test name
Test status
Simulation time 124760533 ps
CPU time 7.28 seconds
Started Jun 07 08:10:10 PM PDT 24
Finished Jun 07 08:10:21 PM PDT 24
Peak memory 232572 kb
Host smart-66dfd717-d82c-48a7-92e3-3ec4e07695bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972486219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1972486219
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3962594981
Short name T207
Test name
Test status
Simulation time 63205355222 ps
CPU time 163.1 seconds
Started Jun 07 08:11:03 PM PDT 24
Finished Jun 07 08:13:49 PM PDT 24
Peak memory 250508 kb
Host smart-b0faa520-a198-44bb-8169-b59f2c0b654c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962594981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3962594981
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.876014855
Short name T303
Test name
Test status
Simulation time 11843793 ps
CPU time 0.71 seconds
Started Jun 07 08:09:30 PM PDT 24
Finished Jun 07 08:09:35 PM PDT 24
Peak memory 205172 kb
Host smart-77d47207-2a75-42e1-9d71-47ef4391f96e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876014855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.876014855
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4020072048
Short name T101
Test name
Test status
Simulation time 197249806 ps
CPU time 4.41 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:15 PM PDT 24
Peak memory 215908 kb
Host smart-aa465024-3174-4099-a77e-009d76279796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020072048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4020072048
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1531824016
Short name T202
Test name
Test status
Simulation time 17202104548 ps
CPU time 247.18 seconds
Started Jun 07 08:09:36 PM PDT 24
Finished Jun 07 08:13:45 PM PDT 24
Peak memory 273248 kb
Host smart-0b197a19-5d39-4e53-a070-403824f00a88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531824016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1531824016
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3885174438
Short name T58
Test name
Test status
Simulation time 91833136990 ps
CPU time 278.92 seconds
Started Jun 07 08:09:30 PM PDT 24
Finished Jun 07 08:14:13 PM PDT 24
Peak memory 263608 kb
Host smart-9f9e5653-dda6-4175-9888-9d46e6073c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885174438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3885174438
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3810772391
Short name T180
Test name
Test status
Simulation time 43958805183 ps
CPU time 425.57 seconds
Started Jun 07 08:10:21 PM PDT 24
Finished Jun 07 08:17:31 PM PDT 24
Peak memory 249060 kb
Host smart-6866d4d5-c510-4c85-a1c7-34b2ed459014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810772391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3810772391
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2798583385
Short name T290
Test name
Test status
Simulation time 206840058294 ps
CPU time 439.33 seconds
Started Jun 07 08:09:10 PM PDT 24
Finished Jun 07 08:16:31 PM PDT 24
Peak memory 264552 kb
Host smart-bd79bf7b-365f-4523-a370-b76cb62551a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798583385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2798583385
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1930679671
Short name T151
Test name
Test status
Simulation time 168158312156 ps
CPU time 362.25 seconds
Started Jun 07 08:11:30 PM PDT 24
Finished Jun 07 08:17:33 PM PDT 24
Peak memory 249120 kb
Host smart-a0f2b992-eb51-4f9b-af62-cbfbeea282c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930679671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1930679671
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1053110591
Short name T239
Test name
Test status
Simulation time 528858407 ps
CPU time 14.11 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:25 PM PDT 24
Peak memory 215812 kb
Host smart-45df8813-74e7-4701-909d-3bbc32021347
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053110591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1053110591
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1236738881
Short name T231
Test name
Test status
Simulation time 9186746579 ps
CPU time 79.94 seconds
Started Jun 07 08:09:28 PM PDT 24
Finished Jun 07 08:10:52 PM PDT 24
Peak memory 256712 kb
Host smart-1cefe35a-72d8-4cf9-a840-744e9885d275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236738881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1236738881
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2450770886
Short name T196
Test name
Test status
Simulation time 93344186573 ps
CPU time 247.19 seconds
Started Jun 07 08:09:55 PM PDT 24
Finished Jun 07 08:14:05 PM PDT 24
Peak memory 281676 kb
Host smart-133d9493-f979-4435-9ebe-f4210f523bdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450770886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2450770886
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3409460822
Short name T500
Test name
Test status
Simulation time 3750285949 ps
CPU time 20.42 seconds
Started Jun 07 08:10:13 PM PDT 24
Finished Jun 07 08:10:37 PM PDT 24
Peak memory 224380 kb
Host smart-76de1e03-edda-4267-a8e8-4454cffe7327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409460822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3409460822
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2366831678
Short name T211
Test name
Test status
Simulation time 11555507176 ps
CPU time 79 seconds
Started Jun 07 08:11:13 PM PDT 24
Finished Jun 07 08:12:35 PM PDT 24
Peak memory 256088 kb
Host smart-731e3f6a-efdb-4a9e-b685-b28b5aae6430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366831678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2366831678
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1722521170
Short name T44
Test name
Test status
Simulation time 151421788582 ps
CPU time 26.17 seconds
Started Jun 07 08:10:06 PM PDT 24
Finished Jun 07 08:10:36 PM PDT 24
Peak memory 224276 kb
Host smart-f60be3ac-7223-4f6d-88cf-34f60cc03ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722521170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1722521170
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3382379726
Short name T697
Test name
Test status
Simulation time 26333401578 ps
CPU time 199.75 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:12:35 PM PDT 24
Peak memory 264328 kb
Host smart-19ef7e4d-2aaa-4433-bb8e-8889711d90ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382379726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3382379726
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_intercept.130346978
Short name T251
Test name
Test status
Simulation time 558431917 ps
CPU time 7.96 seconds
Started Jun 07 08:09:02 PM PDT 24
Finished Jun 07 08:09:13 PM PDT 24
Peak memory 224308 kb
Host smart-77aef22a-2fe5-40e8-ac64-5f2cba03d8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130346978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.130346978
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2283183692
Short name T419
Test name
Test status
Simulation time 5493808839 ps
CPU time 19.51 seconds
Started Jun 07 08:09:15 PM PDT 24
Finished Jun 07 08:09:41 PM PDT 24
Peak memory 217196 kb
Host smart-46ebc8db-b461-4f8c-be26-0612061f8fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283183692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2283183692
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1087701786
Short name T853
Test name
Test status
Simulation time 553804889 ps
CPU time 5.69 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:20 PM PDT 24
Peak memory 224260 kb
Host smart-cfadff67-7cc6-468e-b97d-c5d049b145c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087701786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1087701786
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2442154904
Short name T183
Test name
Test status
Simulation time 200581630 ps
CPU time 5.18 seconds
Started Jun 07 08:09:21 PM PDT 24
Finished Jun 07 08:09:33 PM PDT 24
Peak memory 232452 kb
Host smart-7b87d8b9-5d6a-401d-b35d-1a0287689133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442154904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2442154904
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2645645117
Short name T209
Test name
Test status
Simulation time 29409005515 ps
CPU time 185.04 seconds
Started Jun 07 08:09:27 PM PDT 24
Finished Jun 07 08:12:37 PM PDT 24
Peak memory 249040 kb
Host smart-255a29f5-7b36-4a7d-8c62-cf6fc3bcf519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645645117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2645645117
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.131301950
Short name T179
Test name
Test status
Simulation time 899599877 ps
CPU time 20.36 seconds
Started Jun 07 08:09:46 PM PDT 24
Finished Jun 07 08:10:09 PM PDT 24
Peak memory 233764 kb
Host smart-dcd4f377-28fa-4380-ae2e-ca6c058bcfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131301950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.131301950
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2146534127
Short name T160
Test name
Test status
Simulation time 8735397900 ps
CPU time 68.44 seconds
Started Jun 07 08:09:46 PM PDT 24
Finished Jun 07 08:10:56 PM PDT 24
Peak memory 256360 kb
Host smart-b457136c-65e4-4f26-aa4d-99e9a30bb66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146534127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2146534127
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1915886925
Short name T278
Test name
Test status
Simulation time 464828437 ps
CPU time 13.81 seconds
Started Jun 07 08:10:01 PM PDT 24
Finished Jun 07 08:10:17 PM PDT 24
Peak memory 233464 kb
Host smart-70765e0b-3717-476d-87d4-e2e6677fe835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915886925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1915886925
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1055955390
Short name T212
Test name
Test status
Simulation time 162691266147 ps
CPU time 292.2 seconds
Started Jun 07 08:10:22 PM PDT 24
Finished Jun 07 08:15:19 PM PDT 24
Peak memory 265352 kb
Host smart-542bf960-e6ed-4db2-bc7b-386b600b9106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055955390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1055955390
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1006513334
Short name T226
Test name
Test status
Simulation time 38027612329 ps
CPU time 170.95 seconds
Started Jun 07 08:10:39 PM PDT 24
Finished Jun 07 08:13:34 PM PDT 24
Peak memory 265016 kb
Host smart-56846821-c18d-439f-8db1-5e04c6b320f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006513334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1006513334
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.279145300
Short name T193
Test name
Test status
Simulation time 63454989762 ps
CPU time 169.82 seconds
Started Jun 07 08:10:38 PM PDT 24
Finished Jun 07 08:13:32 PM PDT 24
Peak memory 255728 kb
Host smart-73f615bc-dc77-4e53-b059-d692945f27fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279145300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.279145300
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3591443908
Short name T197
Test name
Test status
Simulation time 81595588105 ps
CPU time 412.61 seconds
Started Jun 07 08:11:08 PM PDT 24
Finished Jun 07 08:18:03 PM PDT 24
Peak memory 249052 kb
Host smart-be41bf63-2598-44d6-bf71-8859c341eb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591443908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3591443908
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4227604129
Short name T144
Test name
Test status
Simulation time 61811152818 ps
CPU time 548.42 seconds
Started Jun 07 08:11:20 PM PDT 24
Finished Jun 07 08:20:31 PM PDT 24
Peak memory 252408 kb
Host smart-98c7a236-2630-45be-bf15-9d673021e814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227604129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4227604129
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2349834496
Short name T229
Test name
Test status
Simulation time 39947934502 ps
CPU time 130.07 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:13:35 PM PDT 24
Peak memory 253936 kb
Host smart-6f1fcc18-953f-44be-8239-f95ad548e196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349834496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2349834496
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.886703716
Short name T96
Test name
Test status
Simulation time 330212430 ps
CPU time 2.25 seconds
Started Jun 07 08:31:56 PM PDT 24
Finished Jun 07 08:32:11 PM PDT 24
Peak memory 215848 kb
Host smart-525a35d9-90f9-497a-83de-b4b59c7ac063
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886703716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.886703716
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1100485408
Short name T86
Test name
Test status
Simulation time 58543665 ps
CPU time 0.88 seconds
Started Jun 07 08:31:45 PM PDT 24
Finished Jun 07 08:31:59 PM PDT 24
Peak memory 207176 kb
Host smart-25c05fc8-9681-4eb2-968f-8dbd6f4b2a63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100485408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1100485408
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1097390229
Short name T87
Test name
Test status
Simulation time 17900649 ps
CPU time 1.12 seconds
Started Jun 07 08:31:40 PM PDT 24
Finished Jun 07 08:31:53 PM PDT 24
Peak memory 207628 kb
Host smart-f91ff39d-c17b-41d6-9757-f50ee377677c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097390229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1097390229
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1450293594
Short name T1040
Test name
Test status
Simulation time 635763936 ps
CPU time 16.07 seconds
Started Jun 07 08:31:42 PM PDT 24
Finished Jun 07 08:32:12 PM PDT 24
Peak memory 207572 kb
Host smart-db9a80aa-7f59-45fb-862a-e90c492199e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450293594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1450293594
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2175610448
Short name T1073
Test name
Test status
Simulation time 3079181521 ps
CPU time 33.13 seconds
Started Jun 07 08:31:47 PM PDT 24
Finished Jun 07 08:32:35 PM PDT 24
Peak memory 207544 kb
Host smart-5e2df22a-34b1-4215-911b-f4e0be176b6a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175610448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2175610448
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3457447844
Short name T1014
Test name
Test status
Simulation time 439451316 ps
CPU time 2.81 seconds
Started Jun 07 08:31:46 PM PDT 24
Finished Jun 07 08:32:03 PM PDT 24
Peak memory 217496 kb
Host smart-973fcd15-5839-4f98-850f-f72efd47f53d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457447844 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3457447844
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1916966371
Short name T138
Test name
Test status
Simulation time 92437844 ps
CPU time 2.27 seconds
Started Jun 07 08:31:36 PM PDT 24
Finished Jun 07 08:31:50 PM PDT 24
Peak memory 215720 kb
Host smart-cbf41150-c5df-492f-b2a4-de1ca5a8383f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916966371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
916966371
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1585740020
Short name T1098
Test name
Test status
Simulation time 14783756 ps
CPU time 0.76 seconds
Started Jun 07 08:31:39 PM PDT 24
Finished Jun 07 08:31:51 PM PDT 24
Peak memory 204132 kb
Host smart-fdcd2729-0bcd-4e49-9adb-1f451785cf80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585740020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
585740020
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1511174473
Short name T1028
Test name
Test status
Simulation time 298894983 ps
CPU time 2.22 seconds
Started Jun 07 08:31:41 PM PDT 24
Finished Jun 07 08:31:56 PM PDT 24
Peak memory 215880 kb
Host smart-1ef5d89e-2aff-4d2c-b179-e47bc229ab50
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511174473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1511174473
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1557074184
Short name T1009
Test name
Test status
Simulation time 27529351 ps
CPU time 0.65 seconds
Started Jun 07 08:31:43 PM PDT 24
Finished Jun 07 08:31:58 PM PDT 24
Peak memory 204084 kb
Host smart-4b369dda-815b-4283-96b9-e9186ba51d4c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557074184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1557074184
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.847114205
Short name T999
Test name
Test status
Simulation time 52126635 ps
CPU time 1.69 seconds
Started Jun 07 08:31:46 PM PDT 24
Finished Jun 07 08:32:02 PM PDT 24
Peak memory 215840 kb
Host smart-fc5666fd-8130-474d-a7ba-57a34110816f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847114205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.847114205
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3320625742
Short name T1101
Test name
Test status
Simulation time 121831896 ps
CPU time 3.49 seconds
Started Jun 07 08:31:43 PM PDT 24
Finished Jun 07 08:32:00 PM PDT 24
Peak memory 216092 kb
Host smart-830a9038-e90e-4ed7-92c5-49c9510fdd18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320625742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
320625742
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2385236224
Short name T95
Test name
Test status
Simulation time 567888050 ps
CPU time 7.52 seconds
Started Jun 07 08:31:43 PM PDT 24
Finished Jun 07 08:32:05 PM PDT 24
Peak memory 215792 kb
Host smart-71b2b4d3-7152-436f-a341-2aa38274bed6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385236224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2385236224
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1013223661
Short name T1039
Test name
Test status
Simulation time 993620336 ps
CPU time 12.11 seconds
Started Jun 07 08:31:43 PM PDT 24
Finished Jun 07 08:32:09 PM PDT 24
Peak memory 215660 kb
Host smart-fd585cc5-cb44-4a5c-9d3c-c2b62cdb6bf2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013223661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1013223661
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1633286582
Short name T1057
Test name
Test status
Simulation time 160283012 ps
CPU time 1.49 seconds
Started Jun 07 08:31:43 PM PDT 24
Finished Jun 07 08:31:59 PM PDT 24
Peak memory 216816 kb
Host smart-38d287b1-265b-4171-a531-10b9f97f3f4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633286582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1633286582
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3297546600
Short name T106
Test name
Test status
Simulation time 56513753 ps
CPU time 1.7 seconds
Started Jun 07 08:31:41 PM PDT 24
Finished Jun 07 08:31:55 PM PDT 24
Peak memory 215948 kb
Host smart-7de5fc25-be63-461c-b994-57afe2ef6490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297546600 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3297546600
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.242468306
Short name T116
Test name
Test status
Simulation time 438942405 ps
CPU time 2.64 seconds
Started Jun 07 08:31:43 PM PDT 24
Finished Jun 07 08:31:59 PM PDT 24
Peak memory 215784 kb
Host smart-0df0040d-053c-451c-aa4f-7e0266b5d014
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242468306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.242468306
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2463851895
Short name T1096
Test name
Test status
Simulation time 21702992 ps
CPU time 0.69 seconds
Started Jun 07 08:31:40 PM PDT 24
Finished Jun 07 08:31:52 PM PDT 24
Peak memory 204404 kb
Host smart-6c985d76-baae-433e-91e1-6ac6f8b91d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463851895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
463851895
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1597054685
Short name T121
Test name
Test status
Simulation time 62445873 ps
CPU time 2.22 seconds
Started Jun 07 08:31:40 PM PDT 24
Finished Jun 07 08:31:54 PM PDT 24
Peak memory 215904 kb
Host smart-4268e2c7-1e14-4f0f-a414-412733e06e4a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597054685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1597054685
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2821694959
Short name T1002
Test name
Test status
Simulation time 34752310 ps
CPU time 0.66 seconds
Started Jun 07 08:31:41 PM PDT 24
Finished Jun 07 08:31:55 PM PDT 24
Peak memory 204056 kb
Host smart-d59e63c1-5cd2-4053-ad11-11a021a539c5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821694959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2821694959
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1741084866
Short name T985
Test name
Test status
Simulation time 106496938 ps
CPU time 1.64 seconds
Started Jun 07 08:31:43 PM PDT 24
Finished Jun 07 08:31:59 PM PDT 24
Peak memory 215748 kb
Host smart-4195a00a-558b-4527-8dbc-eaf454681f0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741084866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1741084866
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1682796074
Short name T111
Test name
Test status
Simulation time 781634079 ps
CPU time 12.15 seconds
Started Jun 07 08:31:41 PM PDT 24
Finished Jun 07 08:32:06 PM PDT 24
Peak memory 215884 kb
Host smart-4cbf907e-e35c-4b14-a077-b7c98fc1af3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682796074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1682796074
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3017500977
Short name T1051
Test name
Test status
Simulation time 125158909 ps
CPU time 3.57 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:14 PM PDT 24
Peak memory 217640 kb
Host smart-54a69b7e-133f-4353-be03-0efe366f03e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017500977 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3017500977
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2713707522
Short name T989
Test name
Test status
Simulation time 325364059 ps
CPU time 2.05 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:18 PM PDT 24
Peak memory 207636 kb
Host smart-bc9cf89c-89ee-454d-b05c-847a09ea943c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713707522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2713707522
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1104236704
Short name T987
Test name
Test status
Simulation time 17528214 ps
CPU time 0.75 seconds
Started Jun 07 08:31:57 PM PDT 24
Finished Jun 07 08:32:11 PM PDT 24
Peak memory 204152 kb
Host smart-d419445f-e532-4dd4-829d-ce6f796b137f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104236704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1104236704
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4223053019
Short name T1058
Test name
Test status
Simulation time 452273185 ps
CPU time 2.59 seconds
Started Jun 07 08:31:59 PM PDT 24
Finished Jun 07 08:32:14 PM PDT 24
Peak memory 207624 kb
Host smart-f16c3f90-706b-4d24-8537-8924d793ec5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223053019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4223053019
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.435523267
Short name T1011
Test name
Test status
Simulation time 48500243 ps
CPU time 1.77 seconds
Started Jun 07 08:32:04 PM PDT 24
Finished Jun 07 08:32:18 PM PDT 24
Peak memory 215908 kb
Host smart-659ca22b-df61-4b28-b0b4-ba01e0c62703
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435523267 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.435523267
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1941283262
Short name T998
Test name
Test status
Simulation time 22661877 ps
CPU time 1.25 seconds
Started Jun 07 08:31:57 PM PDT 24
Finished Jun 07 08:32:11 PM PDT 24
Peak memory 207552 kb
Host smart-3723186f-3570-40ae-8b0d-8d4dfa2c0a66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941283262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1941283262
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1913817276
Short name T1016
Test name
Test status
Simulation time 63765645 ps
CPU time 0.69 seconds
Started Jun 07 08:31:56 PM PDT 24
Finished Jun 07 08:32:10 PM PDT 24
Peak memory 204056 kb
Host smart-c299e4b3-01e7-446c-9749-2ea2543a6f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913817276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1913817276
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4089681197
Short name T1089
Test name
Test status
Simulation time 64149754 ps
CPU time 3.91 seconds
Started Jun 07 08:31:57 PM PDT 24
Finished Jun 07 08:32:14 PM PDT 24
Peak memory 215848 kb
Host smart-9f57f33f-db4a-4d88-b9d5-3ef9131cfcd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089681197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.4089681197
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2694025684
Short name T1086
Test name
Test status
Simulation time 317248536 ps
CPU time 1.5 seconds
Started Jun 07 08:31:57 PM PDT 24
Finished Jun 07 08:32:11 PM PDT 24
Peak memory 216140 kb
Host smart-8009fb66-4d72-41ef-964a-6bcd3f7dd481
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694025684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2694025684
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3744051996
Short name T97
Test name
Test status
Simulation time 102794352 ps
CPU time 6.81 seconds
Started Jun 07 08:31:56 PM PDT 24
Finished Jun 07 08:32:16 PM PDT 24
Peak memory 215804 kb
Host smart-3d46fd1b-c270-4d8b-a352-55277db97ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744051996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3744051996
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4238935642
Short name T1080
Test name
Test status
Simulation time 41141552 ps
CPU time 2.74 seconds
Started Jun 07 08:32:09 PM PDT 24
Finished Jun 07 08:32:23 PM PDT 24
Peak memory 218304 kb
Host smart-7cb8c9e2-8936-4574-abd7-f940e0861af8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238935642 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4238935642
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.347197053
Short name T1093
Test name
Test status
Simulation time 553952651 ps
CPU time 2.18 seconds
Started Jun 07 08:32:01 PM PDT 24
Finished Jun 07 08:32:16 PM PDT 24
Peak memory 215764 kb
Host smart-83866b43-ff45-41a3-9e34-b175158dd662
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347197053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.347197053
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4137544217
Short name T993
Test name
Test status
Simulation time 19771179 ps
CPU time 0.7 seconds
Started Jun 07 08:32:02 PM PDT 24
Finished Jun 07 08:32:15 PM PDT 24
Peak memory 204400 kb
Host smart-30521bde-a59d-4db9-8afa-67addf7b7d3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137544217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
4137544217
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3522287432
Short name T1069
Test name
Test status
Simulation time 265459458 ps
CPU time 2.97 seconds
Started Jun 07 08:31:57 PM PDT 24
Finished Jun 07 08:32:13 PM PDT 24
Peak memory 215856 kb
Host smart-b405387c-9dc5-454d-ab76-9fa132baa4e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522287432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3522287432
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1711024841
Short name T1079
Test name
Test status
Simulation time 136176357 ps
CPU time 3.83 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:15 PM PDT 24
Peak memory 216996 kb
Host smart-5e0617a6-8d87-4faf-a655-405e5fcda0b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711024841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1711024841
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3056785486
Short name T238
Test name
Test status
Simulation time 281451342 ps
CPU time 7.98 seconds
Started Jun 07 08:31:56 PM PDT 24
Finished Jun 07 08:32:17 PM PDT 24
Peak memory 215876 kb
Host smart-7c095aa5-dad5-4178-9b6b-0ee4f97bf7bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056785486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3056785486
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2304624111
Short name T1008
Test name
Test status
Simulation time 338236736 ps
CPU time 2.49 seconds
Started Jun 07 08:32:03 PM PDT 24
Finished Jun 07 08:32:17 PM PDT 24
Peak memory 216928 kb
Host smart-219a3217-720f-4cd3-8d36-d2795964d02a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304624111 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2304624111
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.485239013
Short name T1077
Test name
Test status
Simulation time 30322906 ps
CPU time 1.11 seconds
Started Jun 07 08:31:59 PM PDT 24
Finished Jun 07 08:32:13 PM PDT 24
Peak memory 207620 kb
Host smart-408d9d7e-b78d-409c-9062-ee51dd9beccb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485239013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.485239013
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1291576526
Short name T979
Test name
Test status
Simulation time 57436410 ps
CPU time 0.73 seconds
Started Jun 07 08:32:04 PM PDT 24
Finished Jun 07 08:32:17 PM PDT 24
Peak memory 204120 kb
Host smart-825cc205-db03-4bb2-a27a-9d3f10ae9d41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291576526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1291576526
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3402436619
Short name T991
Test name
Test status
Simulation time 95973387 ps
CPU time 1.78 seconds
Started Jun 07 08:31:56 PM PDT 24
Finished Jun 07 08:32:11 PM PDT 24
Peak memory 215828 kb
Host smart-58129110-cdb1-4caf-9c68-baaaf06a2565
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402436619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3402436619
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2260502960
Short name T99
Test name
Test status
Simulation time 535775016 ps
CPU time 3.36 seconds
Started Jun 07 08:31:56 PM PDT 24
Finished Jun 07 08:32:13 PM PDT 24
Peak memory 215996 kb
Host smart-30103495-cb7b-421d-9fdb-0caa9c4f919f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260502960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2260502960
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2010406469
Short name T1010
Test name
Test status
Simulation time 177274400 ps
CPU time 1.65 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:13 PM PDT 24
Peak memory 215904 kb
Host smart-a9c88e6d-a088-4c3a-8b9a-7e8cab7bd9ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010406469 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2010406469
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3063910934
Short name T1023
Test name
Test status
Simulation time 97836221 ps
CPU time 2.81 seconds
Started Jun 07 08:31:56 PM PDT 24
Finished Jun 07 08:32:12 PM PDT 24
Peak memory 215820 kb
Host smart-02632ef4-75ec-4443-a8fa-fbbe5c991739
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063910934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3063910934
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.991118102
Short name T988
Test name
Test status
Simulation time 25442312 ps
CPU time 0.73 seconds
Started Jun 07 08:32:00 PM PDT 24
Finished Jun 07 08:32:13 PM PDT 24
Peak memory 204060 kb
Host smart-cb78b9a0-e092-42e0-90ba-545b9d0dc8c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991118102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.991118102
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3779114401
Short name T1018
Test name
Test status
Simulation time 231502916 ps
CPU time 4.58 seconds
Started Jun 07 08:32:00 PM PDT 24
Finished Jun 07 08:32:17 PM PDT 24
Peak memory 215832 kb
Host smart-66db00f9-0b30-46aa-99cc-1b42f6f5244a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779114401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3779114401
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1172499137
Short name T235
Test name
Test status
Simulation time 180572143 ps
CPU time 2.94 seconds
Started Jun 07 08:31:56 PM PDT 24
Finished Jun 07 08:32:13 PM PDT 24
Peak memory 216016 kb
Host smart-c3af40bb-497d-4de6-b76c-6166a3869969
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172499137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1172499137
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1543939011
Short name T1064
Test name
Test status
Simulation time 3327752859 ps
CPU time 20.54 seconds
Started Jun 07 08:31:59 PM PDT 24
Finished Jun 07 08:32:32 PM PDT 24
Peak memory 215928 kb
Host smart-26cde7fd-72cd-4fbc-a275-ed3299af0b88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543939011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1543939011
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3519707188
Short name T1021
Test name
Test status
Simulation time 441695180 ps
CPU time 3.99 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:14 PM PDT 24
Peak memory 218124 kb
Host smart-f742e859-824a-4509-84ed-fa1dade463b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519707188 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3519707188
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2964989569
Short name T122
Test name
Test status
Simulation time 61509467 ps
CPU time 1.68 seconds
Started Jun 07 08:32:04 PM PDT 24
Finished Jun 07 08:32:17 PM PDT 24
Peak memory 215792 kb
Host smart-7635d91d-8760-4b7d-b39d-0101a29bca8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964989569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2964989569
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2696044102
Short name T1007
Test name
Test status
Simulation time 19236998 ps
CPU time 0.72 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:11 PM PDT 24
Peak memory 204012 kb
Host smart-4ffeadbb-8a49-4f31-959e-b60f3f29224d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696044102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2696044102
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3348906993
Short name T1003
Test name
Test status
Simulation time 41552124 ps
CPU time 2.65 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:14 PM PDT 24
Peak memory 215844 kb
Host smart-feaaab4a-a297-4316-970e-e982129aa50d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348906993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3348906993
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1378527032
Short name T1078
Test name
Test status
Simulation time 624875576 ps
CPU time 11.7 seconds
Started Jun 07 08:31:59 PM PDT 24
Finished Jun 07 08:32:24 PM PDT 24
Peak memory 215832 kb
Host smart-423cfff7-6a5d-4620-ac6a-0870f8e6fbff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378527032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1378527032
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1364552390
Short name T1032
Test name
Test status
Simulation time 548527900 ps
CPU time 3.78 seconds
Started Jun 07 08:31:59 PM PDT 24
Finished Jun 07 08:32:16 PM PDT 24
Peak memory 217892 kb
Host smart-9730e634-7454-4876-9bb4-ffdd8e68c54c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364552390 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1364552390
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2658415442
Short name T115
Test name
Test status
Simulation time 46367518 ps
CPU time 1.47 seconds
Started Jun 07 08:32:01 PM PDT 24
Finished Jun 07 08:32:15 PM PDT 24
Peak memory 215764 kb
Host smart-493ae27e-a936-41a3-8ee2-4a216e1cc771
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658415442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2658415442
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3252074470
Short name T1015
Test name
Test status
Simulation time 19747471 ps
CPU time 0.74 seconds
Started Jun 07 08:31:59 PM PDT 24
Finished Jun 07 08:32:13 PM PDT 24
Peak memory 204088 kb
Host smart-68085470-36c9-4738-914e-197094333996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252074470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3252074470
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.248996284
Short name T1050
Test name
Test status
Simulation time 44718199 ps
CPU time 2.84 seconds
Started Jun 07 08:32:03 PM PDT 24
Finished Jun 07 08:32:17 PM PDT 24
Peak memory 215836 kb
Host smart-040b3b13-b2e5-4d0a-b0a4-333cb653cf53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248996284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.248996284
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.110019769
Short name T1012
Test name
Test status
Simulation time 66709175 ps
CPU time 4.51 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:15 PM PDT 24
Peak memory 216016 kb
Host smart-0f3531b8-b5d0-4b33-9ec1-1401ae39ca01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110019769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.110019769
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2137901182
Short name T1062
Test name
Test status
Simulation time 570880597 ps
CPU time 18.16 seconds
Started Jun 07 08:31:54 PM PDT 24
Finished Jun 07 08:32:26 PM PDT 24
Peak memory 215896 kb
Host smart-2bc4156e-2c86-4383-b924-b8c34098e556
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137901182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2137901182
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3312065475
Short name T1029
Test name
Test status
Simulation time 107523742 ps
CPU time 3.79 seconds
Started Jun 07 08:32:02 PM PDT 24
Finished Jun 07 08:32:18 PM PDT 24
Peak memory 218820 kb
Host smart-58bdfe12-9cd1-4bab-ab95-0405482b883c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312065475 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3312065475
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3546036207
Short name T1026
Test name
Test status
Simulation time 60210834 ps
CPU time 1.87 seconds
Started Jun 07 08:32:01 PM PDT 24
Finished Jun 07 08:32:16 PM PDT 24
Peak memory 215728 kb
Host smart-e4dc0217-d98b-40ba-80b5-5e6d34a59eb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546036207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3546036207
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.492695557
Short name T1013
Test name
Test status
Simulation time 24819156 ps
CPU time 0.7 seconds
Started Jun 07 08:32:04 PM PDT 24
Finished Jun 07 08:32:20 PM PDT 24
Peak memory 204388 kb
Host smart-a60c6355-5eb2-4001-86c0-1a2efb5d797b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492695557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.492695557
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2412780731
Short name T1006
Test name
Test status
Simulation time 102133339 ps
CPU time 1.65 seconds
Started Jun 07 08:32:05 PM PDT 24
Finished Jun 07 08:32:18 PM PDT 24
Peak memory 215816 kb
Host smart-76623417-4d32-44d1-b881-150709469086
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412780731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2412780731
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3029272396
Short name T102
Test name
Test status
Simulation time 51402127 ps
CPU time 3.41 seconds
Started Jun 07 08:31:59 PM PDT 24
Finished Jun 07 08:32:16 PM PDT 24
Peak memory 215828 kb
Host smart-69c7bf43-455e-4022-9f94-9654a5bda07f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029272396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3029272396
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2699657826
Short name T237
Test name
Test status
Simulation time 391598403 ps
CPU time 11.73 seconds
Started Jun 07 08:32:01 PM PDT 24
Finished Jun 07 08:32:25 PM PDT 24
Peak memory 216116 kb
Host smart-1635fe5d-a275-4fdc-8845-0e0fd2267bce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699657826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2699657826
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2119831005
Short name T1082
Test name
Test status
Simulation time 94134980 ps
CPU time 1.63 seconds
Started Jun 07 08:32:08 PM PDT 24
Finished Jun 07 08:32:21 PM PDT 24
Peak memory 215908 kb
Host smart-030bd59c-59ab-4b70-a9de-e6bec485ba2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119831005 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2119831005
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2746542341
Short name T1044
Test name
Test status
Simulation time 230230934 ps
CPU time 1.95 seconds
Started Jun 07 08:32:14 PM PDT 24
Finished Jun 07 08:32:25 PM PDT 24
Peak memory 207620 kb
Host smart-a2ef95ac-af1e-4b8b-bd22-94a5575e19e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746542341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2746542341
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3055775008
Short name T1022
Test name
Test status
Simulation time 36020014 ps
CPU time 0.74 seconds
Started Jun 07 08:31:59 PM PDT 24
Finished Jun 07 08:32:13 PM PDT 24
Peak memory 204200 kb
Host smart-e43d3435-2e3c-46ba-ad37-ddce8b1f1481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055775008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3055775008
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4015697448
Short name T1095
Test name
Test status
Simulation time 109310339 ps
CPU time 1.81 seconds
Started Jun 07 08:32:04 PM PDT 24
Finished Jun 07 08:32:17 PM PDT 24
Peak memory 215764 kb
Host smart-b7bfd840-cdd8-41e0-9819-6187af18164b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015697448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4015697448
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2309979992
Short name T103
Test name
Test status
Simulation time 454862717 ps
CPU time 3.31 seconds
Started Jun 07 08:32:04 PM PDT 24
Finished Jun 07 08:32:19 PM PDT 24
Peak memory 215992 kb
Host smart-182983ff-cfbb-4d1d-8ea0-4a54f5b1f4a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309979992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2309979992
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3554966265
Short name T1061
Test name
Test status
Simulation time 1275068233 ps
CPU time 6.3 seconds
Started Jun 07 08:31:57 PM PDT 24
Finished Jun 07 08:32:16 PM PDT 24
Peak memory 216184 kb
Host smart-b178a5f0-7eac-40d9-94ab-5661f04669c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554966265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3554966265
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1338535466
Short name T1071
Test name
Test status
Simulation time 88669837 ps
CPU time 1.63 seconds
Started Jun 07 08:32:04 PM PDT 24
Finished Jun 07 08:32:18 PM PDT 24
Peak memory 215920 kb
Host smart-0dfb1a9b-46dd-40b1-9723-cc5d900608a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338535466 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1338535466
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2352045827
Short name T1005
Test name
Test status
Simulation time 106026429 ps
CPU time 1.97 seconds
Started Jun 07 08:32:08 PM PDT 24
Finished Jun 07 08:32:21 PM PDT 24
Peak memory 215812 kb
Host smart-37ef3abc-b334-4f18-ac8a-008ef77105e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352045827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2352045827
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1146291287
Short name T1084
Test name
Test status
Simulation time 20886125 ps
CPU time 0.78 seconds
Started Jun 07 08:32:07 PM PDT 24
Finished Jun 07 08:32:19 PM PDT 24
Peak memory 204124 kb
Host smart-3f819a08-c1dd-4652-9bbc-77188ab913f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146291287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1146291287
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1502995945
Short name T139
Test name
Test status
Simulation time 764910679 ps
CPU time 3.9 seconds
Started Jun 07 08:32:03 PM PDT 24
Finished Jun 07 08:32:19 PM PDT 24
Peak memory 215824 kb
Host smart-ca52f9ae-9505-4dac-aac8-4a0b236798fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502995945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1502995945
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1445309020
Short name T1067
Test name
Test status
Simulation time 301506203 ps
CPU time 2.83 seconds
Started Jun 07 08:32:24 PM PDT 24
Finished Jun 07 08:32:33 PM PDT 24
Peak memory 215980 kb
Host smart-2235a301-b297-45e0-b5cf-e586476f55f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445309020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1445309020
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3836284609
Short name T110
Test name
Test status
Simulation time 564816894 ps
CPU time 7.37 seconds
Started Jun 07 08:32:10 PM PDT 24
Finished Jun 07 08:32:28 PM PDT 24
Peak memory 215820 kb
Host smart-8f6addb3-6254-4b2b-9697-a94ff29f121a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836284609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3836284609
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3462627037
Short name T118
Test name
Test status
Simulation time 1072624130 ps
CPU time 22.58 seconds
Started Jun 07 08:31:40 PM PDT 24
Finished Jun 07 08:32:15 PM PDT 24
Peak memory 215836 kb
Host smart-ca231e32-2329-4b13-8f33-2f5bdb7b0e5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462627037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3462627037
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3895078063
Short name T117
Test name
Test status
Simulation time 16397354523 ps
CPU time 26.27 seconds
Started Jun 07 08:31:46 PM PDT 24
Finished Jun 07 08:32:26 PM PDT 24
Peak memory 215796 kb
Host smart-fc5bd1e3-5811-49a6-b9c5-3de9e00e41c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895078063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3895078063
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.622433439
Short name T1049
Test name
Test status
Simulation time 64845987 ps
CPU time 1.74 seconds
Started Jun 07 08:31:40 PM PDT 24
Finished Jun 07 08:31:54 PM PDT 24
Peak memory 215908 kb
Host smart-0e5d21ea-b7a3-4a2c-8099-07970657b934
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622433439 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.622433439
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1367180584
Short name T1025
Test name
Test status
Simulation time 25774252 ps
CPU time 1.66 seconds
Started Jun 07 08:31:45 PM PDT 24
Finished Jun 07 08:32:00 PM PDT 24
Peak memory 207584 kb
Host smart-d78a4a91-7ddd-415e-ac9a-8d4db4b5e446
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367180584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
367180584
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2998721179
Short name T1036
Test name
Test status
Simulation time 62351069 ps
CPU time 0.72 seconds
Started Jun 07 08:31:41 PM PDT 24
Finished Jun 07 08:31:56 PM PDT 24
Peak memory 204400 kb
Host smart-e26eaf08-6c8c-497c-8cd6-969f95c16793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998721179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
998721179
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4002274681
Short name T119
Test name
Test status
Simulation time 284063838 ps
CPU time 1.45 seconds
Started Jun 07 08:31:45 PM PDT 24
Finished Jun 07 08:31:59 PM PDT 24
Peak memory 215880 kb
Host smart-f7ca6764-8d7f-4c44-b23a-8fd1485d883d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002274681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.4002274681
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2518544516
Short name T1004
Test name
Test status
Simulation time 13314938 ps
CPU time 0.65 seconds
Started Jun 07 08:31:44 PM PDT 24
Finished Jun 07 08:31:59 PM PDT 24
Peak memory 204364 kb
Host smart-eb33ed83-fca5-4571-a9fd-e6933e60714d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518544516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2518544516
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2821470941
Short name T1024
Test name
Test status
Simulation time 917902825 ps
CPU time 4.14 seconds
Started Jun 07 08:31:41 PM PDT 24
Finished Jun 07 08:31:58 PM PDT 24
Peak memory 215860 kb
Host smart-4009ae90-5e89-426f-8cfe-281d66cfc6f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821470941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2821470941
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2738950981
Short name T234
Test name
Test status
Simulation time 111107057 ps
CPU time 2.73 seconds
Started Jun 07 08:31:50 PM PDT 24
Finished Jun 07 08:32:07 PM PDT 24
Peak memory 215940 kb
Host smart-29a1b70a-fa22-49e4-8a0b-febb82eb2fc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738950981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
738950981
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.747410937
Short name T107
Test name
Test status
Simulation time 1651761736 ps
CPU time 20.79 seconds
Started Jun 07 08:31:39 PM PDT 24
Finished Jun 07 08:32:12 PM PDT 24
Peak memory 217112 kb
Host smart-6d0b19d5-b64e-4298-a727-eaa035a1b0ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747410937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.747410937
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1302554452
Short name T1063
Test name
Test status
Simulation time 48921115 ps
CPU time 0.71 seconds
Started Jun 07 08:32:09 PM PDT 24
Finished Jun 07 08:32:21 PM PDT 24
Peak memory 204076 kb
Host smart-4f5d4680-5a4d-4f39-b085-2baa4469a147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302554452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1302554452
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.416705245
Short name T1052
Test name
Test status
Simulation time 46035969 ps
CPU time 0.76 seconds
Started Jun 07 08:32:15 PM PDT 24
Finished Jun 07 08:32:24 PM PDT 24
Peak memory 204424 kb
Host smart-1c97a2cc-bd5a-4a83-8d8d-8d6d05e57a8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416705245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.416705245
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1439763038
Short name T1076
Test name
Test status
Simulation time 72656833 ps
CPU time 0.81 seconds
Started Jun 07 08:32:09 PM PDT 24
Finished Jun 07 08:32:20 PM PDT 24
Peak memory 204404 kb
Host smart-5c2b7b9a-f7ae-4e33-b30d-31e8f2e17ad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439763038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1439763038
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1865498373
Short name T1001
Test name
Test status
Simulation time 47790580 ps
CPU time 0.73 seconds
Started Jun 07 08:32:07 PM PDT 24
Finished Jun 07 08:32:19 PM PDT 24
Peak memory 204368 kb
Host smart-dbdae2de-97a9-477d-8072-3c7519c5618b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865498373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1865498373
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1439819346
Short name T997
Test name
Test status
Simulation time 46838064 ps
CPU time 0.7 seconds
Started Jun 07 08:32:09 PM PDT 24
Finished Jun 07 08:32:24 PM PDT 24
Peak memory 204096 kb
Host smart-3961e432-741f-4d9e-a4f7-603ccb6c45ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439819346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1439819346
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3825337071
Short name T977
Test name
Test status
Simulation time 91590287 ps
CPU time 0.75 seconds
Started Jun 07 08:32:03 PM PDT 24
Finished Jun 07 08:32:16 PM PDT 24
Peak memory 204072 kb
Host smart-afaa11b5-c2d7-419d-90bc-9bd9bb407191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825337071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3825337071
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4134488014
Short name T1094
Test name
Test status
Simulation time 20114032 ps
CPU time 0.7 seconds
Started Jun 07 08:32:23 PM PDT 24
Finished Jun 07 08:32:31 PM PDT 24
Peak memory 204376 kb
Host smart-0b45f311-41ca-4ef5-b564-8399383438c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134488014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
4134488014
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2331882643
Short name T1031
Test name
Test status
Simulation time 19930147 ps
CPU time 0.71 seconds
Started Jun 07 08:32:11 PM PDT 24
Finished Jun 07 08:32:22 PM PDT 24
Peak memory 204072 kb
Host smart-5d719c19-0ae3-4b57-9800-7802419e49b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331882643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2331882643
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4125057978
Short name T1068
Test name
Test status
Simulation time 11772571 ps
CPU time 0.7 seconds
Started Jun 07 08:32:05 PM PDT 24
Finished Jun 07 08:32:17 PM PDT 24
Peak memory 204032 kb
Host smart-24439f81-ec4f-4e90-8e68-fd8688f88cbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125057978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
4125057978
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3201857057
Short name T1099
Test name
Test status
Simulation time 100339439 ps
CPU time 0.74 seconds
Started Jun 07 08:32:12 PM PDT 24
Finished Jun 07 08:32:22 PM PDT 24
Peak memory 204096 kb
Host smart-79a9fc9d-56ae-4418-8308-e6101b44ec34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201857057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3201857057
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2939865059
Short name T1059
Test name
Test status
Simulation time 948052237 ps
CPU time 23.3 seconds
Started Jun 07 08:31:48 PM PDT 24
Finished Jun 07 08:32:26 PM PDT 24
Peak memory 207584 kb
Host smart-7f6e6ce5-4c8b-4202-8a9c-e907fdfeea6a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939865059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2939865059
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.526761088
Short name T1033
Test name
Test status
Simulation time 10044299266 ps
CPU time 35.94 seconds
Started Jun 07 08:31:50 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 215852 kb
Host smart-ba95f118-1f87-445c-bd45-ae855b148cdb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526761088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.526761088
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.950943729
Short name T85
Test name
Test status
Simulation time 14707392 ps
CPU time 0.92 seconds
Started Jun 07 08:31:45 PM PDT 24
Finished Jun 07 08:31:59 PM PDT 24
Peak memory 207336 kb
Host smart-6bab5dfe-dd8e-4cae-b1f4-f44766b0e4a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950943729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.950943729
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4098778832
Short name T1060
Test name
Test status
Simulation time 208662685 ps
CPU time 3.67 seconds
Started Jun 07 08:31:48 PM PDT 24
Finished Jun 07 08:32:06 PM PDT 24
Peak memory 218520 kb
Host smart-3aebc141-8222-4cfa-98a4-50c315ba007f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098778832 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.4098778832
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1792327096
Short name T1100
Test name
Test status
Simulation time 43666685 ps
CPU time 1.48 seconds
Started Jun 07 08:31:50 PM PDT 24
Finished Jun 07 08:32:06 PM PDT 24
Peak memory 207668 kb
Host smart-2daed311-d1ef-4e97-9763-ad1b9a7aa208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792327096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
792327096
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1877648390
Short name T1081
Test name
Test status
Simulation time 14998925 ps
CPU time 0.71 seconds
Started Jun 07 08:31:47 PM PDT 24
Finished Jun 07 08:32:02 PM PDT 24
Peak memory 204064 kb
Host smart-ded8dba3-be91-4e13-a08a-7186732d2b90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877648390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
877648390
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3122790145
Short name T124
Test name
Test status
Simulation time 92452320 ps
CPU time 2.03 seconds
Started Jun 07 08:31:48 PM PDT 24
Finished Jun 07 08:32:05 PM PDT 24
Peak memory 215904 kb
Host smart-148537c1-2cdf-4868-b839-2d7ca8732ea7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122790145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3122790145
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1866036620
Short name T978
Test name
Test status
Simulation time 26570520 ps
CPU time 0.64 seconds
Started Jun 07 08:31:43 PM PDT 24
Finished Jun 07 08:31:58 PM PDT 24
Peak memory 204004 kb
Host smart-ee8b6593-3065-46dd-bed1-e67b82f35d5a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866036620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1866036620
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2411790364
Short name T137
Test name
Test status
Simulation time 237058824 ps
CPU time 4.49 seconds
Started Jun 07 08:31:49 PM PDT 24
Finished Jun 07 08:32:08 PM PDT 24
Peak memory 215780 kb
Host smart-0dd9521a-897b-49c4-b936-d168e0ad80ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411790364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2411790364
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.342361102
Short name T1037
Test name
Test status
Simulation time 308155423 ps
CPU time 4 seconds
Started Jun 07 08:31:47 PM PDT 24
Finished Jun 07 08:32:05 PM PDT 24
Peak memory 215960 kb
Host smart-eefc6c90-1ca3-4aa6-b150-6628c6a61a6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342361102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.342361102
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2297643093
Short name T1097
Test name
Test status
Simulation time 282051596 ps
CPU time 17.3 seconds
Started Jun 07 08:31:41 PM PDT 24
Finished Jun 07 08:32:10 PM PDT 24
Peak memory 215884 kb
Host smart-e08b644d-571a-470c-970a-f07981bb96b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297643093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2297643093
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2653798104
Short name T1055
Test name
Test status
Simulation time 44975531 ps
CPU time 0.73 seconds
Started Jun 07 08:32:06 PM PDT 24
Finished Jun 07 08:32:18 PM PDT 24
Peak memory 204208 kb
Host smart-0a78203e-6ab3-42cc-9501-7aa4a6a68786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653798104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2653798104
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4069412346
Short name T1034
Test name
Test status
Simulation time 17636003 ps
CPU time 0.81 seconds
Started Jun 07 08:32:07 PM PDT 24
Finished Jun 07 08:32:19 PM PDT 24
Peak memory 204392 kb
Host smart-a89ac6c7-6fd9-41f7-a0cb-6175fb26d4e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069412346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4069412346
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2213255357
Short name T1048
Test name
Test status
Simulation time 25958419 ps
CPU time 0.73 seconds
Started Jun 07 08:32:06 PM PDT 24
Finished Jun 07 08:32:18 PM PDT 24
Peak memory 204152 kb
Host smart-4ce615a3-fb8e-4289-9af7-16451fc8b98d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213255357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2213255357
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2339188432
Short name T1056
Test name
Test status
Simulation time 22298532 ps
CPU time 0.74 seconds
Started Jun 07 08:32:03 PM PDT 24
Finished Jun 07 08:32:16 PM PDT 24
Peak memory 204076 kb
Host smart-103ed2a8-1a3e-49ea-ab98-37a0d839ef47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339188432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2339188432
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2392290796
Short name T982
Test name
Test status
Simulation time 16602391 ps
CPU time 0.72 seconds
Started Jun 07 08:32:03 PM PDT 24
Finished Jun 07 08:32:16 PM PDT 24
Peak memory 204376 kb
Host smart-28428f42-aeff-4dcb-91da-da79feae8826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392290796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2392290796
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3661840551
Short name T1045
Test name
Test status
Simulation time 20398679 ps
CPU time 0.71 seconds
Started Jun 07 08:32:03 PM PDT 24
Finished Jun 07 08:32:16 PM PDT 24
Peak memory 204052 kb
Host smart-79813fa6-15bf-41ea-919e-a23e4b685f47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661840551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3661840551
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.182611908
Short name T1085
Test name
Test status
Simulation time 35485517 ps
CPU time 0.76 seconds
Started Jun 07 08:32:06 PM PDT 24
Finished Jun 07 08:32:18 PM PDT 24
Peak memory 204056 kb
Host smart-b8b16de0-2ad0-4a04-b476-41d0d7831a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182611908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.182611908
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4092980288
Short name T1074
Test name
Test status
Simulation time 12347936 ps
CPU time 0.73 seconds
Started Jun 07 08:32:03 PM PDT 24
Finished Jun 07 08:32:16 PM PDT 24
Peak memory 204068 kb
Host smart-497a8949-095b-4a1b-9b9c-7540e0c5a550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092980288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4092980288
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.746415182
Short name T1020
Test name
Test status
Simulation time 57397269 ps
CPU time 0.72 seconds
Started Jun 07 08:32:10 PM PDT 24
Finished Jun 07 08:32:21 PM PDT 24
Peak memory 204068 kb
Host smart-d2e903e6-3697-4997-b8a4-a09b239ff44b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746415182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.746415182
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1315956069
Short name T1072
Test name
Test status
Simulation time 99638306 ps
CPU time 0.72 seconds
Started Jun 07 08:32:04 PM PDT 24
Finished Jun 07 08:32:17 PM PDT 24
Peak memory 204412 kb
Host smart-3061dc42-ef53-4d84-ab1d-2a4033a94beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315956069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1315956069
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2098947762
Short name T114
Test name
Test status
Simulation time 479645445 ps
CPU time 7.47 seconds
Started Jun 07 08:31:53 PM PDT 24
Finished Jun 07 08:32:14 PM PDT 24
Peak memory 215668 kb
Host smart-8e711267-e23f-4e18-a881-7a1be2613a48
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098947762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2098947762
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2937730944
Short name T1046
Test name
Test status
Simulation time 817786169 ps
CPU time 11.63 seconds
Started Jun 07 08:31:48 PM PDT 24
Finished Jun 07 08:32:14 PM PDT 24
Peak memory 207600 kb
Host smart-ea50189d-9959-42e1-ba3a-7a5f242ba5f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937730944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2937730944
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3847927395
Short name T88
Test name
Test status
Simulation time 79497269 ps
CPU time 0.95 seconds
Started Jun 07 08:31:51 PM PDT 24
Finished Jun 07 08:32:06 PM PDT 24
Peak memory 207340 kb
Host smart-9ebb50d1-a513-4129-9dd8-88b04e927bf0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847927395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3847927395
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2512094321
Short name T109
Test name
Test status
Simulation time 54570120 ps
CPU time 1.74 seconds
Started Jun 07 08:31:51 PM PDT 24
Finished Jun 07 08:32:07 PM PDT 24
Peak memory 216868 kb
Host smart-e92a5512-2ad2-4e65-8a97-24ee37c2021b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512094321 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2512094321
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.407010790
Short name T112
Test name
Test status
Simulation time 201404930 ps
CPU time 1.46 seconds
Started Jun 07 08:31:52 PM PDT 24
Finished Jun 07 08:32:07 PM PDT 24
Peak memory 215812 kb
Host smart-851daae3-d199-4e66-a16e-1abbdd82bd0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407010790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.407010790
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3642681626
Short name T1041
Test name
Test status
Simulation time 88367661 ps
CPU time 0.73 seconds
Started Jun 07 08:32:01 PM PDT 24
Finished Jun 07 08:32:14 PM PDT 24
Peak memory 204368 kb
Host smart-290077ec-878b-4f1e-be73-88eea8465929
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642681626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
642681626
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2420362963
Short name T1054
Test name
Test status
Simulation time 40854749 ps
CPU time 1.35 seconds
Started Jun 07 08:31:51 PM PDT 24
Finished Jun 07 08:32:06 PM PDT 24
Peak memory 215904 kb
Host smart-ed646bb1-33db-45bc-a4c2-d9851d2caa65
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420362963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2420362963
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4095463457
Short name T1090
Test name
Test status
Simulation time 16758383 ps
CPU time 0.69 seconds
Started Jun 07 08:31:50 PM PDT 24
Finished Jun 07 08:32:06 PM PDT 24
Peak memory 204036 kb
Host smart-d0441ad5-0ca3-449e-bfe5-1d81ad278247
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095463457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4095463457
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2477661162
Short name T1027
Test name
Test status
Simulation time 108704827 ps
CPU time 1.69 seconds
Started Jun 07 08:31:47 PM PDT 24
Finished Jun 07 08:32:04 PM PDT 24
Peak memory 215820 kb
Host smart-eafac723-2c09-4a3a-aa88-f04cf3a92359
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477661162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2477661162
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1377164719
Short name T108
Test name
Test status
Simulation time 255929401 ps
CPU time 1.7 seconds
Started Jun 07 08:31:51 PM PDT 24
Finished Jun 07 08:32:07 PM PDT 24
Peak memory 216144 kb
Host smart-1fbbd8f9-5408-49a8-9b7d-8dc1438028ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377164719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
377164719
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3535854524
Short name T240
Test name
Test status
Simulation time 215249617 ps
CPU time 6.84 seconds
Started Jun 07 08:31:53 PM PDT 24
Finished Jun 07 08:32:14 PM PDT 24
Peak memory 215536 kb
Host smart-cc14abe0-3f1a-4a40-a588-ef01918f3494
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535854524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3535854524
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.258119838
Short name T1092
Test name
Test status
Simulation time 19959170 ps
CPU time 0.71 seconds
Started Jun 07 08:32:13 PM PDT 24
Finished Jun 07 08:32:23 PM PDT 24
Peak memory 204084 kb
Host smart-19bf0045-cf38-44ae-867c-10a4d2c16cfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258119838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.258119838
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.118338409
Short name T981
Test name
Test status
Simulation time 14601255 ps
CPU time 0.72 seconds
Started Jun 07 08:32:09 PM PDT 24
Finished Jun 07 08:32:21 PM PDT 24
Peak memory 204144 kb
Host smart-6ec933ec-5b82-4a21-8ebf-b48defbd3891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118338409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.118338409
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1934280102
Short name T1030
Test name
Test status
Simulation time 40846084 ps
CPU time 0.71 seconds
Started Jun 07 08:32:08 PM PDT 24
Finished Jun 07 08:32:20 PM PDT 24
Peak memory 204064 kb
Host smart-07fdbe09-e01f-4c70-8813-c0fe5a2f11e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934280102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1934280102
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.742485518
Short name T992
Test name
Test status
Simulation time 13500861 ps
CPU time 0.68 seconds
Started Jun 07 08:32:19 PM PDT 24
Finished Jun 07 08:32:27 PM PDT 24
Peak memory 204076 kb
Host smart-7b4a69ec-33c4-489c-8ad9-42f81a50b17e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742485518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.742485518
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1040793270
Short name T1043
Test name
Test status
Simulation time 26886953 ps
CPU time 0.72 seconds
Started Jun 07 08:32:19 PM PDT 24
Finished Jun 07 08:32:28 PM PDT 24
Peak memory 204088 kb
Host smart-6555ef2c-3c4f-487c-9965-e6fa1f936fa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040793270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1040793270
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.934926901
Short name T986
Test name
Test status
Simulation time 42164496 ps
CPU time 0.71 seconds
Started Jun 07 08:32:12 PM PDT 24
Finished Jun 07 08:32:22 PM PDT 24
Peak memory 204084 kb
Host smart-3c2ed052-28a3-4881-bd48-4f3dd7985955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934926901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.934926901
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4055186550
Short name T994
Test name
Test status
Simulation time 30430754 ps
CPU time 0.67 seconds
Started Jun 07 08:32:25 PM PDT 24
Finished Jun 07 08:32:32 PM PDT 24
Peak memory 204380 kb
Host smart-7660eabe-00f7-4f53-a13c-a5d685f72588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055186550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4055186550
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.460014307
Short name T1038
Test name
Test status
Simulation time 23804822 ps
CPU time 0.71 seconds
Started Jun 07 08:32:21 PM PDT 24
Finished Jun 07 08:32:29 PM PDT 24
Peak memory 204328 kb
Host smart-b57a54e9-4f90-48f8-a058-a1a9b95b1c04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460014307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.460014307
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3514448363
Short name T1053
Test name
Test status
Simulation time 80988803 ps
CPU time 0.73 seconds
Started Jun 07 08:32:24 PM PDT 24
Finished Jun 07 08:32:32 PM PDT 24
Peak memory 204072 kb
Host smart-f6f95de0-12c6-485f-8769-e6ab6504ba48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514448363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3514448363
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.618440519
Short name T1075
Test name
Test status
Simulation time 28055254 ps
CPU time 0.75 seconds
Started Jun 07 08:32:15 PM PDT 24
Finished Jun 07 08:32:25 PM PDT 24
Peak memory 204088 kb
Host smart-790fbd73-ca63-42fc-b7b0-35c487c2957d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618440519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.618440519
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3955541397
Short name T136
Test name
Test status
Simulation time 84411246 ps
CPU time 2.7 seconds
Started Jun 07 08:31:50 PM PDT 24
Finished Jun 07 08:32:07 PM PDT 24
Peak memory 217424 kb
Host smart-9868d9b0-7860-4021-b159-0af5689f8caa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955541397 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3955541397
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.284437172
Short name T1070
Test name
Test status
Simulation time 43519485 ps
CPU time 1.45 seconds
Started Jun 07 08:31:49 PM PDT 24
Finished Jun 07 08:32:04 PM PDT 24
Peak memory 215724 kb
Host smart-bacd4623-0b63-4c73-a807-bbf055e35214
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284437172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.284437172
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1466166552
Short name T1019
Test name
Test status
Simulation time 90190334 ps
CPU time 0.68 seconds
Started Jun 07 08:31:52 PM PDT 24
Finished Jun 07 08:32:07 PM PDT 24
Peak memory 204060 kb
Host smart-e7e616f5-8eb3-4f07-bf1a-48add47b8f3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466166552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
466166552
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4081364573
Short name T995
Test name
Test status
Simulation time 43734462 ps
CPU time 2.66 seconds
Started Jun 07 08:31:52 PM PDT 24
Finished Jun 07 08:32:08 PM PDT 24
Peak memory 215760 kb
Host smart-210f773c-44a1-480a-8a7a-702f6d36d059
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081364573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4081364573
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2226259981
Short name T93
Test name
Test status
Simulation time 458444158 ps
CPU time 3.42 seconds
Started Jun 07 08:31:48 PM PDT 24
Finished Jun 07 08:32:06 PM PDT 24
Peak memory 216024 kb
Host smart-8c3168ff-a5ff-4bdf-baa1-29b20d89312a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226259981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
226259981
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1799320202
Short name T1088
Test name
Test status
Simulation time 221605526 ps
CPU time 1.78 seconds
Started Jun 07 08:31:52 PM PDT 24
Finished Jun 07 08:32:08 PM PDT 24
Peak memory 215956 kb
Host smart-03cceb45-b307-4195-a1be-f09a0b33d69b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799320202 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1799320202
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1180899550
Short name T1047
Test name
Test status
Simulation time 39567970 ps
CPU time 1.16 seconds
Started Jun 07 08:31:55 PM PDT 24
Finished Jun 07 08:32:09 PM PDT 24
Peak memory 207588 kb
Host smart-fa4bfade-fc77-4edd-bdda-a8a34bd413c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180899550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
180899550
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2986222419
Short name T990
Test name
Test status
Simulation time 14930988 ps
CPU time 0.74 seconds
Started Jun 07 08:31:49 PM PDT 24
Finished Jun 07 08:32:04 PM PDT 24
Peak memory 204404 kb
Host smart-b9a225b7-bcc5-4249-8372-d97855b82942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986222419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
986222419
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.764866755
Short name T980
Test name
Test status
Simulation time 60852625 ps
CPU time 3.81 seconds
Started Jun 07 08:31:49 PM PDT 24
Finished Jun 07 08:32:07 PM PDT 24
Peak memory 215844 kb
Host smart-b8238f2b-aa2b-4066-8d86-fe50becf7d38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764866755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.764866755
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.234310244
Short name T100
Test name
Test status
Simulation time 40176539 ps
CPU time 2.69 seconds
Started Jun 07 08:31:54 PM PDT 24
Finished Jun 07 08:32:15 PM PDT 24
Peak memory 219760 kb
Host smart-030ea3df-edf2-4aa5-9adc-5edfc0984776
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234310244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.234310244
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3209393883
Short name T140
Test name
Test status
Simulation time 965360344 ps
CPU time 14.99 seconds
Started Jun 07 08:31:49 PM PDT 24
Finished Jun 07 08:32:19 PM PDT 24
Peak memory 215760 kb
Host smart-da60281f-4ecf-4a4c-b39a-b1e3fa3e73e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209393883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3209393883
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4075642967
Short name T1087
Test name
Test status
Simulation time 227178458 ps
CPU time 3.86 seconds
Started Jun 07 08:31:55 PM PDT 24
Finished Jun 07 08:32:12 PM PDT 24
Peak memory 217496 kb
Host smart-a222055d-1e02-423a-8ef5-eb5aba2a11c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075642967 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.4075642967
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.801303189
Short name T120
Test name
Test status
Simulation time 44967703 ps
CPU time 2.38 seconds
Started Jun 07 08:31:56 PM PDT 24
Finished Jun 07 08:32:16 PM PDT 24
Peak memory 215764 kb
Host smart-e937e5d2-3c4d-4d64-aa3c-a0bb527a7307
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801303189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.801303189
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2198084132
Short name T1000
Test name
Test status
Simulation time 41665777 ps
CPU time 0.72 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:11 PM PDT 24
Peak memory 204408 kb
Host smart-020e79ec-53d9-482b-b9fa-325efa15397a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198084132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
198084132
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1102879335
Short name T983
Test name
Test status
Simulation time 42633361 ps
CPU time 2.89 seconds
Started Jun 07 08:31:57 PM PDT 24
Finished Jun 07 08:32:13 PM PDT 24
Peak memory 216932 kb
Host smart-fc88c87a-52d9-44e4-90d3-6ae6b1f27172
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102879335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1102879335
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3836700205
Short name T104
Test name
Test status
Simulation time 54554952 ps
CPU time 2.96 seconds
Started Jun 07 08:31:50 PM PDT 24
Finished Jun 07 08:32:07 PM PDT 24
Peak memory 216976 kb
Host smart-d802e988-9937-4c11-a2fd-77f363c24086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836700205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
836700205
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2551697984
Short name T1066
Test name
Test status
Simulation time 2540383661 ps
CPU time 14.96 seconds
Started Jun 07 08:31:57 PM PDT 24
Finished Jun 07 08:32:25 PM PDT 24
Peak memory 224044 kb
Host smart-29cffd54-c8f8-4311-9f5d-b437b469543d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551697984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2551697984
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.21042704
Short name T141
Test name
Test status
Simulation time 125216362 ps
CPU time 2.71 seconds
Started Jun 07 08:31:59 PM PDT 24
Finished Jun 07 08:32:14 PM PDT 24
Peak memory 217108 kb
Host smart-49c1f00e-b36b-4412-8010-feae710cd029
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21042704 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.21042704
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1457425776
Short name T123
Test name
Test status
Simulation time 267410673 ps
CPU time 2.09 seconds
Started Jun 07 08:31:57 PM PDT 24
Finished Jun 07 08:32:13 PM PDT 24
Peak memory 215816 kb
Host smart-4f28f86f-3194-4d79-98db-24bf3290e7dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457425776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
457425776
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.366136283
Short name T1091
Test name
Test status
Simulation time 22485615 ps
CPU time 0.7 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:11 PM PDT 24
Peak memory 204396 kb
Host smart-42841d9f-3662-47c8-a659-14e0379709f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366136283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.366136283
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3267329915
Short name T996
Test name
Test status
Simulation time 324987552 ps
CPU time 4.14 seconds
Started Jun 07 08:32:00 PM PDT 24
Finished Jun 07 08:32:17 PM PDT 24
Peak memory 215736 kb
Host smart-15b54117-8f63-45b1-b0df-0fe5ea788fb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267329915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3267329915
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.518915735
Short name T105
Test name
Test status
Simulation time 331305390 ps
CPU time 3.29 seconds
Started Jun 07 08:31:57 PM PDT 24
Finished Jun 07 08:32:14 PM PDT 24
Peak memory 216000 kb
Host smart-09ae7038-1c05-468b-b1f2-6beadb7d8c82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518915735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.518915735
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2341106158
Short name T1083
Test name
Test status
Simulation time 407372704 ps
CPU time 13.65 seconds
Started Jun 07 08:31:56 PM PDT 24
Finished Jun 07 08:32:23 PM PDT 24
Peak memory 215780 kb
Host smart-54774520-b4d2-4512-ba54-03baa28e7159
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341106158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2341106158
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1665728265
Short name T1042
Test name
Test status
Simulation time 57668378 ps
CPU time 3.65 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:15 PM PDT 24
Peak memory 218444 kb
Host smart-9954021d-727a-4dcf-b4e3-59ea029b139d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665728265 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1665728265
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3404253230
Short name T125
Test name
Test status
Simulation time 78210556 ps
CPU time 1.39 seconds
Started Jun 07 08:31:59 PM PDT 24
Finished Jun 07 08:32:14 PM PDT 24
Peak memory 207544 kb
Host smart-55829dba-bf21-42c3-afab-ce1de136e739
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404253230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
404253230
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1518442625
Short name T984
Test name
Test status
Simulation time 213965795 ps
CPU time 0.73 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:11 PM PDT 24
Peak memory 204088 kb
Host smart-1211696d-be78-41d1-9369-706361e5abd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518442625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
518442625
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1121613865
Short name T1065
Test name
Test status
Simulation time 85862126 ps
CPU time 3.72 seconds
Started Jun 07 08:31:58 PM PDT 24
Finished Jun 07 08:32:15 PM PDT 24
Peak memory 215824 kb
Host smart-bfbd0224-1c06-4ac4-b2c9-d994f17e97cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121613865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1121613865
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3852415479
Short name T1017
Test name
Test status
Simulation time 168668235 ps
CPU time 3.88 seconds
Started Jun 07 08:31:56 PM PDT 24
Finished Jun 07 08:32:13 PM PDT 24
Peak memory 216056 kb
Host smart-189b1a88-1fde-43fe-85fb-33ec7e5e919b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852415479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
852415479
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.691079917
Short name T1035
Test name
Test status
Simulation time 1436068562 ps
CPU time 7.86 seconds
Started Jun 07 08:31:56 PM PDT 24
Finished Jun 07 08:32:17 PM PDT 24
Peak memory 215948 kb
Host smart-0bd2b38d-0c36-4d83-8636-ee630ec7e501
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691079917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.691079917
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3439097803
Short name T655
Test name
Test status
Simulation time 10845404 ps
CPU time 0.69 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:14 PM PDT 24
Peak memory 204496 kb
Host smart-1267ca9f-08db-4ef1-a7f3-ec32b5dbc9b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439097803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
439097803
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1164322425
Short name T607
Test name
Test status
Simulation time 122663476 ps
CPU time 4.06 seconds
Started Jun 07 08:09:10 PM PDT 24
Finished Jun 07 08:09:16 PM PDT 24
Peak memory 224296 kb
Host smart-6db4cd3c-58fb-43a4-896e-5b84782f7848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164322425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1164322425
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3197725964
Short name T940
Test name
Test status
Simulation time 12444173 ps
CPU time 0.76 seconds
Started Jun 07 08:09:03 PM PDT 24
Finished Jun 07 08:09:07 PM PDT 24
Peak memory 205192 kb
Host smart-28533ca5-0617-4388-a84c-d078d8a8ca4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197725964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3197725964
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3002698627
Short name T24
Test name
Test status
Simulation time 41509375856 ps
CPU time 391.26 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:15:46 PM PDT 24
Peak memory 250252 kb
Host smart-34d7b773-0d76-47a0-b39d-8024df5d7b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002698627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3002698627
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3159571060
Short name T494
Test name
Test status
Simulation time 676123852 ps
CPU time 3.71 seconds
Started Jun 07 08:09:05 PM PDT 24
Finished Jun 07 08:09:11 PM PDT 24
Peak memory 224284 kb
Host smart-e2f1bc3a-d7df-4645-92e1-bd845e7f2d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159571060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3159571060
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1271773221
Short name T554
Test name
Test status
Simulation time 14035412 ps
CPU time 1.01 seconds
Started Jun 07 08:09:08 PM PDT 24
Finished Jun 07 08:09:10 PM PDT 24
Peak memory 217588 kb
Host smart-d92fdca1-08b9-47c6-8a61-4ac590d37da0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271773221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1271773221
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3906806862
Short name T839
Test name
Test status
Simulation time 33359572781 ps
CPU time 27.49 seconds
Started Jun 07 08:09:02 PM PDT 24
Finished Jun 07 08:09:33 PM PDT 24
Peak memory 233668 kb
Host smart-176d4586-2f6e-4699-bd19-e3319a9d4cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906806862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3906806862
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2492978985
Short name T756
Test name
Test status
Simulation time 7130204867 ps
CPU time 20.25 seconds
Started Jun 07 08:09:10 PM PDT 24
Finished Jun 07 08:09:32 PM PDT 24
Peak memory 224380 kb
Host smart-b1061698-3e0c-46b4-b2a3-cbc7a71620e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492978985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2492978985
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2015172951
Short name T466
Test name
Test status
Simulation time 930077210 ps
CPU time 5.38 seconds
Started Jun 07 08:09:02 PM PDT 24
Finished Jun 07 08:09:10 PM PDT 24
Peak memory 222672 kb
Host smart-38b81b8d-03aa-4415-9736-e0e96ea200d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2015172951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2015172951
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1937805207
Short name T74
Test name
Test status
Simulation time 119354160 ps
CPU time 1.12 seconds
Started Jun 07 08:09:01 PM PDT 24
Finished Jun 07 08:09:06 PM PDT 24
Peak memory 234916 kb
Host smart-33db5ffb-a04a-4d7b-aeb6-eae2b2cc81da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937805207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1937805207
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.612683252
Short name T408
Test name
Test status
Simulation time 10524760302 ps
CPU time 26.58 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:44 PM PDT 24
Peak memory 216200 kb
Host smart-fb04c1f1-ec91-47e6-993a-cc4476ca425a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612683252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.612683252
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3819330685
Short name T378
Test name
Test status
Simulation time 886473964 ps
CPU time 6.12 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:19 PM PDT 24
Peak memory 215976 kb
Host smart-87b0f95d-d149-4402-b8ed-dc06fce9e0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819330685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3819330685
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4167789439
Short name T879
Test name
Test status
Simulation time 87693248 ps
CPU time 3.83 seconds
Started Jun 07 08:09:04 PM PDT 24
Finished Jun 07 08:09:10 PM PDT 24
Peak memory 216036 kb
Host smart-b93396f3-0833-43c6-a737-a292a1fc2627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167789439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4167789439
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1123521929
Short name T749
Test name
Test status
Simulation time 217114627 ps
CPU time 0.91 seconds
Started Jun 07 08:09:03 PM PDT 24
Finished Jun 07 08:09:07 PM PDT 24
Peak memory 205948 kb
Host smart-5f4a1090-51ec-42fc-b423-23981f125ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123521929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1123521929
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.610559292
Short name T469
Test name
Test status
Simulation time 310287917 ps
CPU time 2.76 seconds
Started Jun 07 08:09:03 PM PDT 24
Finished Jun 07 08:09:09 PM PDT 24
Peak memory 224368 kb
Host smart-c6b5cb54-dfbf-4eae-8c08-b4c0be75b3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610559292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.610559292
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3035457044
Short name T895
Test name
Test status
Simulation time 21007712 ps
CPU time 0.78 seconds
Started Jun 07 08:09:15 PM PDT 24
Finished Jun 07 08:09:22 PM PDT 24
Peak memory 204556 kb
Host smart-48f29de3-db7e-4550-83fc-cf0cf0919e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035457044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
035457044
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1698859221
Short name T566
Test name
Test status
Simulation time 1004335444 ps
CPU time 3.94 seconds
Started Jun 07 08:09:12 PM PDT 24
Finished Jun 07 08:09:20 PM PDT 24
Peak memory 224364 kb
Host smart-08842ab6-6016-449e-9e37-4772bf82c1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698859221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1698859221
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3582899611
Short name T626
Test name
Test status
Simulation time 17294868 ps
CPU time 0.76 seconds
Started Jun 07 08:09:03 PM PDT 24
Finished Jun 07 08:09:06 PM PDT 24
Peak memory 206260 kb
Host smart-e2b9099d-f470-40fc-8139-decd36be65b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582899611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3582899611
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3047330343
Short name T39
Test name
Test status
Simulation time 22803305337 ps
CPU time 107.96 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:11:14 PM PDT 24
Peak memory 248960 kb
Host smart-ebd0a52b-dcda-4f41-adce-580da3be62e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047330343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3047330343
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1071622033
Short name T905
Test name
Test status
Simulation time 91946929440 ps
CPU time 122.48 seconds
Started Jun 07 08:09:18 PM PDT 24
Finished Jun 07 08:11:27 PM PDT 24
Peak memory 249024 kb
Host smart-99de50cd-b1d2-4ae1-8348-aafe3d344b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071622033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1071622033
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1539638942
Short name T502
Test name
Test status
Simulation time 181491440 ps
CPU time 3.94 seconds
Started Jun 07 08:09:04 PM PDT 24
Finished Jun 07 08:09:11 PM PDT 24
Peak memory 218400 kb
Host smart-e82f601f-6808-4c7c-9f12-6af12939cbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539638942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1539638942
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3894175137
Short name T572
Test name
Test status
Simulation time 2085668449 ps
CPU time 8.98 seconds
Started Jun 07 08:09:10 PM PDT 24
Finished Jun 07 08:09:21 PM PDT 24
Peak memory 232564 kb
Host smart-8fafdcb6-3b90-4232-8227-b20545cd1258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894175137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3894175137
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.4192503757
Short name T643
Test name
Test status
Simulation time 15774317 ps
CPU time 1.05 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:15 PM PDT 24
Peak memory 216396 kb
Host smart-d90f75ac-600d-440b-8b5d-66bbe249aa29
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192503757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.4192503757
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1014845892
Short name T483
Test name
Test status
Simulation time 6195390362 ps
CPU time 6.16 seconds
Started Jun 07 08:09:04 PM PDT 24
Finished Jun 07 08:09:13 PM PDT 24
Peak memory 224396 kb
Host smart-d4a68047-ed12-40fd-bb72-932179ac60ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014845892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1014845892
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4202879958
Short name T175
Test name
Test status
Simulation time 11113663584 ps
CPU time 17.73 seconds
Started Jun 07 08:09:17 PM PDT 24
Finished Jun 07 08:09:42 PM PDT 24
Peak memory 224236 kb
Host smart-c6e5be10-ddaf-4434-982c-000cd60ca8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202879958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4202879958
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.201397672
Short name T445
Test name
Test status
Simulation time 1067808114 ps
CPU time 4.89 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:23 PM PDT 24
Peak memory 218540 kb
Host smart-e793e760-d2a0-4afa-8572-8fe26e4f1169
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=201397672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.201397672
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2173903922
Short name T75
Test name
Test status
Simulation time 81221992 ps
CPU time 0.94 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:21 PM PDT 24
Peak memory 234952 kb
Host smart-9ac2bd70-d80e-4316-b9e2-5b1276387edd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173903922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2173903922
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3842808429
Short name T928
Test name
Test status
Simulation time 1842225006 ps
CPU time 15.38 seconds
Started Jun 07 08:09:12 PM PDT 24
Finished Jun 07 08:09:31 PM PDT 24
Peak memory 219356 kb
Host smart-5c5ac859-d76c-4e74-905b-1740e032bbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842808429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3842808429
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1735712069
Short name T959
Test name
Test status
Simulation time 43138090120 ps
CPU time 30 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:43 PM PDT 24
Peak memory 216156 kb
Host smart-7fdadfa4-42c3-44a4-9dbe-13de4af7ca64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735712069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1735712069
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3993917016
Short name T593
Test name
Test status
Simulation time 405765120 ps
CPU time 11.78 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:30 PM PDT 24
Peak memory 216020 kb
Host smart-52934d0d-77fa-42db-88c9-41b9982164a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993917016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3993917016
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2928902408
Short name T765
Test name
Test status
Simulation time 327731147 ps
CPU time 0.88 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:14 PM PDT 24
Peak memory 205544 kb
Host smart-c42c8b8c-1487-4673-b805-b203ee21ba55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928902408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2928902408
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3743962953
Short name T421
Test name
Test status
Simulation time 52753038055 ps
CPU time 49.45 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:10:08 PM PDT 24
Peak memory 235852 kb
Host smart-927960ef-344a-466b-b1a7-7f3ac74f44c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743962953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3743962953
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.32131818
Short name T57
Test name
Test status
Simulation time 21107271 ps
CPU time 0.75 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:09:27 PM PDT 24
Peak memory 205192 kb
Host smart-a514448d-c145-4439-a957-e1d8212771a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32131818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.32131818
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2666871288
Short name T371
Test name
Test status
Simulation time 13065994 ps
CPU time 0.74 seconds
Started Jun 07 08:09:28 PM PDT 24
Finished Jun 07 08:09:33 PM PDT 24
Peak memory 206596 kb
Host smart-b5e301e8-507f-4032-abad-e7366ac82e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666871288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2666871288
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.716893704
Short name T592
Test name
Test status
Simulation time 727307002 ps
CPU time 8.55 seconds
Started Jun 07 08:09:17 PM PDT 24
Finished Jun 07 08:09:33 PM PDT 24
Peak memory 236284 kb
Host smart-77c839d5-9dde-4395-85fb-ecc575a19c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716893704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.716893704
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1773193284
Short name T418
Test name
Test status
Simulation time 8191630686 ps
CPU time 60.5 seconds
Started Jun 07 08:09:23 PM PDT 24
Finished Jun 07 08:10:29 PM PDT 24
Peak memory 232576 kb
Host smart-8841989e-3ce2-4e46-9720-92fd99770801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773193284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1773193284
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3676158658
Short name T282
Test name
Test status
Simulation time 635662474 ps
CPU time 9.61 seconds
Started Jun 07 08:09:27 PM PDT 24
Finished Jun 07 08:09:41 PM PDT 24
Peak memory 232532 kb
Host smart-796eb06b-8943-40e0-9081-d216c9f269bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676158658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3676158658
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.930561777
Short name T967
Test name
Test status
Simulation time 2224161696 ps
CPU time 17.9 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:09:45 PM PDT 24
Peak memory 224368 kb
Host smart-51003505-012c-4954-adb4-1f774374de34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930561777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.930561777
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2543337889
Short name T172
Test name
Test status
Simulation time 11807469275 ps
CPU time 27.07 seconds
Started Jun 07 08:09:26 PM PDT 24
Finished Jun 07 08:09:57 PM PDT 24
Peak memory 232560 kb
Host smart-bd67c721-9bfd-4c9b-b111-589b50c29287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543337889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2543337889
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2626274270
Short name T937
Test name
Test status
Simulation time 1147033165 ps
CPU time 5.78 seconds
Started Jun 07 08:09:22 PM PDT 24
Finished Jun 07 08:09:34 PM PDT 24
Peak memory 224272 kb
Host smart-c4584d32-2345-41ba-9f20-1c8a09c466dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626274270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2626274270
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3219549628
Short name T550
Test name
Test status
Simulation time 1897365887 ps
CPU time 5.25 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:09:32 PM PDT 24
Peak memory 224228 kb
Host smart-7268d8bc-26ba-4acc-b7c1-bf211e439ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219549628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3219549628
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2532995444
Short name T873
Test name
Test status
Simulation time 620403659 ps
CPU time 4.08 seconds
Started Jun 07 08:09:28 PM PDT 24
Finished Jun 07 08:09:36 PM PDT 24
Peak memory 222876 kb
Host smart-93a0fdfc-78de-4265-97c0-2b55d104c0d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2532995444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2532995444
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2364457416
Short name T610
Test name
Test status
Simulation time 3271296870 ps
CPU time 70.11 seconds
Started Jun 07 08:09:23 PM PDT 24
Finished Jun 07 08:10:39 PM PDT 24
Peak memory 252180 kb
Host smart-eaa995db-0bef-4a0e-b2ce-73f6b5bcd3c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364457416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2364457416
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2807174670
Short name T529
Test name
Test status
Simulation time 209546489 ps
CPU time 3.39 seconds
Started Jun 07 08:09:25 PM PDT 24
Finished Jun 07 08:09:33 PM PDT 24
Peak memory 217440 kb
Host smart-d072b882-3acd-4164-b70c-2f12f9b21d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807174670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2807174670
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3774043960
Short name T595
Test name
Test status
Simulation time 943082317 ps
CPU time 5.73 seconds
Started Jun 07 08:09:21 PM PDT 24
Finished Jun 07 08:09:34 PM PDT 24
Peak memory 216048 kb
Host smart-fc8bf5d5-5cc2-4525-9748-1d06c426cb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774043960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3774043960
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1505366661
Short name T460
Test name
Test status
Simulation time 291559888 ps
CPU time 3.82 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:09:30 PM PDT 24
Peak memory 215988 kb
Host smart-657cb39d-9d25-4a48-9dbb-f17820882504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505366661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1505366661
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.712412338
Short name T637
Test name
Test status
Simulation time 267211585 ps
CPU time 0.81 seconds
Started Jun 07 08:09:25 PM PDT 24
Finished Jun 07 08:09:31 PM PDT 24
Peak memory 205604 kb
Host smart-7769e0fb-b41b-48a8-b1b0-dd874e8ef0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712412338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.712412338
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.56879637
Short name T597
Test name
Test status
Simulation time 5352611157 ps
CPU time 9.76 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:09:36 PM PDT 24
Peak memory 240720 kb
Host smart-cf9d3c80-d606-44aa-9b09-ff53cc1842e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56879637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.56879637
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1498799396
Short name T357
Test name
Test status
Simulation time 54419470 ps
CPU time 0.69 seconds
Started Jun 07 08:09:28 PM PDT 24
Finished Jun 07 08:09:33 PM PDT 24
Peak memory 205168 kb
Host smart-dc45a66f-ab4b-4c50-82c0-5947235f6296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498799396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1498799396
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.764431051
Short name T332
Test name
Test status
Simulation time 1006903800 ps
CPU time 5.47 seconds
Started Jun 07 08:09:28 PM PDT 24
Finished Jun 07 08:09:38 PM PDT 24
Peak memory 224332 kb
Host smart-c35eec78-36a5-4768-8074-89ecb7331752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764431051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.764431051
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1212588254
Short name T865
Test name
Test status
Simulation time 40555044 ps
CPU time 0.74 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:09:27 PM PDT 24
Peak memory 206580 kb
Host smart-437c480e-e692-4505-8876-3adb18b0b177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212588254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1212588254
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1406151857
Short name T393
Test name
Test status
Simulation time 2261525786 ps
CPU time 9.65 seconds
Started Jun 07 08:09:31 PM PDT 24
Finished Jun 07 08:09:44 PM PDT 24
Peak memory 233952 kb
Host smart-b9d35baa-3c25-49a8-a9c9-8ce530762b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406151857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1406151857
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.647414963
Short name T263
Test name
Test status
Simulation time 143908156838 ps
CPU time 324.02 seconds
Started Jun 07 08:09:28 PM PDT 24
Finished Jun 07 08:14:57 PM PDT 24
Peak memory 256832 kb
Host smart-c3e25fab-445e-43e7-a11d-4bd1661c9cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647414963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.647414963
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1641997249
Short name T423
Test name
Test status
Simulation time 8648353642 ps
CPU time 21.87 seconds
Started Jun 07 08:09:31 PM PDT 24
Finished Jun 07 08:09:56 PM PDT 24
Peak memory 217456 kb
Host smart-2ba459f2-90c0-4e36-a5d0-2a2141575f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641997249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1641997249
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2227647110
Short name T361
Test name
Test status
Simulation time 1683282158 ps
CPU time 10.26 seconds
Started Jun 07 08:09:30 PM PDT 24
Finished Jun 07 08:09:45 PM PDT 24
Peak memory 224364 kb
Host smart-3024e629-40fe-4f0e-a081-27375279cce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227647110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2227647110
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2570745515
Short name T724
Test name
Test status
Simulation time 628800132 ps
CPU time 4.87 seconds
Started Jun 07 08:09:28 PM PDT 24
Finished Jun 07 08:09:37 PM PDT 24
Peak memory 232504 kb
Host smart-6cb1b554-6998-4c14-949c-3c3756b40799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570745515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2570745515
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1471544052
Short name T243
Test name
Test status
Simulation time 20603388126 ps
CPU time 36.5 seconds
Started Jun 07 08:09:28 PM PDT 24
Finished Jun 07 08:10:09 PM PDT 24
Peak memory 240672 kb
Host smart-e99fa8d8-1b24-47c8-9c7c-3d0685cf7c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471544052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1471544052
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2278501430
Short name T405
Test name
Test status
Simulation time 57234551 ps
CPU time 1.05 seconds
Started Jun 07 08:09:28 PM PDT 24
Finished Jun 07 08:09:33 PM PDT 24
Peak memory 217640 kb
Host smart-66485bf3-3489-4f87-b003-e59097f3e603
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278501430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2278501430
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1705736352
Short name T395
Test name
Test status
Simulation time 98762559 ps
CPU time 3.19 seconds
Started Jun 07 08:09:27 PM PDT 24
Finished Jun 07 08:09:34 PM PDT 24
Peak memory 232528 kb
Host smart-7a94cae4-0e01-40b7-9534-9e2ba5c5f6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705736352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1705736352
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.254040581
Short name T936
Test name
Test status
Simulation time 204815917 ps
CPU time 4.16 seconds
Started Jun 07 08:09:23 PM PDT 24
Finished Jun 07 08:09:33 PM PDT 24
Peak memory 224228 kb
Host smart-bcc42016-c555-4e89-a92f-26cb26875db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254040581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.254040581
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1341420587
Short name T133
Test name
Test status
Simulation time 821128256 ps
CPU time 6.06 seconds
Started Jun 07 08:09:26 PM PDT 24
Finished Jun 07 08:09:37 PM PDT 24
Peak memory 218576 kb
Host smart-8e08e964-29cb-4e04-90d1-e3f7b6131536
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1341420587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1341420587
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2761684158
Short name T687
Test name
Test status
Simulation time 70254221 ps
CPU time 0.91 seconds
Started Jun 07 08:09:31 PM PDT 24
Finished Jun 07 08:09:35 PM PDT 24
Peak memory 206544 kb
Host smart-dcd6d5a8-48be-427a-a394-9a991e1e27f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761684158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2761684158
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.606349255
Short name T292
Test name
Test status
Simulation time 2848209941 ps
CPU time 18.93 seconds
Started Jun 07 08:09:28 PM PDT 24
Finished Jun 07 08:09:51 PM PDT 24
Peak memory 216104 kb
Host smart-b98af635-4b90-4e94-9a0e-f69601d89708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606349255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.606349255
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.4172858268
Short name T887
Test name
Test status
Simulation time 1737176617 ps
CPU time 9.01 seconds
Started Jun 07 08:09:27 PM PDT 24
Finished Jun 07 08:09:40 PM PDT 24
Peak memory 216092 kb
Host smart-9bc3959e-7b89-48e5-abd6-16d1a97d190d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172858268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.4172858268
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2290284933
Short name T562
Test name
Test status
Simulation time 87536194 ps
CPU time 0.77 seconds
Started Jun 07 08:09:28 PM PDT 24
Finished Jun 07 08:09:33 PM PDT 24
Peak memory 205644 kb
Host smart-790a9543-3c6b-4e1f-b0c8-d0ac905551c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290284933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2290284933
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.778753705
Short name T634
Test name
Test status
Simulation time 67172263 ps
CPU time 0.77 seconds
Started Jun 07 08:09:25 PM PDT 24
Finished Jun 07 08:09:30 PM PDT 24
Peak memory 205520 kb
Host smart-1b65beca-0b5b-4e66-b533-52e25b2caf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778753705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.778753705
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.377234968
Short name T149
Test name
Test status
Simulation time 954597991 ps
CPU time 3.64 seconds
Started Jun 07 08:09:23 PM PDT 24
Finished Jun 07 08:09:32 PM PDT 24
Peak memory 232592 kb
Host smart-0985cfd8-f87f-4efa-9788-d4bedcfa47df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377234968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.377234968
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.782761797
Short name T346
Test name
Test status
Simulation time 61536212 ps
CPU time 2.74 seconds
Started Jun 07 08:09:27 PM PDT 24
Finished Jun 07 08:09:34 PM PDT 24
Peak memory 232492 kb
Host smart-6997bd9f-e703-4af3-93ec-dbab989ffc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782761797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.782761797
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2624318269
Short name T647
Test name
Test status
Simulation time 26828593 ps
CPU time 0.76 seconds
Started Jun 07 08:09:29 PM PDT 24
Finished Jun 07 08:09:34 PM PDT 24
Peak memory 205560 kb
Host smart-8365c446-c7c0-4db7-9b1c-37461750918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624318269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2624318269
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3336735939
Short name T162
Test name
Test status
Simulation time 11389762146 ps
CPU time 104.5 seconds
Started Jun 07 08:09:33 PM PDT 24
Finished Jun 07 08:11:20 PM PDT 24
Peak memory 249436 kb
Host smart-8255d17b-d2a7-42a4-99bf-6dbeea277b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336735939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3336735939
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3287575418
Short name T902
Test name
Test status
Simulation time 11742452055 ps
CPU time 175.96 seconds
Started Jun 07 08:09:29 PM PDT 24
Finished Jun 07 08:12:29 PM PDT 24
Peak memory 265460 kb
Host smart-32749842-45bf-4e2b-9ea4-3d8fde978a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287575418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3287575418
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2195908564
Short name T465
Test name
Test status
Simulation time 1009055468 ps
CPU time 5.98 seconds
Started Jun 07 08:09:30 PM PDT 24
Finished Jun 07 08:09:40 PM PDT 24
Peak memory 224284 kb
Host smart-fda6a679-55dc-4c72-a706-8b7ea4cb3895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195908564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2195908564
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1931469104
Short name T246
Test name
Test status
Simulation time 1310696019 ps
CPU time 13.87 seconds
Started Jun 07 08:09:31 PM PDT 24
Finished Jun 07 08:09:49 PM PDT 24
Peak memory 224264 kb
Host smart-2120deae-471f-42c0-b9fc-714c85c6be75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931469104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1931469104
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3771134520
Short name T903
Test name
Test status
Simulation time 690585231 ps
CPU time 20.64 seconds
Started Jun 07 08:09:31 PM PDT 24
Finished Jun 07 08:09:55 PM PDT 24
Peak memory 232632 kb
Host smart-31a9b2d5-3231-4c1a-b0cf-d76b0b874fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771134520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3771134520
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1604664535
Short name T519
Test name
Test status
Simulation time 363231971 ps
CPU time 0.99 seconds
Started Jun 07 08:09:30 PM PDT 24
Finished Jun 07 08:09:35 PM PDT 24
Peak memory 217592 kb
Host smart-fa2b0d56-a74c-4b62-897f-329ab64feec7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604664535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1604664535
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2474214539
Short name T274
Test name
Test status
Simulation time 5523406976 ps
CPU time 10.59 seconds
Started Jun 07 08:09:36 PM PDT 24
Finished Jun 07 08:09:49 PM PDT 24
Peak memory 232596 kb
Host smart-7cfd149e-cc27-4157-8aa5-8b8c6bb0cda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474214539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2474214539
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2064874855
Short name T396
Test name
Test status
Simulation time 3560485654 ps
CPU time 4.04 seconds
Started Jun 07 08:09:30 PM PDT 24
Finished Jun 07 08:09:38 PM PDT 24
Peak memory 224380 kb
Host smart-5459f911-9d90-46b7-b331-c8affb6fe74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064874855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2064874855
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3290345310
Short name T945
Test name
Test status
Simulation time 573306372 ps
CPU time 5.02 seconds
Started Jun 07 08:09:29 PM PDT 24
Finished Jun 07 08:09:38 PM PDT 24
Peak memory 222804 kb
Host smart-50e7f04b-8c39-4162-a41d-af7d67a0f7ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3290345310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3290345310
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1159769879
Short name T790
Test name
Test status
Simulation time 15743661971 ps
CPU time 21.4 seconds
Started Jun 07 08:09:32 PM PDT 24
Finished Jun 07 08:09:57 PM PDT 24
Peak memory 216088 kb
Host smart-55d7dd23-4063-4300-96fb-cde5e6a7d789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159769879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1159769879
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1632756525
Short name T322
Test name
Test status
Simulation time 944859318 ps
CPU time 5.83 seconds
Started Jun 07 08:09:29 PM PDT 24
Finished Jun 07 08:09:39 PM PDT 24
Peak memory 215920 kb
Host smart-5d3361e3-aae1-499f-8ac4-eb3b43db78b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632756525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1632756525
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3815696626
Short name T381
Test name
Test status
Simulation time 66930073 ps
CPU time 1.56 seconds
Started Jun 07 08:09:37 PM PDT 24
Finished Jun 07 08:09:40 PM PDT 24
Peak memory 215984 kb
Host smart-5cdcfd3c-dd46-4ebc-9a09-14dfa9cc469a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815696626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3815696626
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1718453072
Short name T950
Test name
Test status
Simulation time 53178776 ps
CPU time 0.9 seconds
Started Jun 07 08:09:28 PM PDT 24
Finished Jun 07 08:09:33 PM PDT 24
Peak memory 206088 kb
Host smart-1c12535d-dc2d-4c3d-bcb5-4268e4240bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718453072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1718453072
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1698365320
Short name T472
Test name
Test status
Simulation time 1161992481 ps
CPU time 5.89 seconds
Started Jun 07 08:09:29 PM PDT 24
Finished Jun 07 08:09:39 PM PDT 24
Peak memory 224336 kb
Host smart-a2098cc0-f08a-4111-b8ba-f42fd5bf8d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698365320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1698365320
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.397427397
Short name T339
Test name
Test status
Simulation time 22871825 ps
CPU time 0.74 seconds
Started Jun 07 08:09:39 PM PDT 24
Finished Jun 07 08:09:42 PM PDT 24
Peak memory 205184 kb
Host smart-18012720-ef1f-45d7-927a-1862d759911f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397427397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.397427397
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3604091138
Short name T612
Test name
Test status
Simulation time 210396607 ps
CPU time 2.7 seconds
Started Jun 07 08:09:38 PM PDT 24
Finished Jun 07 08:09:42 PM PDT 24
Peak memory 232580 kb
Host smart-4f8e4a19-0b99-4242-9eb7-22b00bab01ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604091138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3604091138
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.626080462
Short name T779
Test name
Test status
Simulation time 23999940 ps
CPU time 0.78 seconds
Started Jun 07 08:09:30 PM PDT 24
Finished Jun 07 08:09:35 PM PDT 24
Peak memory 206540 kb
Host smart-0dc60bb1-a0b1-4849-b8be-bc3d3b6b880b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626080462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.626080462
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.563912906
Short name T621
Test name
Test status
Simulation time 24256321856 ps
CPU time 25.06 seconds
Started Jun 07 08:09:37 PM PDT 24
Finished Jun 07 08:10:04 PM PDT 24
Peak memory 239108 kb
Host smart-bd53f320-746d-4eee-bec1-fb5846413eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563912906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.563912906
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1342174109
Short name T850
Test name
Test status
Simulation time 104039840674 ps
CPU time 199.61 seconds
Started Jun 07 08:09:39 PM PDT 24
Finished Jun 07 08:13:01 PM PDT 24
Peak memory 252196 kb
Host smart-c58a286e-06f0-43b5-93b3-8b3c3d664f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342174109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1342174109
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.244591543
Short name T222
Test name
Test status
Simulation time 5863042648 ps
CPU time 119.99 seconds
Started Jun 07 08:09:39 PM PDT 24
Finished Jun 07 08:11:41 PM PDT 24
Peak memory 250388 kb
Host smart-ee2729fc-af11-4a19-8606-488128e7206a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244591543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.244591543
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3053950375
Short name T764
Test name
Test status
Simulation time 5529341024 ps
CPU time 32.21 seconds
Started Jun 07 08:09:36 PM PDT 24
Finished Jun 07 08:10:10 PM PDT 24
Peak memory 255060 kb
Host smart-5951fb51-c89c-4959-999e-c07c076d6e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053950375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3053950375
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3298749356
Short name T452
Test name
Test status
Simulation time 614790422 ps
CPU time 6.53 seconds
Started Jun 07 08:09:38 PM PDT 24
Finished Jun 07 08:09:47 PM PDT 24
Peak memory 232424 kb
Host smart-fe99b6c3-df79-4690-b89c-2423869367b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298749356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3298749356
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.58792428
Short name T604
Test name
Test status
Simulation time 73927290 ps
CPU time 2.27 seconds
Started Jun 07 08:09:38 PM PDT 24
Finished Jun 07 08:09:43 PM PDT 24
Peak memory 222872 kb
Host smart-114fd501-b016-4c9c-ba27-f22b854d2906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58792428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.58792428
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3956432120
Short name T454
Test name
Test status
Simulation time 27021664 ps
CPU time 1.07 seconds
Started Jun 07 08:09:28 PM PDT 24
Finished Jun 07 08:09:34 PM PDT 24
Peak memory 216296 kb
Host smart-28954a88-eaaf-4ccc-997b-2473faf0964a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956432120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3956432120
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3860927470
Short name T570
Test name
Test status
Simulation time 224811548 ps
CPU time 2.48 seconds
Started Jun 07 08:09:38 PM PDT 24
Finished Jun 07 08:09:43 PM PDT 24
Peak memory 224180 kb
Host smart-01563581-36fb-4d7a-8050-353c1f99f7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860927470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3860927470
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3097562859
Short name T872
Test name
Test status
Simulation time 599890253 ps
CPU time 2.26 seconds
Started Jun 07 08:09:39 PM PDT 24
Finished Jun 07 08:09:44 PM PDT 24
Peak memory 222924 kb
Host smart-481a49de-6377-4ad1-b5e3-1e43bb62abac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097562859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3097562859
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.4159111552
Short name T584
Test name
Test status
Simulation time 2476228249 ps
CPU time 6.1 seconds
Started Jun 07 08:09:38 PM PDT 24
Finished Jun 07 08:09:46 PM PDT 24
Peak memory 222824 kb
Host smart-38451abe-1717-4d43-bf2d-16a588951188
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4159111552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.4159111552
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3556457941
Short name T698
Test name
Test status
Simulation time 10064109250 ps
CPU time 29.4 seconds
Started Jun 07 08:09:31 PM PDT 24
Finished Jun 07 08:10:04 PM PDT 24
Peak memory 216076 kb
Host smart-cb0d8375-58f1-49ef-8561-26bb0c310ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556457941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3556457941
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3957149246
Short name T733
Test name
Test status
Simulation time 368835222 ps
CPU time 1.5 seconds
Started Jun 07 08:09:28 PM PDT 24
Finished Jun 07 08:09:34 PM PDT 24
Peak memory 207484 kb
Host smart-ed061c2d-a82d-4da5-a9e0-1d6c6e954fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957149246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3957149246
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2471101487
Short name T579
Test name
Test status
Simulation time 94667766 ps
CPU time 1.52 seconds
Started Jun 07 08:09:30 PM PDT 24
Finished Jun 07 08:09:35 PM PDT 24
Peak memory 215992 kb
Host smart-84c2d609-f4e8-43a9-a510-260b9ec22535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471101487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2471101487
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1335473259
Short name T919
Test name
Test status
Simulation time 108565882 ps
CPU time 0.99 seconds
Started Jun 07 08:09:28 PM PDT 24
Finished Jun 07 08:09:33 PM PDT 24
Peak memory 205616 kb
Host smart-1b7a3ef7-a501-4740-bffa-087dd3b190de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335473259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1335473259
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.773993600
Short name T564
Test name
Test status
Simulation time 1056617483 ps
CPU time 6.66 seconds
Started Jun 07 08:09:42 PM PDT 24
Finished Jun 07 08:09:50 PM PDT 24
Peak memory 240076 kb
Host smart-0f42a695-c2dc-440c-98b3-d0b000643fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773993600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.773993600
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.4118558018
Short name T528
Test name
Test status
Simulation time 12963188 ps
CPU time 0.72 seconds
Started Jun 07 08:09:47 PM PDT 24
Finished Jun 07 08:09:50 PM PDT 24
Peak memory 204516 kb
Host smart-efef1b19-801e-4896-ac8b-adff60a033fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118558018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
4118558018
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2483708019
Short name T91
Test name
Test status
Simulation time 366825224 ps
CPU time 2.31 seconds
Started Jun 07 08:09:39 PM PDT 24
Finished Jun 07 08:09:43 PM PDT 24
Peak memory 224320 kb
Host smart-6b30bcf2-e8eb-445b-a2c5-7ee07d0924c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483708019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2483708019
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.232019409
Short name T739
Test name
Test status
Simulation time 48655309 ps
CPU time 0.78 seconds
Started Jun 07 08:09:41 PM PDT 24
Finished Jun 07 08:09:44 PM PDT 24
Peak memory 206212 kb
Host smart-875f2106-12ba-4b98-8066-7d1dc5189a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232019409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.232019409
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1015535901
Short name T414
Test name
Test status
Simulation time 29366000279 ps
CPU time 76.28 seconds
Started Jun 07 08:09:46 PM PDT 24
Finished Jun 07 08:11:05 PM PDT 24
Peak memory 256408 kb
Host smart-58f321d6-7131-421e-9f7a-f47f85610deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015535901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1015535901
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3978901695
Short name T747
Test name
Test status
Simulation time 3662616481 ps
CPU time 11.94 seconds
Started Jun 07 08:09:45 PM PDT 24
Finished Jun 07 08:09:59 PM PDT 24
Peak memory 217384 kb
Host smart-a3995c8e-0dab-4939-b0aa-5355723e941f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978901695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3978901695
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4270516369
Short name T682
Test name
Test status
Simulation time 208637491 ps
CPU time 7.6 seconds
Started Jun 07 08:09:40 PM PDT 24
Finished Jun 07 08:09:50 PM PDT 24
Peak memory 232608 kb
Host smart-e66f9813-0cd7-45e7-a7ae-c8a19a4d698a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270516369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4270516369
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.963159520
Short name T448
Test name
Test status
Simulation time 1351562289 ps
CPU time 3.29 seconds
Started Jun 07 08:09:36 PM PDT 24
Finished Jun 07 08:09:41 PM PDT 24
Peak memory 224304 kb
Host smart-78922345-1616-4c5e-8a62-24ec4ede2463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963159520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.963159520
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2364701195
Short name T392
Test name
Test status
Simulation time 298036877 ps
CPU time 3.28 seconds
Started Jun 07 08:09:37 PM PDT 24
Finished Jun 07 08:09:42 PM PDT 24
Peak memory 232544 kb
Host smart-30c16929-dec8-4287-b77f-53e594b893f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364701195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2364701195
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2715786094
Short name T27
Test name
Test status
Simulation time 44838919 ps
CPU time 1.12 seconds
Started Jun 07 08:09:39 PM PDT 24
Finished Jun 07 08:09:43 PM PDT 24
Peak memory 216392 kb
Host smart-6a507b5d-a8f9-42bf-94c3-101b0d7506c8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715786094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2715786094
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3385049082
Short name T389
Test name
Test status
Simulation time 596273917 ps
CPU time 6.55 seconds
Started Jun 07 08:09:38 PM PDT 24
Finished Jun 07 08:09:47 PM PDT 24
Peak memory 232532 kb
Host smart-c8c7fd1f-a741-4ae8-aad7-ea46b98d7b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385049082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3385049082
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1331105036
Short name T176
Test name
Test status
Simulation time 9776483594 ps
CPU time 17.39 seconds
Started Jun 07 08:09:37 PM PDT 24
Finished Jun 07 08:09:56 PM PDT 24
Peak memory 240012 kb
Host smart-c1f13a34-2ca4-40ca-a8fd-bb3b9aa4015e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331105036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1331105036
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3064914618
Short name T598
Test name
Test status
Simulation time 5785645942 ps
CPU time 7.55 seconds
Started Jun 07 08:09:44 PM PDT 24
Finished Jun 07 08:09:53 PM PDT 24
Peak memory 218728 kb
Host smart-5389cddb-de88-4a53-a53b-2ce7d18c3245
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3064914618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3064914618
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.794548007
Short name T577
Test name
Test status
Simulation time 3704263458 ps
CPU time 29.84 seconds
Started Jun 07 08:09:38 PM PDT 24
Finished Jun 07 08:10:10 PM PDT 24
Peak memory 219384 kb
Host smart-c3e4f2b9-7268-4709-8628-ca41d5b3a28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794548007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.794548007
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2364362588
Short name T388
Test name
Test status
Simulation time 1536009047 ps
CPU time 6.15 seconds
Started Jun 07 08:09:38 PM PDT 24
Finished Jun 07 08:09:46 PM PDT 24
Peak memory 216016 kb
Host smart-d7589a29-4193-4f03-95eb-63ff0804c6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364362588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2364362588
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1205544739
Short name T340
Test name
Test status
Simulation time 37736946 ps
CPU time 0.71 seconds
Started Jun 07 08:09:39 PM PDT 24
Finished Jun 07 08:09:42 PM PDT 24
Peak memory 205232 kb
Host smart-504772b3-4fef-435b-889d-a9f5df2a1654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205544739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1205544739
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2210994920
Short name T491
Test name
Test status
Simulation time 144093481 ps
CPU time 0.92 seconds
Started Jun 07 08:09:39 PM PDT 24
Finished Jun 07 08:09:42 PM PDT 24
Peak memory 205560 kb
Host smart-72647d75-be3e-4351-93f9-4a3ea11e5ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210994920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2210994920
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1926775180
Short name T48
Test name
Test status
Simulation time 623553714 ps
CPU time 2.41 seconds
Started Jun 07 08:09:37 PM PDT 24
Finished Jun 07 08:09:41 PM PDT 24
Peak memory 224288 kb
Host smart-998eeb97-4aaf-4600-be60-62f32cbfdee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926775180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1926775180
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3520070430
Short name T953
Test name
Test status
Simulation time 105177832 ps
CPU time 0.77 seconds
Started Jun 07 08:09:48 PM PDT 24
Finished Jun 07 08:09:52 PM PDT 24
Peak memory 205180 kb
Host smart-2ec9dca7-6a8f-456d-b45d-5d2bffb5fffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520070430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3520070430
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.574005179
Short name T495
Test name
Test status
Simulation time 92976576 ps
CPU time 3.12 seconds
Started Jun 07 08:09:45 PM PDT 24
Finished Jun 07 08:09:49 PM PDT 24
Peak memory 232488 kb
Host smart-441365d4-997e-4c87-a099-317129735bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574005179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.574005179
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2433183785
Short name T961
Test name
Test status
Simulation time 57589923 ps
CPU time 0.77 seconds
Started Jun 07 08:09:48 PM PDT 24
Finished Jun 07 08:09:52 PM PDT 24
Peak memory 205548 kb
Host smart-54a91b81-5417-4675-8476-10a4a42cdcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433183785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2433183785
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3058212491
Short name T252
Test name
Test status
Simulation time 56386934858 ps
CPU time 101.87 seconds
Started Jun 07 08:09:44 PM PDT 24
Finished Jun 07 08:11:27 PM PDT 24
Peak memory 254588 kb
Host smart-ba31a575-3697-448f-a051-89ac6a6d25b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058212491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3058212491
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.802519959
Short name T150
Test name
Test status
Simulation time 3272486793 ps
CPU time 15.19 seconds
Started Jun 07 08:09:48 PM PDT 24
Finished Jun 07 08:10:06 PM PDT 24
Peak memory 240760 kb
Host smart-d93c7aab-3d12-4d08-8e53-109332729ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802519959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.802519959
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.4125894712
Short name T461
Test name
Test status
Simulation time 39104895753 ps
CPU time 124.49 seconds
Started Jun 07 08:09:46 PM PDT 24
Finished Jun 07 08:11:52 PM PDT 24
Peak memory 240672 kb
Host smart-3419bb64-e527-464a-a41d-a258f3e3e714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125894712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.4125894712
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3663345483
Short name T281
Test name
Test status
Simulation time 3945109317 ps
CPU time 23.19 seconds
Started Jun 07 08:09:49 PM PDT 24
Finished Jun 07 08:10:15 PM PDT 24
Peak memory 224384 kb
Host smart-81ae0765-1b3c-4e93-8eed-a61b72b3ebc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663345483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3663345483
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2413891766
Short name T941
Test name
Test status
Simulation time 121390190 ps
CPU time 2.73 seconds
Started Jun 07 08:09:44 PM PDT 24
Finished Jun 07 08:09:49 PM PDT 24
Peak memory 224236 kb
Host smart-d19199b6-d61f-4399-ad8a-cf78822b4dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413891766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2413891766
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1006520690
Short name T614
Test name
Test status
Simulation time 385742849 ps
CPU time 6.88 seconds
Started Jun 07 08:09:46 PM PDT 24
Finished Jun 07 08:09:55 PM PDT 24
Peak memory 224316 kb
Host smart-83bb7961-9223-42ae-aca3-e2f66b925d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006520690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1006520690
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1135297148
Short name T336
Test name
Test status
Simulation time 94404246 ps
CPU time 1.02 seconds
Started Jun 07 08:09:45 PM PDT 24
Finished Jun 07 08:09:47 PM PDT 24
Peak memory 217596 kb
Host smart-826beaa8-d58c-4a53-bc9b-2429c0b9c916
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135297148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1135297148
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1238567010
Short name T181
Test name
Test status
Simulation time 178909959 ps
CPU time 4.33 seconds
Started Jun 07 08:09:46 PM PDT 24
Finished Jun 07 08:09:53 PM PDT 24
Peak memory 232500 kb
Host smart-21d74b8e-2b37-4d12-a79d-e4aee2828be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238567010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1238567010
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1306368724
Short name T413
Test name
Test status
Simulation time 658243031 ps
CPU time 2.7 seconds
Started Jun 07 08:09:53 PM PDT 24
Finished Jun 07 08:09:57 PM PDT 24
Peak memory 224312 kb
Host smart-f5babae5-495e-44ae-b34a-7a3de0e1e712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306368724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1306368724
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2919245342
Short name T132
Test name
Test status
Simulation time 1408056212 ps
CPU time 12.75 seconds
Started Jun 07 08:09:45 PM PDT 24
Finished Jun 07 08:09:59 PM PDT 24
Peak memory 222816 kb
Host smart-1e856c8d-d588-4b82-8108-b1b183d9b94d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2919245342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2919245342
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4094140652
Short name T42
Test name
Test status
Simulation time 127442249473 ps
CPU time 307.36 seconds
Started Jun 07 08:09:48 PM PDT 24
Finished Jun 07 08:14:59 PM PDT 24
Peak memory 249068 kb
Host smart-b0fea802-6162-4d31-a23c-bee063026b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094140652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4094140652
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.4175728420
Short name T819
Test name
Test status
Simulation time 738570590 ps
CPU time 5.49 seconds
Started Jun 07 08:09:47 PM PDT 24
Finished Jun 07 08:09:55 PM PDT 24
Peak memory 216056 kb
Host smart-837e0c76-dbc9-4eb5-9ef0-eb4e3002de32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175728420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4175728420
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1434809644
Short name T538
Test name
Test status
Simulation time 473733832 ps
CPU time 3.72 seconds
Started Jun 07 08:09:48 PM PDT 24
Finished Jun 07 08:09:55 PM PDT 24
Peak memory 216036 kb
Host smart-74c240b7-6ca8-4b61-8bb8-6c75558d16a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434809644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1434809644
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2244356323
Short name T714
Test name
Test status
Simulation time 70249149 ps
CPU time 1.72 seconds
Started Jun 07 08:09:48 PM PDT 24
Finished Jun 07 08:09:52 PM PDT 24
Peak memory 215956 kb
Host smart-ea201712-130b-4243-98a0-b5a9d966068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244356323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2244356323
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1290973985
Short name T906
Test name
Test status
Simulation time 281258070 ps
CPU time 0.87 seconds
Started Jun 07 08:09:53 PM PDT 24
Finished Jun 07 08:09:55 PM PDT 24
Peak memory 205572 kb
Host smart-bd12f9af-7bbe-48c4-81e5-62c59d432c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290973985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1290973985
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.40410702
Short name T966
Test name
Test status
Simulation time 1923929430 ps
CPU time 7.05 seconds
Started Jun 07 08:09:46 PM PDT 24
Finished Jun 07 08:09:56 PM PDT 24
Peak memory 224248 kb
Host smart-5b55ad1a-afd0-4df0-93e9-91885afe22e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40410702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.40410702
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2174132303
Short name T683
Test name
Test status
Simulation time 157522859 ps
CPU time 0.72 seconds
Started Jun 07 08:09:54 PM PDT 24
Finished Jun 07 08:09:57 PM PDT 24
Peak memory 205144 kb
Host smart-47ea2b21-3d2e-4aea-92cf-d35ac17165af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174132303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2174132303
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.72416882
Short name T485
Test name
Test status
Simulation time 1760966850 ps
CPU time 5.15 seconds
Started Jun 07 08:09:48 PM PDT 24
Finished Jun 07 08:09:56 PM PDT 24
Peak memory 232544 kb
Host smart-3d47bc3d-9267-4f2e-81d4-1f1f6bbf6084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72416882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.72416882
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3597718
Short name T650
Test name
Test status
Simulation time 31435578 ps
CPU time 0.75 seconds
Started Jun 07 08:09:48 PM PDT 24
Finished Jun 07 08:09:52 PM PDT 24
Peak memory 205524 kb
Host smart-1c584b56-9694-4f0f-aef8-8f6d7cea4819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3597718
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.183361471
Short name T219
Test name
Test status
Simulation time 551786241388 ps
CPU time 577.29 seconds
Started Jun 07 08:09:47 PM PDT 24
Finished Jun 07 08:19:26 PM PDT 24
Peak memory 256972 kb
Host smart-b61f99f8-a1b0-4d07-a1aa-7ff43c1f5189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183361471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.183361471
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1933941911
Short name T751
Test name
Test status
Simulation time 15680260084 ps
CPU time 158.56 seconds
Started Jun 07 08:09:45 PM PDT 24
Finished Jun 07 08:12:26 PM PDT 24
Peak memory 249132 kb
Host smart-7f7d59f8-7796-4402-945d-22e0e469b455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933941911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1933941911
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1418232611
Short name T565
Test name
Test status
Simulation time 215649468 ps
CPU time 6.41 seconds
Started Jun 07 08:09:53 PM PDT 24
Finished Jun 07 08:10:01 PM PDT 24
Peak memory 235288 kb
Host smart-4854b429-95cd-4842-9344-7abce4b8d656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418232611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1418232611
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.449207925
Short name T795
Test name
Test status
Simulation time 3295284555 ps
CPU time 17.58 seconds
Started Jun 07 08:09:53 PM PDT 24
Finished Jun 07 08:10:13 PM PDT 24
Peak memory 232568 kb
Host smart-20e27a19-a7d3-4eab-961e-f2930dafe531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449207925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.449207925
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1434304006
Short name T92
Test name
Test status
Simulation time 454871084 ps
CPU time 5.84 seconds
Started Jun 07 08:09:48 PM PDT 24
Finished Jun 07 08:09:57 PM PDT 24
Peak memory 240296 kb
Host smart-4d24f3ec-0d13-4290-b6b0-7eb02be8c85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434304006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1434304006
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.508447019
Short name T737
Test name
Test status
Simulation time 61329866 ps
CPU time 1.17 seconds
Started Jun 07 08:09:49 PM PDT 24
Finished Jun 07 08:09:53 PM PDT 24
Peak memory 216356 kb
Host smart-f7ae6426-6623-4d3d-adb8-1df4a97ee6b0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508447019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.508447019
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4292734018
Short name T458
Test name
Test status
Simulation time 12419029798 ps
CPU time 14.1 seconds
Started Jun 07 08:09:53 PM PDT 24
Finished Jun 07 08:10:10 PM PDT 24
Peak memory 248672 kb
Host smart-15990899-df9e-46e1-bfc9-4d72e4997257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292734018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4292734018
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1026289378
Short name T628
Test name
Test status
Simulation time 24840272232 ps
CPU time 25.13 seconds
Started Jun 07 08:09:47 PM PDT 24
Finished Jun 07 08:10:15 PM PDT 24
Peak memory 233460 kb
Host smart-677bca4b-1d18-4dd8-bbfb-1c2b97893152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026289378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1026289378
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2517351902
Short name T362
Test name
Test status
Simulation time 750944861 ps
CPU time 7.83 seconds
Started Jun 07 08:09:48 PM PDT 24
Finished Jun 07 08:09:59 PM PDT 24
Peak memory 218648 kb
Host smart-64a8db1f-0980-43c2-98ce-036c95b53b69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2517351902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2517351902
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1929946848
Short name T827
Test name
Test status
Simulation time 154998810 ps
CPU time 0.93 seconds
Started Jun 07 08:09:55 PM PDT 24
Finished Jun 07 08:09:59 PM PDT 24
Peak memory 206564 kb
Host smart-4558510d-77a8-4157-b99a-cb101d80256c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929946848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1929946848
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1862373398
Short name T916
Test name
Test status
Simulation time 10681029263 ps
CPU time 51.47 seconds
Started Jun 07 08:09:45 PM PDT 24
Finished Jun 07 08:10:38 PM PDT 24
Peak memory 216200 kb
Host smart-f4363a33-00a7-4878-bcdd-80bf9dc6839c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862373398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1862373398
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.530616497
Short name T366
Test name
Test status
Simulation time 6541879747 ps
CPU time 4.13 seconds
Started Jun 07 08:09:48 PM PDT 24
Finished Jun 07 08:09:55 PM PDT 24
Peak memory 215924 kb
Host smart-79a84eac-6681-4eb3-ac09-8c5958ef7872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530616497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.530616497
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1443300715
Short name T689
Test name
Test status
Simulation time 24273674 ps
CPU time 1.04 seconds
Started Jun 07 08:09:46 PM PDT 24
Finished Jun 07 08:09:49 PM PDT 24
Peak memory 207268 kb
Host smart-68dd59fc-671e-4eca-b3fe-4edfe17ec1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443300715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1443300715
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.988117063
Short name T410
Test name
Test status
Simulation time 90241699 ps
CPU time 0.82 seconds
Started Jun 07 08:09:53 PM PDT 24
Finished Jun 07 08:09:55 PM PDT 24
Peak memory 205572 kb
Host smart-f9680631-b142-4a19-8312-a0245c551e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988117063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.988117063
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.468379526
Short name T526
Test name
Test status
Simulation time 34744004749 ps
CPU time 23.15 seconds
Started Jun 07 08:09:47 PM PDT 24
Finished Jun 07 08:10:13 PM PDT 24
Peak memory 232600 kb
Host smart-3ae34c01-3117-4e3c-b59f-323d64c67634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468379526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.468379526
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.835585408
Short name T390
Test name
Test status
Simulation time 17099853 ps
CPU time 0.75 seconds
Started Jun 07 08:09:53 PM PDT 24
Finished Jun 07 08:09:56 PM PDT 24
Peak memory 205180 kb
Host smart-3a3a506c-9c7a-4251-9e91-c1759219669d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835585408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.835585408
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1261676447
Short name T871
Test name
Test status
Simulation time 3032872340 ps
CPU time 12.51 seconds
Started Jun 07 08:09:55 PM PDT 24
Finished Jun 07 08:10:11 PM PDT 24
Peak memory 232588 kb
Host smart-f5937f54-e25a-4590-8428-c89d7769f9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261676447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1261676447
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3304470167
Short name T8
Test name
Test status
Simulation time 87454443 ps
CPU time 0.77 seconds
Started Jun 07 08:09:56 PM PDT 24
Finished Jun 07 08:09:59 PM PDT 24
Peak memory 205536 kb
Host smart-d9605635-d721-47ed-bab7-f7c2fb0de3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304470167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3304470167
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3245021427
Short name T856
Test name
Test status
Simulation time 6060793010 ps
CPU time 78.4 seconds
Started Jun 07 08:09:57 PM PDT 24
Finished Jun 07 08:11:18 PM PDT 24
Peak memory 249040 kb
Host smart-7e1c2e4f-3650-45c6-920e-e616007e04c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245021427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3245021427
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2916526162
Short name T230
Test name
Test status
Simulation time 698258421550 ps
CPU time 500.51 seconds
Started Jun 07 08:09:54 PM PDT 24
Finished Jun 07 08:18:17 PM PDT 24
Peak memory 251464 kb
Host smart-26b03107-77a5-41c4-a75a-67e3b067ecaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916526162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2916526162
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3596594723
Short name T128
Test name
Test status
Simulation time 154336169338 ps
CPU time 152.39 seconds
Started Jun 07 08:09:55 PM PDT 24
Finished Jun 07 08:12:30 PM PDT 24
Peak memory 249052 kb
Host smart-02c4857b-6cee-4fb7-b74b-80eeed04a595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596594723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3596594723
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2131003972
Short name T539
Test name
Test status
Simulation time 765629084 ps
CPU time 7.23 seconds
Started Jun 07 08:09:56 PM PDT 24
Finished Jun 07 08:10:06 PM PDT 24
Peak memory 224316 kb
Host smart-2e4aeafa-5d1e-408d-aeea-a0685f769838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131003972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2131003972
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.423867100
Short name T182
Test name
Test status
Simulation time 443274550 ps
CPU time 5.1 seconds
Started Jun 07 08:09:56 PM PDT 24
Finished Jun 07 08:10:04 PM PDT 24
Peak memory 232568 kb
Host smart-2821a727-36ab-4978-881d-50b2b8af328e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423867100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.423867100
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.410305029
Short name T373
Test name
Test status
Simulation time 187309754 ps
CPU time 6.17 seconds
Started Jun 07 08:09:55 PM PDT 24
Finished Jun 07 08:10:04 PM PDT 24
Peak memory 232592 kb
Host smart-76020306-3158-4b43-a999-765f13c54d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410305029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.410305029
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1027543593
Short name T922
Test name
Test status
Simulation time 54734769 ps
CPU time 1.09 seconds
Started Jun 07 08:09:55 PM PDT 24
Finished Jun 07 08:09:59 PM PDT 24
Peak memory 217568 kb
Host smart-87382ad0-cd1c-493f-9c1f-3c04e8fdbeeb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027543593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1027543593
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2603064217
Short name T463
Test name
Test status
Simulation time 2127474992 ps
CPU time 12.73 seconds
Started Jun 07 08:09:52 PM PDT 24
Finished Jun 07 08:10:07 PM PDT 24
Peak memory 240672 kb
Host smart-a574917b-e0aa-4a90-a826-5bb21a906f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603064217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2603064217
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2403572340
Short name T82
Test name
Test status
Simulation time 12171854536 ps
CPU time 34.5 seconds
Started Jun 07 08:09:54 PM PDT 24
Finished Jun 07 08:10:30 PM PDT 24
Peak memory 232608 kb
Host smart-6faad33f-353f-4c70-a20e-41addd7e7e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403572340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2403572340
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1868467317
Short name T622
Test name
Test status
Simulation time 106322426 ps
CPU time 4.31 seconds
Started Jun 07 08:09:56 PM PDT 24
Finished Jun 07 08:10:03 PM PDT 24
Peak memory 222784 kb
Host smart-d091226c-8397-4eeb-a9e2-fc3ef0fa942b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1868467317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1868467317
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3947975306
Short name T482
Test name
Test status
Simulation time 23087831570 ps
CPU time 33.27 seconds
Started Jun 07 08:09:56 PM PDT 24
Finished Jun 07 08:10:32 PM PDT 24
Peak memory 216088 kb
Host smart-c5f29973-2ea3-4334-9925-c15b8295cdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947975306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3947975306
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.310301223
Short name T667
Test name
Test status
Simulation time 5500783974 ps
CPU time 16.04 seconds
Started Jun 07 08:09:56 PM PDT 24
Finished Jun 07 08:10:14 PM PDT 24
Peak memory 216164 kb
Host smart-9242c09c-8eb2-43d6-b988-e0c524c4c32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310301223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.310301223
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3518708951
Short name T619
Test name
Test status
Simulation time 128844847 ps
CPU time 1.28 seconds
Started Jun 07 08:09:53 PM PDT 24
Finished Jun 07 08:09:57 PM PDT 24
Peak memory 216040 kb
Host smart-bb1b167f-8972-4031-8c83-037a93ec41bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518708951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3518708951
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.159786576
Short name T891
Test name
Test status
Simulation time 565257195 ps
CPU time 0.89 seconds
Started Jun 07 08:10:01 PM PDT 24
Finished Jun 07 08:10:03 PM PDT 24
Peak memory 205600 kb
Host smart-a53f5868-214b-4387-90c9-da3e809ab749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159786576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.159786576
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1552054539
Short name T696
Test name
Test status
Simulation time 312697203 ps
CPU time 2.88 seconds
Started Jun 07 08:09:54 PM PDT 24
Finished Jun 07 08:10:00 PM PDT 24
Peak memory 223884 kb
Host smart-60592e7b-d746-449c-95c6-c7a1bb38c37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552054539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1552054539
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.801248100
Short name T533
Test name
Test status
Simulation time 26047388 ps
CPU time 0.73 seconds
Started Jun 07 08:10:06 PM PDT 24
Finished Jun 07 08:10:10 PM PDT 24
Peak memory 205060 kb
Host smart-8f0dd160-5913-412a-8280-407e1960c9f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801248100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.801248100
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.356607676
Short name T355
Test name
Test status
Simulation time 2986799532 ps
CPU time 8.68 seconds
Started Jun 07 08:10:00 PM PDT 24
Finished Jun 07 08:10:11 PM PDT 24
Peak memory 224364 kb
Host smart-4474534e-6892-4960-aa3e-3184be7ed339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356607676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.356607676
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.983482199
Short name T798
Test name
Test status
Simulation time 35643750 ps
CPU time 0.78 seconds
Started Jun 07 08:09:56 PM PDT 24
Finished Jun 07 08:09:59 PM PDT 24
Peak memory 205224 kb
Host smart-f2e95001-d15c-4b17-a64b-02fc87b18529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983482199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.983482199
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2601860075
Short name T963
Test name
Test status
Simulation time 19076383687 ps
CPU time 61.45 seconds
Started Jun 07 08:10:07 PM PDT 24
Finished Jun 07 08:11:12 PM PDT 24
Peak memory 249792 kb
Host smart-af996fb5-ac11-4ad5-8d2e-d1aa305d4583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601860075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2601860075
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4100378293
Short name T391
Test name
Test status
Simulation time 25253072692 ps
CPU time 30.8 seconds
Started Jun 07 08:10:02 PM PDT 24
Finished Jun 07 08:10:36 PM PDT 24
Peak memory 224412 kb
Host smart-6c2d4d56-d9ff-4cf1-ba7a-f64919fcb1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100378293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4100378293
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1904336050
Short name T294
Test name
Test status
Simulation time 17157067756 ps
CPU time 44.56 seconds
Started Jun 07 08:10:02 PM PDT 24
Finished Jun 07 08:10:49 PM PDT 24
Peak memory 224412 kb
Host smart-0a5462e0-b3b0-4980-8016-1b57549fe0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904336050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1904336050
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_intercept.4212620724
Short name T426
Test name
Test status
Simulation time 3558778439 ps
CPU time 24.65 seconds
Started Jun 07 08:10:01 PM PDT 24
Finished Jun 07 08:10:27 PM PDT 24
Peak memory 224412 kb
Host smart-02f8b83e-8154-46bf-8703-496e69a77ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212620724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.4212620724
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1095816138
Short name T425
Test name
Test status
Simulation time 354602297 ps
CPU time 5.68 seconds
Started Jun 07 08:10:05 PM PDT 24
Finished Jun 07 08:10:14 PM PDT 24
Peak memory 224300 kb
Host smart-fc8f2bb3-72b2-4a77-9259-3fe2dd66bfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095816138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1095816138
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3170287836
Short name T468
Test name
Test status
Simulation time 343377232 ps
CPU time 1.09 seconds
Started Jun 07 08:09:58 PM PDT 24
Finished Jun 07 08:10:01 PM PDT 24
Peak memory 216356 kb
Host smart-608e9f1b-e6fa-4c02-baa1-3eb168b23b8f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170287836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3170287836
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2093146725
Short name T367
Test name
Test status
Simulation time 361524747 ps
CPU time 2.8 seconds
Started Jun 07 08:10:04 PM PDT 24
Finished Jun 07 08:10:10 PM PDT 24
Peak memory 224320 kb
Host smart-d741b41b-ff21-4335-ad8d-c658ba246082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093146725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2093146725
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1599466044
Short name T799
Test name
Test status
Simulation time 9651235897 ps
CPU time 8.07 seconds
Started Jun 07 08:10:02 PM PDT 24
Finished Jun 07 08:10:13 PM PDT 24
Peak memory 232656 kb
Host smart-5dac4b6c-dc36-4d33-8373-36fbc1a26dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599466044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1599466044
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3595590062
Short name T958
Test name
Test status
Simulation time 1046057743 ps
CPU time 6.95 seconds
Started Jun 07 08:10:03 PM PDT 24
Finished Jun 07 08:10:14 PM PDT 24
Peak memory 219280 kb
Host smart-09d26f07-d3aa-4d21-aa89-9c2c34f509f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3595590062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3595590062
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3596395973
Short name T147
Test name
Test status
Simulation time 9278814245 ps
CPU time 51.33 seconds
Started Jun 07 08:10:03 PM PDT 24
Finished Jun 07 08:10:58 PM PDT 24
Peak memory 249016 kb
Host smart-5439cea4-1186-47f0-a629-98e5a1c72ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596395973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3596395973
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3563850859
Short name T524
Test name
Test status
Simulation time 33602874 ps
CPU time 0.7 seconds
Started Jun 07 08:09:55 PM PDT 24
Finished Jun 07 08:09:59 PM PDT 24
Peak memory 205344 kb
Host smart-786d86ce-33d0-420a-a1b8-344d9a9427f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563850859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3563850859
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1806914516
Short name T952
Test name
Test status
Simulation time 1944031365 ps
CPU time 5.67 seconds
Started Jun 07 08:09:57 PM PDT 24
Finished Jun 07 08:10:05 PM PDT 24
Peak memory 216048 kb
Host smart-7c9265f5-8246-4cc5-9608-3feeb83266c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806914516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1806914516
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1967996956
Short name T943
Test name
Test status
Simulation time 704472550 ps
CPU time 0.95 seconds
Started Jun 07 08:09:56 PM PDT 24
Finished Jun 07 08:10:00 PM PDT 24
Peak memory 206252 kb
Host smart-07add178-0688-4110-80a4-4538f431aa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967996956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1967996956
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2164853291
Short name T913
Test name
Test status
Simulation time 26578758 ps
CPU time 0.73 seconds
Started Jun 07 08:09:56 PM PDT 24
Finished Jun 07 08:09:59 PM PDT 24
Peak memory 205612 kb
Host smart-5498a5f5-5edd-4ecc-a5c6-81d59fafcc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164853291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2164853291
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.4046791827
Short name T185
Test name
Test status
Simulation time 2762837198 ps
CPU time 10.74 seconds
Started Jun 07 08:10:03 PM PDT 24
Finished Jun 07 08:10:17 PM PDT 24
Peak memory 232568 kb
Host smart-032d54df-0bf0-4f44-8bfd-d7411f608c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046791827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4046791827
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2189201890
Short name T583
Test name
Test status
Simulation time 10595397 ps
CPU time 0.74 seconds
Started Jun 07 08:10:03 PM PDT 24
Finished Jun 07 08:10:08 PM PDT 24
Peak memory 204564 kb
Host smart-fc872054-04e8-438e-a6f5-56824adc9963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189201890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2189201890
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.209738803
Short name T9
Test name
Test status
Simulation time 250511928 ps
CPU time 3.32 seconds
Started Jun 07 08:10:04 PM PDT 24
Finished Jun 07 08:10:12 PM PDT 24
Peak memory 224304 kb
Host smart-daeeea38-cc15-43e0-8c03-de10b35c711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209738803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.209738803
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1645258231
Short name T559
Test name
Test status
Simulation time 36766032 ps
CPU time 0.8 seconds
Started Jun 07 08:10:01 PM PDT 24
Finished Jun 07 08:10:03 PM PDT 24
Peak memory 206240 kb
Host smart-688679ce-bc1c-47c7-958e-d539fff35696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645258231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1645258231
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.595895516
Short name T569
Test name
Test status
Simulation time 1443636189 ps
CPU time 28.2 seconds
Started Jun 07 08:10:05 PM PDT 24
Finished Jun 07 08:10:37 PM PDT 24
Peak memory 250332 kb
Host smart-648877ec-374a-4255-ab59-8ff824b19843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595895516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.595895516
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1892943028
Short name T221
Test name
Test status
Simulation time 103352464951 ps
CPU time 462.46 seconds
Started Jun 07 08:10:03 PM PDT 24
Finished Jun 07 08:17:49 PM PDT 24
Peak memory 255504 kb
Host smart-24b5a277-ca7d-4c56-8ff0-fbfe68fb7999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892943028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1892943028
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3002955470
Short name T947
Test name
Test status
Simulation time 130654482161 ps
CPU time 256.38 seconds
Started Jun 07 08:10:07 PM PDT 24
Finished Jun 07 08:14:27 PM PDT 24
Peak memory 252340 kb
Host smart-a7024a51-2dbe-43a0-a831-33f2b0202f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002955470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3002955470
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1257752749
Short name T955
Test name
Test status
Simulation time 1746602301 ps
CPU time 22.58 seconds
Started Jun 07 08:10:01 PM PDT 24
Finished Jun 07 08:10:26 PM PDT 24
Peak memory 240720 kb
Host smart-4b6f03a6-650a-4500-be5a-e83cd5046336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257752749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1257752749
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.339858767
Short name T890
Test name
Test status
Simulation time 795789500 ps
CPU time 11.22 seconds
Started Jun 07 08:10:03 PM PDT 24
Finished Jun 07 08:10:18 PM PDT 24
Peak memory 232516 kb
Host smart-6548443a-b0a5-43ba-8e80-8872cd66e8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339858767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.339858767
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3057844625
Short name T774
Test name
Test status
Simulation time 51845884 ps
CPU time 2.16 seconds
Started Jun 07 08:10:03 PM PDT 24
Finished Jun 07 08:10:08 PM PDT 24
Peak memory 222920 kb
Host smart-844a5f9c-f839-4761-89b2-078984f78bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057844625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3057844625
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1146725701
Short name T26
Test name
Test status
Simulation time 99167891 ps
CPU time 1.12 seconds
Started Jun 07 08:10:01 PM PDT 24
Finished Jun 07 08:10:04 PM PDT 24
Peak memory 216396 kb
Host smart-7be65d15-474d-4298-bbfe-4243c96de6d9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146725701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1146725701
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2204257144
Short name T244
Test name
Test status
Simulation time 518155783 ps
CPU time 3.8 seconds
Started Jun 07 08:10:02 PM PDT 24
Finished Jun 07 08:10:08 PM PDT 24
Peak memory 224288 kb
Host smart-a2ce098f-87c9-4e65-b316-6eb0321af18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204257144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2204257144
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.80922484
Short name T673
Test name
Test status
Simulation time 2147067885 ps
CPU time 6.07 seconds
Started Jun 07 08:10:00 PM PDT 24
Finished Jun 07 08:10:07 PM PDT 24
Peak memory 221980 kb
Host smart-f973fbc4-31c3-4fb1-8b41-6ce7f531469c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=80922484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direc
t.80922484
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2767635054
Short name T269
Test name
Test status
Simulation time 42840680991 ps
CPU time 192.75 seconds
Started Jun 07 08:10:06 PM PDT 24
Finished Jun 07 08:13:22 PM PDT 24
Peak memory 240728 kb
Host smart-65ea6c18-501e-43e9-8fb8-87f1dd893c90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767635054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2767635054
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.91461679
Short name T29
Test name
Test status
Simulation time 10014033548 ps
CPU time 22.81 seconds
Started Jun 07 08:10:04 PM PDT 24
Finished Jun 07 08:10:31 PM PDT 24
Peak memory 216240 kb
Host smart-8052ac87-79e6-4de5-a78d-4fb4c452d55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91461679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.91461679
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3278186776
Short name T833
Test name
Test status
Simulation time 3183865207 ps
CPU time 6.29 seconds
Started Jun 07 08:10:01 PM PDT 24
Finished Jun 07 08:10:09 PM PDT 24
Peak memory 216088 kb
Host smart-e58d0c18-ebb5-4f10-8f1a-0f91e499c600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278186776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3278186776
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.939886499
Short name T775
Test name
Test status
Simulation time 72941131 ps
CPU time 1.4 seconds
Started Jun 07 08:10:03 PM PDT 24
Finished Jun 07 08:10:08 PM PDT 24
Peak memory 216104 kb
Host smart-157ef5f3-91f8-4397-bacd-45c86f5b26eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939886499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.939886499
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1918441594
Short name T296
Test name
Test status
Simulation time 95827740 ps
CPU time 0.82 seconds
Started Jun 07 08:10:04 PM PDT 24
Finished Jun 07 08:10:09 PM PDT 24
Peak memory 205620 kb
Host smart-7cdc56a4-f6cd-4c91-9ccc-f6a728cc9f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918441594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1918441594
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.163353760
Short name T189
Test name
Test status
Simulation time 4549534567 ps
CPU time 5.79 seconds
Started Jun 07 08:10:04 PM PDT 24
Finished Jun 07 08:10:13 PM PDT 24
Peak memory 232484 kb
Host smart-7263715c-b34f-4620-8605-cccc40d40073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163353760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.163353760
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.308807138
Short name T506
Test name
Test status
Simulation time 48189435 ps
CPU time 0.76 seconds
Started Jun 07 08:09:16 PM PDT 24
Finished Jun 07 08:09:23 PM PDT 24
Peak memory 204336 kb
Host smart-ef151a4e-d7e2-4016-ab3e-3162eb0a06ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308807138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.308807138
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.198233825
Short name T627
Test name
Test status
Simulation time 1654728527 ps
CPU time 4.22 seconds
Started Jun 07 08:09:18 PM PDT 24
Finished Jun 07 08:09:29 PM PDT 24
Peak memory 224280 kb
Host smart-c5d3c838-e884-4909-a2a7-483a81f380da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198233825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.198233825
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1346440045
Short name T864
Test name
Test status
Simulation time 19761340 ps
CPU time 0.76 seconds
Started Jun 07 08:09:15 PM PDT 24
Finished Jun 07 08:09:22 PM PDT 24
Peak memory 206244 kb
Host smart-48d09a8c-2e28-48ab-90ee-5ef7d9bb6052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346440045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1346440045
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3252495263
Short name T249
Test name
Test status
Simulation time 1261998947 ps
CPU time 26.94 seconds
Started Jun 07 08:09:15 PM PDT 24
Finished Jun 07 08:09:48 PM PDT 24
Peak memory 240812 kb
Host smart-0174da31-11b6-4ab8-b473-0bdb2839622b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252495263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3252495263
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.288654793
Short name T224
Test name
Test status
Simulation time 17448792413 ps
CPU time 64.71 seconds
Started Jun 07 08:09:17 PM PDT 24
Finished Jun 07 08:10:29 PM PDT 24
Peak memory 254140 kb
Host smart-6cfb4ca3-f94d-4292-82d2-838540e3474a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288654793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
288654793
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4178289179
Short name T379
Test name
Test status
Simulation time 5648133110 ps
CPU time 14.29 seconds
Started Jun 07 08:09:15 PM PDT 24
Finished Jun 07 08:09:35 PM PDT 24
Peak memory 232616 kb
Host smart-90ea3551-d2d8-4de2-86f0-5904ae6c74c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178289179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4178289179
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2056425253
Short name T851
Test name
Test status
Simulation time 193725906 ps
CPU time 6.58 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:27 PM PDT 24
Peak memory 224280 kb
Host smart-444e120c-f4c9-42ff-b5a2-eb14c9ea4ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056425253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2056425253
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1543139526
Short name T397
Test name
Test status
Simulation time 372540635 ps
CPU time 8.34 seconds
Started Jun 07 08:09:10 PM PDT 24
Finished Jun 07 08:09:20 PM PDT 24
Peak memory 230372 kb
Host smart-b1016c36-1f70-46bd-b151-9be1aef07382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543139526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1543139526
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.101913176
Short name T386
Test name
Test status
Simulation time 14647145 ps
CPU time 0.99 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:09:27 PM PDT 24
Peak memory 217612 kb
Host smart-cccfa4e3-0b8a-4474-9420-e74f48337ba8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101913176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.101913176
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.649063542
Short name T385
Test name
Test status
Simulation time 451073437 ps
CPU time 2.24 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:23 PM PDT 24
Peak memory 232544 kb
Host smart-bb100494-0d32-4550-8b59-fce04e4379c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649063542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
649063542
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2083939319
Short name T268
Test name
Test status
Simulation time 1795129883 ps
CPU time 7.21 seconds
Started Jun 07 08:09:17 PM PDT 24
Finished Jun 07 08:09:31 PM PDT 24
Peak memory 224328 kb
Host smart-9301278b-5f28-4558-beae-0bab38de9f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083939319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2083939319
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1631735481
Short name T602
Test name
Test status
Simulation time 840309405 ps
CPU time 4.11 seconds
Started Jun 07 08:09:18 PM PDT 24
Finished Jun 07 08:09:29 PM PDT 24
Peak memory 218904 kb
Host smart-9ad0c6c4-39e0-4997-8385-7e965c269968
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1631735481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1631735481
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3689931673
Short name T76
Test name
Test status
Simulation time 93127594 ps
CPU time 1.2 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:15 PM PDT 24
Peak memory 236468 kb
Host smart-3a548200-4b65-4683-8f2c-5da7fc3b7b06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689931673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3689931673
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.200004383
Short name T969
Test name
Test status
Simulation time 8584125117 ps
CPU time 7.23 seconds
Started Jun 07 08:09:01 PM PDT 24
Finished Jun 07 08:09:12 PM PDT 24
Peak memory 224488 kb
Host smart-802a65e2-12af-43d2-95f8-cdc11ae6d1d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200004383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.200004383
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.386145248
Short name T699
Test name
Test status
Simulation time 3911482945 ps
CPU time 25.59 seconds
Started Jun 07 08:09:15 PM PDT 24
Finished Jun 07 08:09:47 PM PDT 24
Peak memory 216108 kb
Host smart-fc5da9f7-29e7-4f46-8e4c-8e31e42b6064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386145248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.386145248
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1967289535
Short name T701
Test name
Test status
Simulation time 53641975243 ps
CPU time 12.25 seconds
Started Jun 07 08:09:19 PM PDT 24
Finished Jun 07 08:09:38 PM PDT 24
Peak memory 216160 kb
Host smart-b98f1b49-f8b8-4780-b3ac-0037b690247d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967289535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1967289535
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2536264027
Short name T513
Test name
Test status
Simulation time 158892490 ps
CPU time 6.38 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:26 PM PDT 24
Peak memory 216088 kb
Host smart-632ae58a-9c18-46a7-86f6-42346a82c3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536264027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2536264027
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3921647764
Short name T808
Test name
Test status
Simulation time 317486723 ps
CPU time 0.9 seconds
Started Jun 07 08:09:15 PM PDT 24
Finished Jun 07 08:09:22 PM PDT 24
Peak memory 205620 kb
Host smart-329a29f1-a178-4d5d-9ee8-481761798e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921647764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3921647764
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2592083742
Short name T471
Test name
Test status
Simulation time 117876424 ps
CPU time 2.59 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:23 PM PDT 24
Peak memory 224236 kb
Host smart-43419278-c28d-4d73-bd65-26dc54a383e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592083742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2592083742
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3913520586
Short name T870
Test name
Test status
Simulation time 18177378 ps
CPU time 0.71 seconds
Started Jun 07 08:10:12 PM PDT 24
Finished Jun 07 08:10:17 PM PDT 24
Peak memory 205144 kb
Host smart-33d95828-ecfb-4cdf-aa08-652a32f44776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913520586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3913520586
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.4291661093
Short name T758
Test name
Test status
Simulation time 892091647 ps
CPU time 9.58 seconds
Started Jun 07 08:10:04 PM PDT 24
Finished Jun 07 08:10:18 PM PDT 24
Peak memory 224348 kb
Host smart-a36b098d-3b2b-42a0-a140-8214293eae03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291661093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4291661093
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2790132971
Short name T771
Test name
Test status
Simulation time 83471608 ps
CPU time 0.79 seconds
Started Jun 07 08:10:03 PM PDT 24
Finished Jun 07 08:10:07 PM PDT 24
Peak memory 206576 kb
Host smart-c6b9d8a9-1e93-4aec-a1bf-3dddcb01e601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790132971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2790132971
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3333349974
Short name T876
Test name
Test status
Simulation time 9662347561 ps
CPU time 62.88 seconds
Started Jun 07 08:10:01 PM PDT 24
Finished Jun 07 08:11:06 PM PDT 24
Peak memory 240792 kb
Host smart-3fc85607-fac8-4850-8445-c28ba8d2364d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333349974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3333349974
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1442424407
Short name T629
Test name
Test status
Simulation time 96706566404 ps
CPU time 194.91 seconds
Started Jun 07 08:10:02 PM PDT 24
Finished Jun 07 08:13:21 PM PDT 24
Peak memory 248924 kb
Host smart-ec61ab23-2c71-4996-be87-a14c9381bbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442424407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1442424407
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1337139755
Short name T741
Test name
Test status
Simulation time 2690153575 ps
CPU time 44.1 seconds
Started Jun 07 08:10:02 PM PDT 24
Finished Jun 07 08:10:49 PM PDT 24
Peak memory 240800 kb
Host smart-9e16854f-e2b0-4e0f-98dd-102540c4ceb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337139755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1337139755
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3422050452
Short name T823
Test name
Test status
Simulation time 190770722 ps
CPU time 2.48 seconds
Started Jun 07 08:10:02 PM PDT 24
Finished Jun 07 08:10:08 PM PDT 24
Peak memory 232244 kb
Host smart-f15c6f61-ffd2-4bb0-864d-b4a8ff8ef1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422050452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3422050452
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3625572104
Short name T816
Test name
Test status
Simulation time 2358682798 ps
CPU time 22.85 seconds
Started Jun 07 08:10:03 PM PDT 24
Finished Jun 07 08:10:29 PM PDT 24
Peak memory 232576 kb
Host smart-aa6e9fb4-53e0-4788-8e6c-5da6204bfa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625572104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3625572104
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.831497225
Short name T35
Test name
Test status
Simulation time 32654889391 ps
CPU time 19.41 seconds
Started Jun 07 08:10:05 PM PDT 24
Finished Jun 07 08:10:28 PM PDT 24
Peak memory 224420 kb
Host smart-9212b9bf-b9c8-47ac-b853-5dc61a41c9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831497225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.831497225
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3000547891
Short name T80
Test name
Test status
Simulation time 201022797 ps
CPU time 2.48 seconds
Started Jun 07 08:10:04 PM PDT 24
Finished Jun 07 08:10:10 PM PDT 24
Peak memory 224344 kb
Host smart-a9593dea-c368-4a67-91c1-64299f566d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000547891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3000547891
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2341025750
Short name T894
Test name
Test status
Simulation time 102094597 ps
CPU time 4.5 seconds
Started Jun 07 08:10:05 PM PDT 24
Finished Jun 07 08:10:14 PM PDT 24
Peak memory 222668 kb
Host smart-c2669ece-d3ef-4166-9967-76ec50bbe03c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2341025750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2341025750
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1905084579
Short name T716
Test name
Test status
Simulation time 466603003 ps
CPU time 8.2 seconds
Started Jun 07 08:10:10 PM PDT 24
Finished Jun 07 08:10:22 PM PDT 24
Peak memory 224452 kb
Host smart-681a79ea-35c2-4a21-a1b2-1605476dd525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905084579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1905084579
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3234392169
Short name T976
Test name
Test status
Simulation time 4570622134 ps
CPU time 19.61 seconds
Started Jun 07 08:10:01 PM PDT 24
Finished Jun 07 08:10:22 PM PDT 24
Peak memory 216104 kb
Host smart-20412899-2fd8-45d3-98f1-0f55ca72c89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234392169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3234392169
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2384775724
Short name T641
Test name
Test status
Simulation time 421272991 ps
CPU time 1.66 seconds
Started Jun 07 08:10:05 PM PDT 24
Finished Jun 07 08:10:10 PM PDT 24
Peak memory 215860 kb
Host smart-a51412c7-e0e9-4f6a-bb91-3c7d59482ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384775724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2384775724
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.253511700
Short name T473
Test name
Test status
Simulation time 84181334 ps
CPU time 1.28 seconds
Started Jun 07 08:10:03 PM PDT 24
Finished Jun 07 08:10:07 PM PDT 24
Peak memory 207808 kb
Host smart-8d1d07d9-4028-47c1-889c-f323b5819eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253511700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.253511700
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2458244030
Short name T556
Test name
Test status
Simulation time 213473629 ps
CPU time 0.96 seconds
Started Jun 07 08:10:04 PM PDT 24
Finished Jun 07 08:10:09 PM PDT 24
Peak memory 205820 kb
Host smart-0555b746-e35f-4c08-949d-98f08a8d475c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458244030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2458244030
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1023930493
Short name T49
Test name
Test status
Simulation time 10594922709 ps
CPU time 16.01 seconds
Started Jun 07 08:10:01 PM PDT 24
Finished Jun 07 08:10:20 PM PDT 24
Peak memory 240760 kb
Host smart-02c5769c-9308-4a34-8ce8-41ff014ae03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023930493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1023930493
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1061766958
Short name T661
Test name
Test status
Simulation time 49193132 ps
CPU time 0.73 seconds
Started Jun 07 08:10:09 PM PDT 24
Finished Jun 07 08:10:13 PM PDT 24
Peak memory 204524 kb
Host smart-c25a724c-7795-4fe6-929a-5dd2495f8e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061766958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1061766958
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3251976348
Short name T1
Test name
Test status
Simulation time 276931487 ps
CPU time 3.33 seconds
Started Jun 07 08:10:10 PM PDT 24
Finished Jun 07 08:10:17 PM PDT 24
Peak memory 232508 kb
Host smart-a1431de1-7b1b-4fb1-949f-d56886975152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251976348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3251976348
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2980590666
Short name T18
Test name
Test status
Simulation time 51916880 ps
CPU time 0.82 seconds
Started Jun 07 08:10:11 PM PDT 24
Finished Jun 07 08:10:15 PM PDT 24
Peak memory 206544 kb
Host smart-925cbd0d-02e7-4207-ba99-d5d10c1853b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980590666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2980590666
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3757063036
Short name T625
Test name
Test status
Simulation time 4640390983 ps
CPU time 72.27 seconds
Started Jun 07 08:10:11 PM PDT 24
Finished Jun 07 08:11:27 PM PDT 24
Peak memory 265384 kb
Host smart-260418f2-8b0a-4c75-84fa-36e7799a2996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757063036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3757063036
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1102894162
Short name T131
Test name
Test status
Simulation time 21880557377 ps
CPU time 178.98 seconds
Started Jun 07 08:10:13 PM PDT 24
Finished Jun 07 08:13:15 PM PDT 24
Peak memory 266416 kb
Host smart-ef0b3a5c-0104-43cb-a050-abbe933d4538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102894162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1102894162
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2230899640
Short name T227
Test name
Test status
Simulation time 19108631567 ps
CPU time 136.09 seconds
Started Jun 07 08:10:09 PM PDT 24
Finished Jun 07 08:12:29 PM PDT 24
Peak memory 268068 kb
Host smart-80a14279-e044-488a-9c87-8e4416b7af8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230899640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2230899640
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2131208165
Short name T285
Test name
Test status
Simulation time 544627785 ps
CPU time 7.34 seconds
Started Jun 07 08:10:11 PM PDT 24
Finished Jun 07 08:10:22 PM PDT 24
Peak memory 234276 kb
Host smart-7d79a026-8553-431d-982b-379bd6b47874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131208165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2131208165
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2868890148
Short name T376
Test name
Test status
Simulation time 385375087 ps
CPU time 6.06 seconds
Started Jun 07 08:10:10 PM PDT 24
Finished Jun 07 08:10:20 PM PDT 24
Peak memory 224088 kb
Host smart-93bc824c-86dc-4dee-928b-893de7935862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868890148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2868890148
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2094496111
Short name T403
Test name
Test status
Simulation time 5171045385 ps
CPU time 20.82 seconds
Started Jun 07 08:10:07 PM PDT 24
Finished Jun 07 08:10:31 PM PDT 24
Peak memory 240620 kb
Host smart-cabdbc82-40d5-4fb0-adc9-00cc52cc1c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094496111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2094496111
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.254310988
Short name T205
Test name
Test status
Simulation time 8196513535 ps
CPU time 10.39 seconds
Started Jun 07 08:10:08 PM PDT 24
Finished Jun 07 08:10:22 PM PDT 24
Peak memory 232592 kb
Host smart-d70e9667-0556-4efd-b579-84a9e52ab97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254310988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.254310988
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1682206366
Short name T828
Test name
Test status
Simulation time 35577290 ps
CPU time 2.5 seconds
Started Jun 07 08:10:08 PM PDT 24
Finished Jun 07 08:10:14 PM PDT 24
Peak memory 232328 kb
Host smart-0768f830-f760-496a-9bdd-cc8c41e3c6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682206366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1682206366
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3038172165
Short name T631
Test name
Test status
Simulation time 7041604319 ps
CPU time 21.47 seconds
Started Jun 07 08:10:10 PM PDT 24
Finished Jun 07 08:10:35 PM PDT 24
Peak memory 218996 kb
Host smart-a7722d09-bbdd-41db-a5c0-3a3150769cff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3038172165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3038172165
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.584036725
Short name T228
Test name
Test status
Simulation time 10468319940 ps
CPU time 142.58 seconds
Started Jun 07 08:10:10 PM PDT 24
Finished Jun 07 08:12:35 PM PDT 24
Peak memory 257228 kb
Host smart-b915544d-54c6-40a0-99c7-3ebc4b934343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584036725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.584036725
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1636081288
Short name T778
Test name
Test status
Simulation time 1977380621 ps
CPU time 15.3 seconds
Started Jun 07 08:10:09 PM PDT 24
Finished Jun 07 08:10:27 PM PDT 24
Peak memory 216092 kb
Host smart-b5517e78-28b8-4031-b8dc-11a25e006798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636081288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1636081288
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.947806247
Short name T962
Test name
Test status
Simulation time 865773480 ps
CPU time 4.72 seconds
Started Jun 07 08:10:08 PM PDT 24
Finished Jun 07 08:10:16 PM PDT 24
Peak memory 216076 kb
Host smart-379add33-a3c5-4969-84c1-9c24eb7c65f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947806247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.947806247
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1770376118
Short name T965
Test name
Test status
Simulation time 582228523 ps
CPU time 2.06 seconds
Started Jun 07 08:10:08 PM PDT 24
Finished Jun 07 08:10:14 PM PDT 24
Peak memory 216100 kb
Host smart-21699260-31a7-44ca-b757-7387dbf390ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770376118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1770376118
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2028535945
Short name T700
Test name
Test status
Simulation time 176097756 ps
CPU time 0.97 seconds
Started Jun 07 08:10:12 PM PDT 24
Finished Jun 07 08:10:16 PM PDT 24
Peak memory 205584 kb
Host smart-8893342e-b8f3-49ab-9ece-2f2cb91df69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028535945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2028535945
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3850259771
Short name T342
Test name
Test status
Simulation time 587948828 ps
CPU time 2.43 seconds
Started Jun 07 08:10:12 PM PDT 24
Finished Jun 07 08:10:18 PM PDT 24
Peak memory 224032 kb
Host smart-bff59043-1773-4e6a-b8fd-8a3c7a3c5714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850259771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3850259771
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1458943556
Short name T939
Test name
Test status
Simulation time 40208534 ps
CPU time 0.7 seconds
Started Jun 07 08:10:12 PM PDT 24
Finished Jun 07 08:10:17 PM PDT 24
Peak memory 205128 kb
Host smart-aca0c4cb-6335-496c-a4b9-3be1d45ae4ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458943556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1458943556
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1525256322
Short name T615
Test name
Test status
Simulation time 512986679 ps
CPU time 3.18 seconds
Started Jun 07 08:10:12 PM PDT 24
Finished Jun 07 08:10:19 PM PDT 24
Peak memory 224332 kb
Host smart-bfa667a0-fea0-4127-952b-e65045e175eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525256322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1525256322
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.4044842457
Short name T467
Test name
Test status
Simulation time 15092504 ps
CPU time 0.75 seconds
Started Jun 07 08:10:10 PM PDT 24
Finished Jun 07 08:10:13 PM PDT 24
Peak memory 205176 kb
Host smart-2d70de26-3930-4150-8844-9bcec0cbd4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044842457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4044842457
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.256280065
Short name T806
Test name
Test status
Simulation time 43090416306 ps
CPU time 133.6 seconds
Started Jun 07 08:10:09 PM PDT 24
Finished Jun 07 08:12:26 PM PDT 24
Peak memory 249020 kb
Host smart-c6f59a5b-615a-448a-90d6-3d71c8180524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256280065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.256280065
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.960785713
Short name T968
Test name
Test status
Simulation time 16936385151 ps
CPU time 37.43 seconds
Started Jun 07 08:10:08 PM PDT 24
Finished Jun 07 08:10:49 PM PDT 24
Peak memory 217560 kb
Host smart-6df74d47-5cc9-486c-b27a-eb6f771136de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960785713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.960785713
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1089782303
Short name T287
Test name
Test status
Simulation time 16441211159 ps
CPU time 42.16 seconds
Started Jun 07 08:10:10 PM PDT 24
Finished Jun 07 08:10:55 PM PDT 24
Peak memory 217544 kb
Host smart-d33f8f27-c857-4cec-8cf2-7a83e9203332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089782303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1089782303
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3119332356
Short name T671
Test name
Test status
Simulation time 2534584883 ps
CPU time 7.15 seconds
Started Jun 07 08:10:11 PM PDT 24
Finished Jun 07 08:10:22 PM PDT 24
Peak memory 219392 kb
Host smart-f3eb2782-ce01-4a25-aca7-9737d6d02ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119332356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3119332356
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1742732589
Short name T45
Test name
Test status
Simulation time 10405918621 ps
CPU time 88.67 seconds
Started Jun 07 08:10:12 PM PDT 24
Finished Jun 07 08:11:44 PM PDT 24
Peak memory 240676 kb
Host smart-86ec29af-d4e7-4845-ba72-b11909f6bf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742732589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1742732589
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2841636526
Short name T755
Test name
Test status
Simulation time 249800249 ps
CPU time 3.09 seconds
Started Jun 07 08:10:09 PM PDT 24
Finished Jun 07 08:10:15 PM PDT 24
Peak memory 232540 kb
Host smart-156c090c-47d2-462a-89bd-9bcefcfcf44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841636526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2841636526
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1612776624
Short name T497
Test name
Test status
Simulation time 64105233 ps
CPU time 2.52 seconds
Started Jun 07 08:10:10 PM PDT 24
Finished Jun 07 08:10:15 PM PDT 24
Peak memory 232560 kb
Host smart-becdf34f-a04e-49c6-a6b1-90665ee65aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612776624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1612776624
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3155139988
Short name T335
Test name
Test status
Simulation time 1624446674 ps
CPU time 20.18 seconds
Started Jun 07 08:10:11 PM PDT 24
Finished Jun 07 08:10:35 PM PDT 24
Peak memory 221564 kb
Host smart-b6d41949-7ca2-4b51-94b8-539e7a3c5de7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3155139988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3155139988
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2247498017
Short name T143
Test name
Test status
Simulation time 81007194 ps
CPU time 1.27 seconds
Started Jun 07 08:10:11 PM PDT 24
Finished Jun 07 08:10:15 PM PDT 24
Peak memory 206908 kb
Host smart-b5fdbfbe-6562-4eea-8cb8-3ec88e57a13d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247498017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2247498017
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1218560685
Short name T431
Test name
Test status
Simulation time 835068628 ps
CPU time 1.7 seconds
Started Jun 07 08:10:10 PM PDT 24
Finished Jun 07 08:10:14 PM PDT 24
Peak memory 216060 kb
Host smart-c7904e6e-c12b-4d6f-87ea-a60102e90a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218560685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1218560685
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1698170025
Short name T826
Test name
Test status
Simulation time 732193785 ps
CPU time 2.01 seconds
Started Jun 07 08:10:09 PM PDT 24
Finished Jun 07 08:10:14 PM PDT 24
Peak memory 207660 kb
Host smart-3bc7ac6f-9c47-4cb4-bbbc-b22735f46aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698170025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1698170025
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.298305199
Short name T680
Test name
Test status
Simulation time 153174445 ps
CPU time 1.26 seconds
Started Jun 07 08:10:11 PM PDT 24
Finished Jun 07 08:10:16 PM PDT 24
Peak memory 215924 kb
Host smart-1a7b6abe-022a-4b2f-a246-93ef380d5058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298305199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.298305199
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1867174041
Short name T933
Test name
Test status
Simulation time 315678691 ps
CPU time 0.87 seconds
Started Jun 07 08:10:10 PM PDT 24
Finished Jun 07 08:10:15 PM PDT 24
Peak memory 205612 kb
Host smart-6dd8bb2b-5fe2-483b-8fdf-31ccd6e7c616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867174041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1867174041
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2502407758
Short name T651
Test name
Test status
Simulation time 17359462915 ps
CPU time 12.52 seconds
Started Jun 07 08:10:09 PM PDT 24
Finished Jun 07 08:10:24 PM PDT 24
Peak memory 232588 kb
Host smart-e37b5117-09fe-4c96-8200-78662ae4450d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502407758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2502407758
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.368193745
Short name T541
Test name
Test status
Simulation time 12015737 ps
CPU time 0.67 seconds
Started Jun 07 08:10:11 PM PDT 24
Finished Jun 07 08:10:16 PM PDT 24
Peak memory 205524 kb
Host smart-cccd165a-658d-4bbf-974f-d8d6e1a5e134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368193745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.368193745
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.4004066530
Short name T679
Test name
Test status
Simulation time 885682093 ps
CPU time 5.51 seconds
Started Jun 07 08:10:12 PM PDT 24
Finished Jun 07 08:10:22 PM PDT 24
Peak memory 224388 kb
Host smart-d1b9ffc8-1346-43b2-879b-ab137cd63025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004066530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.4004066530
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1372742197
Short name T442
Test name
Test status
Simulation time 55160112 ps
CPU time 0.79 seconds
Started Jun 07 08:10:10 PM PDT 24
Finished Jun 07 08:10:15 PM PDT 24
Peak memory 205196 kb
Host smart-b5f9414a-8c46-4dc7-b136-84afd8875567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372742197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1372742197
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2797166264
Short name T644
Test name
Test status
Simulation time 4522514561 ps
CPU time 31.55 seconds
Started Jun 07 08:10:13 PM PDT 24
Finished Jun 07 08:10:48 PM PDT 24
Peak memory 235900 kb
Host smart-90b38aaf-427b-4319-9c49-363e2cfa5c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797166264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2797166264
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.324861772
Short name T601
Test name
Test status
Simulation time 117386674122 ps
CPU time 280.48 seconds
Started Jun 07 08:10:13 PM PDT 24
Finished Jun 07 08:14:57 PM PDT 24
Peak memory 249048 kb
Host smart-a4d3c90b-9b4c-4361-aa78-334f024774f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324861772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.324861772
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1418315303
Short name T201
Test name
Test status
Simulation time 80178747601 ps
CPU time 149.36 seconds
Started Jun 07 08:10:12 PM PDT 24
Finished Jun 07 08:12:46 PM PDT 24
Peak memory 249068 kb
Host smart-d14e0da1-18a0-4576-a836-ea68b8d7ae55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418315303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1418315303
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4166917420
Short name T374
Test name
Test status
Simulation time 1143715118 ps
CPU time 6.59 seconds
Started Jun 07 08:10:12 PM PDT 24
Finished Jun 07 08:10:23 PM PDT 24
Peak memory 224272 kb
Host smart-2f723fd0-e997-481e-b5a7-4fb39f4ca39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166917420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4166917420
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3017556357
Short name T349
Test name
Test status
Simulation time 242482693 ps
CPU time 5.38 seconds
Started Jun 07 08:10:12 PM PDT 24
Finished Jun 07 08:10:21 PM PDT 24
Peak memory 232512 kb
Host smart-d4a58e6e-3e98-4437-9717-2ef707f58935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017556357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3017556357
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2897437366
Short name T586
Test name
Test status
Simulation time 2345330083 ps
CPU time 5.37 seconds
Started Jun 07 08:10:11 PM PDT 24
Finished Jun 07 08:10:20 PM PDT 24
Peak memory 240408 kb
Host smart-07ae4e07-53b8-4e3f-9bed-1bee4fe684ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897437366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2897437366
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1973180034
Short name T767
Test name
Test status
Simulation time 11332691688 ps
CPU time 18.32 seconds
Started Jun 07 08:10:12 PM PDT 24
Finished Jun 07 08:10:35 PM PDT 24
Peak memory 240276 kb
Host smart-8a411307-464f-486e-871b-85140792e0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973180034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1973180034
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2649912337
Short name T428
Test name
Test status
Simulation time 369414761 ps
CPU time 4.07 seconds
Started Jun 07 08:10:12 PM PDT 24
Finished Jun 07 08:10:20 PM PDT 24
Peak memory 222816 kb
Host smart-7ccbba43-67a3-45d0-a033-a615d5875b17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2649912337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2649912337
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1533109929
Short name T861
Test name
Test status
Simulation time 6045290068 ps
CPU time 124.14 seconds
Started Jun 07 08:10:12 PM PDT 24
Finished Jun 07 08:12:20 PM PDT 24
Peak memory 260184 kb
Host smart-43e7baf1-4579-4340-ba30-d9f3e364e2ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533109929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1533109929
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2196537051
Short name T327
Test name
Test status
Simulation time 478565334 ps
CPU time 6.69 seconds
Started Jun 07 08:10:11 PM PDT 24
Finished Jun 07 08:10:21 PM PDT 24
Peak memory 216040 kb
Host smart-25f43b84-8dad-48e9-ab2e-b3dff27e7498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196537051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2196537051
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3188333694
Short name T710
Test name
Test status
Simulation time 4858819718 ps
CPU time 6.8 seconds
Started Jun 07 08:10:13 PM PDT 24
Finished Jun 07 08:10:24 PM PDT 24
Peak memory 216160 kb
Host smart-26c97704-cf51-4050-bf3c-3a5fe180dfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188333694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3188333694
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1572968593
Short name T880
Test name
Test status
Simulation time 61668327 ps
CPU time 2.04 seconds
Started Jun 07 08:10:11 PM PDT 24
Finished Jun 07 08:10:17 PM PDT 24
Peak memory 216040 kb
Host smart-27948a67-0af9-4269-a291-7386138490b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572968593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1572968593
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.842883736
Short name T432
Test name
Test status
Simulation time 38631923 ps
CPU time 0.73 seconds
Started Jun 07 08:10:09 PM PDT 24
Finished Jun 07 08:10:13 PM PDT 24
Peak memory 205624 kb
Host smart-5003cbc7-8c37-4700-b944-5723a69d3cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842883736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.842883736
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.816628366
Short name T242
Test name
Test status
Simulation time 99089953 ps
CPU time 3.78 seconds
Started Jun 07 08:10:11 PM PDT 24
Finished Jun 07 08:10:18 PM PDT 24
Peak memory 232620 kb
Host smart-ff746ea7-6afe-4a91-9563-3d51cbc3d82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816628366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.816628366
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4093529797
Short name T609
Test name
Test status
Simulation time 11821327 ps
CPU time 0.73 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:10:25 PM PDT 24
Peak memory 204560 kb
Host smart-f28c1137-175b-4074-b84f-d46d526688b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093529797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4093529797
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.619446780
Short name T451
Test name
Test status
Simulation time 224249553 ps
CPU time 2.84 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:10:27 PM PDT 24
Peak memory 232476 kb
Host smart-df40db03-12f3-4254-a90f-c36f390b905a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619446780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.619446780
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1580143540
Short name T707
Test name
Test status
Simulation time 38608464 ps
CPU time 0.8 seconds
Started Jun 07 08:10:09 PM PDT 24
Finished Jun 07 08:10:13 PM PDT 24
Peak memory 206576 kb
Host smart-a409419b-f811-4ac7-b387-e67e7c7ad246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580143540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1580143540
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2449226578
Short name T66
Test name
Test status
Simulation time 25643469018 ps
CPU time 189.23 seconds
Started Jun 07 08:10:19 PM PDT 24
Finished Jun 07 08:13:30 PM PDT 24
Peak memory 254596 kb
Host smart-d4b58cb2-2595-416a-abcb-51a27f0a4f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449226578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2449226578
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3440149367
Short name T478
Test name
Test status
Simulation time 40063203657 ps
CPU time 375.29 seconds
Started Jun 07 08:10:21 PM PDT 24
Finished Jun 07 08:16:41 PM PDT 24
Peak memory 252720 kb
Host smart-66ccbb29-c955-4145-824a-0d6a24fceb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440149367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3440149367
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3584686415
Short name T276
Test name
Test status
Simulation time 1483870523 ps
CPU time 10.17 seconds
Started Jun 07 08:10:21 PM PDT 24
Finished Jun 07 08:10:36 PM PDT 24
Peak memory 233952 kb
Host smart-a770a000-a59e-49aa-8994-9f83f57803eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584686415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3584686415
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.794850528
Short name T375
Test name
Test status
Simulation time 157640060 ps
CPU time 2.15 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:10:27 PM PDT 24
Peak memory 224264 kb
Host smart-713c4294-0f49-4314-b538-3c4379d419c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794850528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.794850528
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.623182102
Short name T165
Test name
Test status
Simulation time 16724651314 ps
CPU time 70.79 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:11:35 PM PDT 24
Peak memory 240420 kb
Host smart-db4dbdd0-3d1c-4212-b76e-d29c87496a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623182102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.623182102
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.171456428
Short name T194
Test name
Test status
Simulation time 175192371 ps
CPU time 5 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:10:28 PM PDT 24
Peak memory 232540 kb
Host smart-3466e63c-ffe6-4569-b8e5-aeb4b9193e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171456428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.171456428
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.797092385
Short name T382
Test name
Test status
Simulation time 5667339678 ps
CPU time 8.53 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:10:32 PM PDT 24
Peak memory 224352 kb
Host smart-4c57c2e6-dcb5-4d9c-9c21-7b1d53b30b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797092385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.797092385
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1414415714
Short name T789
Test name
Test status
Simulation time 3104752446 ps
CPU time 16.11 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:10:40 PM PDT 24
Peak memory 221620 kb
Host smart-cff6dd50-ad11-47c0-b1f9-e02eff7b20ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1414415714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1414415714
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3239438706
Short name T146
Test name
Test status
Simulation time 10963388112 ps
CPU time 94.43 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:11:58 PM PDT 24
Peak memory 255876 kb
Host smart-ebf68f78-eda8-4c4b-851f-abd723414f0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239438706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3239438706
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.215326899
Short name T30
Test name
Test status
Simulation time 14482275794 ps
CPU time 21.46 seconds
Started Jun 07 08:10:18 PM PDT 24
Finished Jun 07 08:10:42 PM PDT 24
Peak memory 216200 kb
Host smart-71d55f67-344e-46c1-a622-3efaab0296ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215326899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.215326899
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.356982624
Short name T923
Test name
Test status
Simulation time 3243157361 ps
CPU time 7.81 seconds
Started Jun 07 08:10:18 PM PDT 24
Finished Jun 07 08:10:28 PM PDT 24
Peak memory 216112 kb
Host smart-76e558f9-cbb3-4b1e-9ba3-8ffb19dc5f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356982624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.356982624
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.288579833
Short name T728
Test name
Test status
Simulation time 219500177 ps
CPU time 1.34 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:10:24 PM PDT 24
Peak memory 216128 kb
Host smart-355e02fd-019b-4aa0-9e8b-d94e9c74b4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288579833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.288579833
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.784203575
Short name T317
Test name
Test status
Simulation time 107939511 ps
CPU time 0.81 seconds
Started Jun 07 08:10:18 PM PDT 24
Finished Jun 07 08:10:21 PM PDT 24
Peak memory 205524 kb
Host smart-7de1cb82-2389-4644-9175-b17c8f7b4e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784203575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.784203575
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2925943436
Short name T852
Test name
Test status
Simulation time 4165708253 ps
CPU time 16.03 seconds
Started Jun 07 08:10:19 PM PDT 24
Finished Jun 07 08:10:38 PM PDT 24
Peak memory 240796 kb
Host smart-41e83865-e72f-4fce-bd3e-6bacb88d827b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925943436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2925943436
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.75821531
Short name T858
Test name
Test status
Simulation time 36500799 ps
CPU time 0.73 seconds
Started Jun 07 08:10:19 PM PDT 24
Finished Jun 07 08:10:23 PM PDT 24
Peak memory 205184 kb
Host smart-3439c898-e766-4409-9cac-4d2a7e7bb2f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75821531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.75821531
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1135287229
Short name T684
Test name
Test status
Simulation time 6143094357 ps
CPU time 16.94 seconds
Started Jun 07 08:10:19 PM PDT 24
Finished Jun 07 08:10:38 PM PDT 24
Peak memory 224380 kb
Host smart-ba5a8e42-4d24-4a16-a846-8bfdd458ace2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135287229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1135287229
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.28434270
Short name T337
Test name
Test status
Simulation time 74380785 ps
CPU time 0.8 seconds
Started Jun 07 08:10:22 PM PDT 24
Finished Jun 07 08:10:28 PM PDT 24
Peak memory 206228 kb
Host smart-794e3580-d853-4b60-a61a-35840cbb9e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28434270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.28434270
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.243412646
Short name T417
Test name
Test status
Simulation time 5109196252 ps
CPU time 41.97 seconds
Started Jun 07 08:10:19 PM PDT 24
Finished Jun 07 08:11:03 PM PDT 24
Peak memory 236976 kb
Host smart-0571d682-a997-4993-9a2f-eac6ba2e404a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243412646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.243412646
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2141872431
Short name T152
Test name
Test status
Simulation time 808024021994 ps
CPU time 640.49 seconds
Started Jun 07 08:10:21 PM PDT 24
Finished Jun 07 08:21:06 PM PDT 24
Peak memory 263064 kb
Host smart-17cc7d47-19be-4a1d-b3fe-6895476b9abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141872431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2141872431
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2465238692
Short name T970
Test name
Test status
Simulation time 107459332944 ps
CPU time 90.5 seconds
Started Jun 07 08:10:17 PM PDT 24
Finished Jun 07 08:11:50 PM PDT 24
Peak memory 236852 kb
Host smart-a1c3e731-3557-462b-a084-3346f1e04c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465238692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2465238692
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3026364208
Short name T932
Test name
Test status
Simulation time 581048677 ps
CPU time 5.57 seconds
Started Jun 07 08:10:17 PM PDT 24
Finished Jun 07 08:10:25 PM PDT 24
Peak memory 237660 kb
Host smart-2123b943-7be7-4a2d-bd3f-a0eb89a243cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026364208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3026364208
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3826369167
Short name T678
Test name
Test status
Simulation time 162154080 ps
CPU time 4.12 seconds
Started Jun 07 08:10:22 PM PDT 24
Finished Jun 07 08:10:31 PM PDT 24
Peak memory 224292 kb
Host smart-90989d5a-3377-47ee-920a-e1302d36bf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826369167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3826369167
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1464531141
Short name T547
Test name
Test status
Simulation time 1833245967 ps
CPU time 8.01 seconds
Started Jun 07 08:10:21 PM PDT 24
Finished Jun 07 08:10:33 PM PDT 24
Peak memory 224312 kb
Host smart-2c5ffd03-7cd1-4f2e-bd51-50e41dd4ff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464531141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1464531141
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.294861631
Short name T503
Test name
Test status
Simulation time 9238787184 ps
CPU time 8.85 seconds
Started Jun 07 08:10:28 PM PDT 24
Finished Jun 07 08:10:41 PM PDT 24
Peak memory 232580 kb
Host smart-cdcf4705-c4f4-4e56-bbb3-2b06b6613cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294861631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.294861631
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.679736533
Short name T158
Test name
Test status
Simulation time 7249224299 ps
CPU time 11.34 seconds
Started Jun 07 08:10:19 PM PDT 24
Finished Jun 07 08:10:34 PM PDT 24
Peak memory 239448 kb
Host smart-6a950b7a-943c-4d48-91bf-70e853416803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679736533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.679736533
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3557037066
Short name T320
Test name
Test status
Simulation time 251668723 ps
CPU time 5.26 seconds
Started Jun 07 08:10:18 PM PDT 24
Finished Jun 07 08:10:26 PM PDT 24
Peak memory 221468 kb
Host smart-15acba7b-593a-4d35-a184-04bde2122cee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3557037066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3557037066
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3518586078
Short name T877
Test name
Test status
Simulation time 18605941597 ps
CPU time 112.45 seconds
Started Jun 07 08:10:23 PM PDT 24
Finished Jun 07 08:12:20 PM PDT 24
Peak memory 268356 kb
Host smart-46a9047a-d93f-4ad2-afa7-133a6d5e5c32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518586078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3518586078
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1678775491
Short name T560
Test name
Test status
Simulation time 14557459587 ps
CPU time 33.49 seconds
Started Jun 07 08:10:22 PM PDT 24
Finished Jun 07 08:11:00 PM PDT 24
Peak memory 216116 kb
Host smart-dea66935-9856-44e5-bbc3-11381bd9a31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678775491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1678775491
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2019328956
Short name T353
Test name
Test status
Simulation time 2740698842 ps
CPU time 3.18 seconds
Started Jun 07 08:10:18 PM PDT 24
Finished Jun 07 08:10:24 PM PDT 24
Peak memory 216084 kb
Host smart-ad70ad94-ea5e-47c8-b144-ce874a0488b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019328956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2019328956
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3020632209
Short name T908
Test name
Test status
Simulation time 26348836 ps
CPU time 0.7 seconds
Started Jun 07 08:10:23 PM PDT 24
Finished Jun 07 08:10:28 PM PDT 24
Peak memory 205156 kb
Host smart-382669c7-360c-454d-9f42-92e6ccf8da51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020632209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3020632209
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1163694157
Short name T453
Test name
Test status
Simulation time 56114688 ps
CPU time 0.82 seconds
Started Jun 07 08:10:22 PM PDT 24
Finished Jun 07 08:10:27 PM PDT 24
Peak memory 205524 kb
Host smart-3b092c87-e4da-4b20-8298-b998939a31cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163694157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1163694157
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1124130486
Short name T163
Test name
Test status
Simulation time 3245345190 ps
CPU time 8.32 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:10:31 PM PDT 24
Peak memory 224460 kb
Host smart-8b10be35-f67e-4aa0-8839-74c8e376a10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124130486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1124130486
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1868629813
Short name T68
Test name
Test status
Simulation time 43399789 ps
CPU time 0.75 seconds
Started Jun 07 08:10:28 PM PDT 24
Finished Jun 07 08:10:33 PM PDT 24
Peak memory 205168 kb
Host smart-a4541c8c-e02a-4959-934c-34d578eb7d8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868629813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1868629813
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3544921162
Short name T90
Test name
Test status
Simulation time 54003879 ps
CPU time 2.64 seconds
Started Jun 07 08:10:21 PM PDT 24
Finished Jun 07 08:10:28 PM PDT 24
Peak memory 232540 kb
Host smart-45712e82-3f2d-4410-a104-154bce751381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544921162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3544921162
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3259121848
Short name T909
Test name
Test status
Simulation time 78590076 ps
CPU time 0.81 seconds
Started Jun 07 08:10:18 PM PDT 24
Finished Jun 07 08:10:21 PM PDT 24
Peak memory 206244 kb
Host smart-5348bdd2-5424-42b8-8ff7-04466aa0c373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259121848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3259121848
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3133903278
Short name T534
Test name
Test status
Simulation time 115317870701 ps
CPU time 218.4 seconds
Started Jun 07 08:10:22 PM PDT 24
Finished Jun 07 08:14:06 PM PDT 24
Peak memory 248952 kb
Host smart-afdc4df9-b159-402c-b2f6-64d378f028ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133903278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3133903278
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2875033320
Short name T543
Test name
Test status
Simulation time 28163805721 ps
CPU time 122 seconds
Started Jun 07 08:10:21 PM PDT 24
Finished Jun 07 08:12:28 PM PDT 24
Peak memory 249424 kb
Host smart-9a127ca0-72f2-458c-939e-b037a2159c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875033320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2875033320
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3239887710
Short name T65
Test name
Test status
Simulation time 7917829889 ps
CPU time 135.6 seconds
Started Jun 07 08:10:22 PM PDT 24
Finished Jun 07 08:12:42 PM PDT 24
Peak memory 250832 kb
Host smart-10842cce-bf39-4b54-befa-031d926dbc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239887710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3239887710
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.144492258
Short name T43
Test name
Test status
Simulation time 924251814 ps
CPU time 12.66 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:10:36 PM PDT 24
Peak memory 224308 kb
Host smart-e34f18c2-d0f5-4899-8e99-3a32ff0b7c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144492258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.144492258
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1827888123
Short name T721
Test name
Test status
Simulation time 51778351 ps
CPU time 2.76 seconds
Started Jun 07 08:10:23 PM PDT 24
Finished Jun 07 08:10:31 PM PDT 24
Peak memory 224300 kb
Host smart-53a92d48-15d7-4b96-874e-89369e591f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827888123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1827888123
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1162809053
Short name T837
Test name
Test status
Simulation time 8852410574 ps
CPU time 27.55 seconds
Started Jun 07 08:10:23 PM PDT 24
Finished Jun 07 08:10:55 PM PDT 24
Peak memory 232528 kb
Host smart-8e1196df-909a-4e67-879b-fdd2ff5733c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162809053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1162809053
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1381413297
Short name T187
Test name
Test status
Simulation time 2400255281 ps
CPU time 4.38 seconds
Started Jun 07 08:10:27 PM PDT 24
Finished Jun 07 08:10:36 PM PDT 24
Peak memory 232604 kb
Host smart-102bf211-e9d1-4fe1-8a35-8de6664fa7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381413297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1381413297
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.335249751
Short name T305
Test name
Test status
Simulation time 54656677122 ps
CPU time 13.02 seconds
Started Jun 07 08:10:21 PM PDT 24
Finished Jun 07 08:10:39 PM PDT 24
Peak memory 232492 kb
Host smart-c08a77d5-84ef-4026-985a-a5dd89ad9e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335249751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.335249751
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3888846971
Short name T581
Test name
Test status
Simulation time 9180523023 ps
CPU time 8.91 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:10:34 PM PDT 24
Peak memory 218884 kb
Host smart-721b341f-45c1-4980-99ae-f630cd6577fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3888846971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3888846971
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2396204227
Short name T433
Test name
Test status
Simulation time 18475427541 ps
CPU time 32.68 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:10:55 PM PDT 24
Peak memory 216180 kb
Host smart-3b3a21ba-edb3-4882-ae67-4a91a8ad0e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396204227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2396204227
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1757099249
Short name T555
Test name
Test status
Simulation time 4828984985 ps
CPU time 15.24 seconds
Started Jun 07 08:10:23 PM PDT 24
Finished Jun 07 08:10:42 PM PDT 24
Peak memory 216104 kb
Host smart-d9a5a306-7e74-4021-ae14-d7ada7bd78cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757099249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1757099249
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2558241011
Short name T740
Test name
Test status
Simulation time 261764448 ps
CPU time 1.71 seconds
Started Jun 07 08:10:19 PM PDT 24
Finished Jun 07 08:10:24 PM PDT 24
Peak memory 215960 kb
Host smart-cac25ee6-2f3f-40ee-9467-2a967b495570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558241011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2558241011
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2957106108
Short name T558
Test name
Test status
Simulation time 74440420 ps
CPU time 0.91 seconds
Started Jun 07 08:10:21 PM PDT 24
Finished Jun 07 08:10:26 PM PDT 24
Peak memory 205584 kb
Host smart-b6f52f41-2b2b-404e-9f44-b261be563e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957106108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2957106108
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1099858886
Short name T409
Test name
Test status
Simulation time 13693988101 ps
CPU time 14.1 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:10:37 PM PDT 24
Peak memory 239632 kb
Host smart-258813f4-99ca-4e5d-ab92-2818639927b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099858886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1099858886
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3429582719
Short name T711
Test name
Test status
Simulation time 16330021 ps
CPU time 0.7 seconds
Started Jun 07 08:10:29 PM PDT 24
Finished Jun 07 08:10:35 PM PDT 24
Peak memory 205524 kb
Host smart-deca0ba9-8bb7-4976-8700-67566bba5d2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429582719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3429582719
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.557195369
Short name T831
Test name
Test status
Simulation time 534202867 ps
CPU time 3.84 seconds
Started Jun 07 08:10:23 PM PDT 24
Finished Jun 07 08:10:31 PM PDT 24
Peak memory 232492 kb
Host smart-97c10799-10d2-4cbc-a9b0-8c2352cc6b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557195369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.557195369
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.158396601
Short name T306
Test name
Test status
Simulation time 36526795 ps
CPU time 0.84 seconds
Started Jun 07 08:10:27 PM PDT 24
Finished Jun 07 08:10:33 PM PDT 24
Peak memory 206224 kb
Host smart-b90861cf-d112-4627-8ac7-7728ff0396ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158396601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.158396601
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2547038609
Short name T130
Test name
Test status
Simulation time 22455528597 ps
CPU time 223.17 seconds
Started Jun 07 08:10:27 PM PDT 24
Finished Jun 07 08:14:15 PM PDT 24
Peak memory 260020 kb
Host smart-4bff18d9-9aa4-49e0-a5a0-5859a86d341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547038609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2547038609
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2644225355
Short name T260
Test name
Test status
Simulation time 7231650040 ps
CPU time 45.78 seconds
Started Jun 07 08:10:29 PM PDT 24
Finished Jun 07 08:11:20 PM PDT 24
Peak memory 252668 kb
Host smart-f4908237-74d6-4327-9649-b1504d89f9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644225355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2644225355
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3737644705
Short name T773
Test name
Test status
Simulation time 27189556342 ps
CPU time 110.56 seconds
Started Jun 07 08:10:29 PM PDT 24
Finished Jun 07 08:12:24 PM PDT 24
Peak memory 249056 kb
Host smart-515a3b60-185c-481a-a4cb-733c0f2fc879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737644705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3737644705
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1348449853
Short name T649
Test name
Test status
Simulation time 1760964327 ps
CPU time 29.13 seconds
Started Jun 07 08:10:21 PM PDT 24
Finished Jun 07 08:10:55 PM PDT 24
Peak memory 232556 kb
Host smart-144fb9f2-4a0a-44e8-829f-062917d5fade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348449853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1348449853
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2389029715
Short name T255
Test name
Test status
Simulation time 8497394885 ps
CPU time 20.19 seconds
Started Jun 07 08:10:22 PM PDT 24
Finished Jun 07 08:10:47 PM PDT 24
Peak memory 224340 kb
Host smart-58fefcb3-2c8e-43ab-8fc2-0a6d391c5452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389029715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2389029715
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.4083935911
Short name T854
Test name
Test status
Simulation time 9010420127 ps
CPU time 78.1 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:11:42 PM PDT 24
Peak memory 248952 kb
Host smart-c8418a67-6caf-4425-a100-93b73c4003f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083935911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4083935911
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2594279683
Short name T412
Test name
Test status
Simulation time 2062485449 ps
CPU time 9.7 seconds
Started Jun 07 08:10:23 PM PDT 24
Finished Jun 07 08:10:37 PM PDT 24
Peak memory 240040 kb
Host smart-f0be9086-8c6d-4813-a20c-b5f894016adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594279683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2594279683
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2066432184
Short name T537
Test name
Test status
Simulation time 22282709308 ps
CPU time 29.41 seconds
Started Jun 07 08:10:22 PM PDT 24
Finished Jun 07 08:10:56 PM PDT 24
Peak memory 240784 kb
Host smart-296bc0a9-253b-4f08-b2c4-df4d7cfac2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066432184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2066432184
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3897470813
Short name T929
Test name
Test status
Simulation time 230310995 ps
CPU time 4.16 seconds
Started Jun 07 08:10:23 PM PDT 24
Finished Jun 07 08:10:32 PM PDT 24
Peak memory 222704 kb
Host smart-db220422-23cd-4ebe-80ca-b46fcc2664fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3897470813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3897470813
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1166261839
Short name T64
Test name
Test status
Simulation time 6403725675 ps
CPU time 135.41 seconds
Started Jun 07 08:10:31 PM PDT 24
Finished Jun 07 08:12:51 PM PDT 24
Peak memory 255032 kb
Host smart-a96c6b76-06d3-495a-9bc8-6d1c32aaa57c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166261839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1166261839
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.173198927
Short name T664
Test name
Test status
Simulation time 4669995984 ps
CPU time 14.22 seconds
Started Jun 07 08:10:20 PM PDT 24
Finished Jun 07 08:10:39 PM PDT 24
Peak memory 216156 kb
Host smart-f5f5a456-54e7-4ebc-845d-0290458b28b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173198927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.173198927
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3568318783
Short name T708
Test name
Test status
Simulation time 25993142487 ps
CPU time 4.03 seconds
Started Jun 07 08:10:23 PM PDT 24
Finished Jun 07 08:10:31 PM PDT 24
Peak memory 216000 kb
Host smart-cc51004a-605e-464c-98aa-1140027418b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568318783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3568318783
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1511129784
Short name T356
Test name
Test status
Simulation time 72268325 ps
CPU time 1.01 seconds
Started Jun 07 08:10:22 PM PDT 24
Finished Jun 07 08:10:28 PM PDT 24
Peak memory 206792 kb
Host smart-629b3fff-033c-4dd4-be99-4e0a62598a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511129784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1511129784
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1233021608
Short name T746
Test name
Test status
Simulation time 482007055 ps
CPU time 0.87 seconds
Started Jun 07 08:10:22 PM PDT 24
Finished Jun 07 08:10:28 PM PDT 24
Peak memory 205580 kb
Host smart-de5ce9a8-48bc-423e-ba90-9cb959b4a752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233021608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1233021608
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3326838461
Short name T487
Test name
Test status
Simulation time 27308041978 ps
CPU time 19.39 seconds
Started Jun 07 08:10:23 PM PDT 24
Finished Jun 07 08:10:47 PM PDT 24
Peak memory 224408 kb
Host smart-7589f190-7a94-4c2c-a6c9-b5d253652b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326838461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3326838461
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1891236380
Short name T79
Test name
Test status
Simulation time 17333045 ps
CPU time 0.75 seconds
Started Jun 07 08:10:30 PM PDT 24
Finished Jun 07 08:10:35 PM PDT 24
Peak memory 204556 kb
Host smart-28719e27-0d89-462e-a634-b239d549aaae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891236380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1891236380
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2901889154
Short name T867
Test name
Test status
Simulation time 32658643 ps
CPU time 2.29 seconds
Started Jun 07 08:10:31 PM PDT 24
Finished Jun 07 08:10:38 PM PDT 24
Peak memory 224236 kb
Host smart-276eb152-9615-4acb-b79e-7375bc4ba3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901889154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2901889154
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1860278307
Short name T869
Test name
Test status
Simulation time 18229986 ps
CPU time 0.77 seconds
Started Jun 07 08:10:29 PM PDT 24
Finished Jun 07 08:10:35 PM PDT 24
Peak memory 205544 kb
Host smart-8aa5c3d5-779a-421d-ba0f-5241bb75525b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860278307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1860278307
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3725606229
Short name T192
Test name
Test status
Simulation time 1431797680 ps
CPU time 35.19 seconds
Started Jun 07 08:10:29 PM PDT 24
Finished Jun 07 08:11:09 PM PDT 24
Peak memory 248960 kb
Host smart-a82482fa-4cfb-4fc3-9b0c-9b9873c0d1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725606229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3725606229
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1111784041
Short name T720
Test name
Test status
Simulation time 8170343633 ps
CPU time 31.76 seconds
Started Jun 07 08:10:29 PM PDT 24
Finished Jun 07 08:11:05 PM PDT 24
Peak memory 232684 kb
Host smart-2d2f68b1-1e69-46db-84a6-6fde95a129eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111784041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1111784041
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2979374273
Short name T946
Test name
Test status
Simulation time 2480166987 ps
CPU time 64.85 seconds
Started Jun 07 08:10:29 PM PDT 24
Finished Jun 07 08:11:39 PM PDT 24
Peak memory 249036 kb
Host smart-3fab0351-9ed1-4d88-b73d-5d19b2c2f453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979374273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2979374273
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3573130075
Short name T279
Test name
Test status
Simulation time 8992448161 ps
CPU time 44 seconds
Started Jun 07 08:10:27 PM PDT 24
Finished Jun 07 08:11:16 PM PDT 24
Peak memory 235528 kb
Host smart-ee1bdc1b-d20d-4c33-af6d-b47737e37d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573130075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3573130075
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2166516044
Short name T270
Test name
Test status
Simulation time 220016158 ps
CPU time 4.95 seconds
Started Jun 07 08:10:32 PM PDT 24
Finished Jun 07 08:10:41 PM PDT 24
Peak memory 232492 kb
Host smart-ceaef8ea-46be-4329-9cbf-b932680ca9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166516044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2166516044
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2980395182
Short name T184
Test name
Test status
Simulation time 211505838 ps
CPU time 2.39 seconds
Started Jun 07 08:10:30 PM PDT 24
Finished Jun 07 08:10:37 PM PDT 24
Peak memory 224356 kb
Host smart-02364bee-e51b-4f67-8dbc-0325f7fc436e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980395182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2980395182
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.553517784
Short name T875
Test name
Test status
Simulation time 9962994174 ps
CPU time 19.21 seconds
Started Jun 07 08:10:27 PM PDT 24
Finished Jun 07 08:10:51 PM PDT 24
Peak memory 224336 kb
Host smart-8b6cabe2-8fe1-4a5c-8b92-016e52195557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553517784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.553517784
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3675114226
Short name T504
Test name
Test status
Simulation time 7045399218 ps
CPU time 5.88 seconds
Started Jun 07 08:10:31 PM PDT 24
Finished Jun 07 08:10:41 PM PDT 24
Peak memory 240420 kb
Host smart-ad701d83-bec1-4516-aa49-ca1866c98690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675114226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3675114226
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.713398598
Short name T501
Test name
Test status
Simulation time 148225698 ps
CPU time 4.17 seconds
Started Jun 07 08:10:31 PM PDT 24
Finished Jun 07 08:10:39 PM PDT 24
Peak memory 222252 kb
Host smart-3e5b1a3b-7f0c-43f3-bc0e-9bf5e354c1d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=713398598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.713398598
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3034485101
Short name T754
Test name
Test status
Simulation time 42393844873 ps
CPU time 202.69 seconds
Started Jun 07 08:10:33 PM PDT 24
Finished Jun 07 08:13:59 PM PDT 24
Peak memory 256288 kb
Host smart-423a4023-92ba-4030-9344-e82444e9ab51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034485101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3034485101
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3550274647
Short name T585
Test name
Test status
Simulation time 7173620287 ps
CPU time 19.78 seconds
Started Jun 07 08:10:30 PM PDT 24
Finished Jun 07 08:10:54 PM PDT 24
Peak memory 216132 kb
Host smart-92377d69-6281-465b-aab3-93825ab67690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550274647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3550274647
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2825854092
Short name T297
Test name
Test status
Simulation time 15977362568 ps
CPU time 5.63 seconds
Started Jun 07 08:10:31 PM PDT 24
Finished Jun 07 08:10:41 PM PDT 24
Peak memory 216120 kb
Host smart-2331397a-e7e4-4305-9068-1bfa0bf2c1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825854092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2825854092
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3303096004
Short name T318
Test name
Test status
Simulation time 442876480 ps
CPU time 2.86 seconds
Started Jun 07 08:10:30 PM PDT 24
Finished Jun 07 08:10:37 PM PDT 24
Peak memory 216108 kb
Host smart-f82e829b-5465-4754-9bd5-6f34cf514934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303096004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3303096004
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1891041924
Short name T574
Test name
Test status
Simulation time 270854832 ps
CPU time 1.1 seconds
Started Jun 07 08:10:29 PM PDT 24
Finished Jun 07 08:10:34 PM PDT 24
Peak memory 206604 kb
Host smart-c9e7a994-eb2e-4f5e-af32-46000546880c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891041924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1891041924
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.580303845
Short name T942
Test name
Test status
Simulation time 350623592 ps
CPU time 3.9 seconds
Started Jun 07 08:10:28 PM PDT 24
Finished Jun 07 08:10:37 PM PDT 24
Peak memory 224320 kb
Host smart-cd42694b-70e0-4302-8a1d-8bdd1dfd2bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580303845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.580303845
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.124094565
Short name T360
Test name
Test status
Simulation time 11617750 ps
CPU time 0.7 seconds
Started Jun 07 08:10:31 PM PDT 24
Finished Jun 07 08:10:36 PM PDT 24
Peak memory 205180 kb
Host smart-771a6f0f-9ddb-4207-8c8c-e2e6a7194de2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124094565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.124094565
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.4226282773
Short name T901
Test name
Test status
Simulation time 1871308086 ps
CPU time 18.3 seconds
Started Jun 07 08:10:29 PM PDT 24
Finished Jun 07 08:10:52 PM PDT 24
Peak memory 232580 kb
Host smart-9adf4ca4-d2bc-4d9b-8c77-2d45ef0c555e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226282773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.4226282773
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2607619483
Short name T406
Test name
Test status
Simulation time 36870542 ps
CPU time 0.8 seconds
Started Jun 07 08:10:29 PM PDT 24
Finished Jun 07 08:10:34 PM PDT 24
Peak memory 205516 kb
Host smart-3d74a247-c6f6-4509-80e9-092ec5dccd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607619483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2607619483
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.4102819856
Short name T420
Test name
Test status
Simulation time 12523888089 ps
CPU time 65.06 seconds
Started Jun 07 08:10:32 PM PDT 24
Finished Jun 07 08:11:41 PM PDT 24
Peak memory 250660 kb
Host smart-7c57ef40-4886-47eb-9c1e-94fc4893dba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102819856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.4102819856
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.598485559
Short name T935
Test name
Test status
Simulation time 8276278415 ps
CPU time 99.68 seconds
Started Jun 07 08:10:32 PM PDT 24
Finished Jun 07 08:12:16 PM PDT 24
Peak memory 255100 kb
Host smart-a7049dbb-b24b-4f0a-903d-323683a0f580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598485559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.598485559
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3847610477
Short name T129
Test name
Test status
Simulation time 56462429165 ps
CPU time 520.54 seconds
Started Jun 07 08:10:31 PM PDT 24
Finished Jun 07 08:19:16 PM PDT 24
Peak memory 256344 kb
Host smart-de12b5e0-218f-48e0-a83c-fabc127fb533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847610477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3847610477
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2646051380
Short name T668
Test name
Test status
Simulation time 1637960870 ps
CPU time 7.51 seconds
Started Jun 07 08:10:30 PM PDT 24
Finished Jun 07 08:10:42 PM PDT 24
Peak memory 224320 kb
Host smart-0f3091d5-ed1b-4f13-ba3d-81020feabb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646051380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2646051380
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1573349383
Short name T859
Test name
Test status
Simulation time 5540988973 ps
CPU time 16.24 seconds
Started Jun 07 08:10:31 PM PDT 24
Finished Jun 07 08:10:51 PM PDT 24
Peak memory 224360 kb
Host smart-82db0d02-d9fe-4e6c-ac93-cc08138fd22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573349383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1573349383
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2600121797
Short name T256
Test name
Test status
Simulation time 8788878499 ps
CPU time 107.03 seconds
Started Jun 07 08:10:31 PM PDT 24
Finished Jun 07 08:12:22 PM PDT 24
Peak memory 232660 kb
Host smart-85c061b8-3338-4e7d-939c-d925e4d9d1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600121797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2600121797
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3909372071
Short name T33
Test name
Test status
Simulation time 4975196765 ps
CPU time 10.12 seconds
Started Jun 07 08:10:40 PM PDT 24
Finished Jun 07 08:10:54 PM PDT 24
Peak memory 224380 kb
Host smart-a86960ae-6cd8-4de6-a850-5fb9625cd5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909372071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3909372071
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1124749343
Short name T315
Test name
Test status
Simulation time 112482681 ps
CPU time 2.49 seconds
Started Jun 07 08:10:32 PM PDT 24
Finished Jun 07 08:10:39 PM PDT 24
Peak memory 232304 kb
Host smart-27e2a944-e934-4fa1-a8f7-d95f884b97b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124749343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1124749343
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3425770977
Short name T813
Test name
Test status
Simulation time 715478449 ps
CPU time 9.6 seconds
Started Jun 07 08:10:29 PM PDT 24
Finished Jun 07 08:10:44 PM PDT 24
Peak memory 219012 kb
Host smart-e9e5cc08-ea76-46d5-9019-72ccb866ee46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3425770977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3425770977
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2027080848
Short name T32
Test name
Test status
Simulation time 154915198787 ps
CPU time 604.01 seconds
Started Jun 07 08:10:29 PM PDT 24
Finished Jun 07 08:20:38 PM PDT 24
Peak memory 264760 kb
Host smart-0fd95c41-1784-4815-8508-f7a89456c477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027080848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2027080848
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3062522257
Short name T885
Test name
Test status
Simulation time 30343572852 ps
CPU time 46.09 seconds
Started Jun 07 08:10:27 PM PDT 24
Finished Jun 07 08:11:18 PM PDT 24
Peak memory 216124 kb
Host smart-1e89cbd8-dc7d-498a-846a-e15a51ecc76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062522257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3062522257
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4079113625
Short name T912
Test name
Test status
Simulation time 10527058005 ps
CPU time 15.2 seconds
Started Jun 07 08:10:30 PM PDT 24
Finished Jun 07 08:10:50 PM PDT 24
Peak memory 216080 kb
Host smart-5dc4f9e3-996c-459a-98fb-011051470617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079113625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4079113625
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2030124544
Short name T148
Test name
Test status
Simulation time 1539870864 ps
CPU time 1.7 seconds
Started Jun 07 08:10:29 PM PDT 24
Finished Jun 07 08:10:36 PM PDT 24
Peak memory 216052 kb
Host smart-1e566502-dfbb-4c76-bb7f-ac61aa1ef663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030124544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2030124544
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1890632490
Short name T874
Test name
Test status
Simulation time 47598162 ps
CPU time 0.83 seconds
Started Jun 07 08:10:32 PM PDT 24
Finished Jun 07 08:10:37 PM PDT 24
Peak memory 205616 kb
Host smart-51f7261e-7afa-46fe-a548-016959a7b492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890632490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1890632490
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1166428223
Short name T415
Test name
Test status
Simulation time 991874298 ps
CPU time 4.2 seconds
Started Jun 07 08:10:40 PM PDT 24
Finished Jun 07 08:10:48 PM PDT 24
Peak memory 232504 kb
Host smart-3bc28d62-2f2b-43df-adfb-c9427a8e7ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166428223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1166428223
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3079734931
Short name T333
Test name
Test status
Simulation time 23784140 ps
CPU time 0.74 seconds
Started Jun 07 08:09:12 PM PDT 24
Finished Jun 07 08:09:17 PM PDT 24
Peak memory 205180 kb
Host smart-ee70e7f5-a5f0-4885-8421-d6b4b7afa2f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079734931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
079734931
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1443722483
Short name T769
Test name
Test status
Simulation time 328628940 ps
CPU time 4.69 seconds
Started Jun 07 08:09:15 PM PDT 24
Finished Jun 07 08:09:27 PM PDT 24
Peak memory 224284 kb
Host smart-d72fda96-cc8f-4b3f-991d-9bb4cf9adf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443722483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1443722483
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.17368405
Short name T613
Test name
Test status
Simulation time 88053815 ps
CPU time 0.77 seconds
Started Jun 07 08:09:16 PM PDT 24
Finished Jun 07 08:09:23 PM PDT 24
Peak memory 206232 kb
Host smart-e6197490-cb62-45d3-8c9b-73607932c159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17368405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.17368405
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1653814585
Short name T241
Test name
Test status
Simulation time 3586472497 ps
CPU time 57.28 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:10:10 PM PDT 24
Peak memory 248956 kb
Host smart-95cf4957-6eaa-42f5-948d-329fd200421e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653814585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1653814585
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3269393935
Short name T161
Test name
Test status
Simulation time 10270594258 ps
CPU time 7.74 seconds
Started Jun 07 08:09:12 PM PDT 24
Finished Jun 07 08:09:24 PM PDT 24
Peak memory 233652 kb
Host smart-936c7a3b-6b7b-47ec-9899-87597cfa4d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269393935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3269393935
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3537009364
Short name T925
Test name
Test status
Simulation time 8578158523 ps
CPU time 56.09 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:10:16 PM PDT 24
Peak memory 238584 kb
Host smart-ee6ab558-31d8-4cdb-96ba-53ddd471cf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537009364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3537009364
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.624063780
Short name T807
Test name
Test status
Simulation time 2293702585 ps
CPU time 34.32 seconds
Started Jun 07 08:09:04 PM PDT 24
Finished Jun 07 08:09:41 PM PDT 24
Peak memory 233644 kb
Host smart-9e4650c2-44e9-47ef-af9c-97c5d42b2c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624063780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.624063780
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.481275835
Short name T170
Test name
Test status
Simulation time 508991487 ps
CPU time 3.48 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:23 PM PDT 24
Peak memory 224340 kb
Host smart-0995edfb-c150-4257-9533-caa0875cb43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481275835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.481275835
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2644117088
Short name T949
Test name
Test status
Simulation time 13028943433 ps
CPU time 44.03 seconds
Started Jun 07 08:09:12 PM PDT 24
Finished Jun 07 08:10:01 PM PDT 24
Peak memory 232564 kb
Host smart-b09ff8bc-9e65-4f19-81d0-d54848abc1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644117088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2644117088
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3295562715
Short name T910
Test name
Test status
Simulation time 17985691 ps
CPU time 1.05 seconds
Started Jun 07 08:09:18 PM PDT 24
Finished Jun 07 08:09:27 PM PDT 24
Peak memory 216344 kb
Host smart-926e3df7-b575-4d8a-8c34-129d161debce
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295562715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3295562715
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3452909610
Short name T4
Test name
Test status
Simulation time 6455857728 ps
CPU time 21.41 seconds
Started Jun 07 08:09:17 PM PDT 24
Finished Jun 07 08:09:46 PM PDT 24
Peak memory 232420 kb
Host smart-658d4fe8-6339-41be-b341-e94224b1ca1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452909610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3452909610
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1606258358
Short name T832
Test name
Test status
Simulation time 8004873560 ps
CPU time 10.6 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:31 PM PDT 24
Peak memory 232584 kb
Host smart-88d11e62-ddaa-41bd-a00d-d2d47d680cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606258358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1606258358
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.597672032
Short name T135
Test name
Test status
Simulation time 719277395 ps
CPU time 4.95 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:18 PM PDT 24
Peak memory 219064 kb
Host smart-16518b3d-18d3-4789-80ea-6c091724ce35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=597672032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.597672032
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1599998941
Short name T73
Test name
Test status
Simulation time 91352360 ps
CPU time 1.2 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:15 PM PDT 24
Peak memory 235004 kb
Host smart-233b4706-85c4-40ec-ae39-ae1b4bc4789e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599998941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1599998941
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1257054116
Short name T214
Test name
Test status
Simulation time 22090722148 ps
CPU time 276.64 seconds
Started Jun 07 08:09:16 PM PDT 24
Finished Jun 07 08:13:59 PM PDT 24
Peak memory 256948 kb
Host smart-9f61bf19-0873-4072-8f16-8fff541c0464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257054116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1257054116
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.4085506356
Short name T515
Test name
Test status
Simulation time 13410335508 ps
CPU time 27.22 seconds
Started Jun 07 08:09:16 PM PDT 24
Finished Jun 07 08:09:49 PM PDT 24
Peak memory 215980 kb
Host smart-60524b34-470f-4a84-8bfb-7420a0861650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085506356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.4085506356
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1004300441
Short name T784
Test name
Test status
Simulation time 19405547187 ps
CPU time 13.74 seconds
Started Jun 07 08:09:16 PM PDT 24
Finished Jun 07 08:09:36 PM PDT 24
Peak memory 216188 kb
Host smart-a5063c7d-58ac-42af-be23-50a3dbfc284e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004300441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1004300441
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1608468523
Short name T424
Test name
Test status
Simulation time 165100869 ps
CPU time 2.1 seconds
Started Jun 07 08:09:17 PM PDT 24
Finished Jun 07 08:09:26 PM PDT 24
Peak memory 216056 kb
Host smart-34668c2f-74bf-4f69-842f-d81cc5f989ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608468523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1608468523
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1549939756
Short name T311
Test name
Test status
Simulation time 88005911 ps
CPU time 0.84 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:19 PM PDT 24
Peak memory 205612 kb
Host smart-bf60099c-dc93-4355-8181-64073da9b1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549939756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1549939756
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.209089829
Short name T508
Test name
Test status
Simulation time 4352069739 ps
CPU time 9.84 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:30 PM PDT 24
Peak memory 224424 kb
Host smart-894f9fff-19a8-4b29-9599-60a7d176fe96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209089829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.209089829
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.290321535
Short name T742
Test name
Test status
Simulation time 48306539 ps
CPU time 0.76 seconds
Started Jun 07 08:10:34 PM PDT 24
Finished Jun 07 08:10:39 PM PDT 24
Peak memory 205140 kb
Host smart-85d7a3f4-8fe8-4c59-a29e-a4e5a8a64749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290321535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.290321535
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2381395635
Short name T464
Test name
Test status
Simulation time 283876788 ps
CPU time 2.97 seconds
Started Jun 07 08:10:30 PM PDT 24
Finished Jun 07 08:10:37 PM PDT 24
Peak memory 224360 kb
Host smart-572cb7e8-89f4-48fa-963e-bf481fb87f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381395635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2381395635
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1800951019
Short name T301
Test name
Test status
Simulation time 70601087 ps
CPU time 0.77 seconds
Started Jun 07 08:10:40 PM PDT 24
Finished Jun 07 08:10:44 PM PDT 24
Peak memory 206216 kb
Host smart-6300261b-bd6c-4b22-9c01-0015d0c86f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800951019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1800951019
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1955513342
Short name T173
Test name
Test status
Simulation time 21195882953 ps
CPU time 21.28 seconds
Started Jun 07 08:10:36 PM PDT 24
Finished Jun 07 08:11:01 PM PDT 24
Peak memory 236080 kb
Host smart-df22268b-ac3b-41a8-a4cb-750cb32e19e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955513342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1955513342
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2733913835
Short name T254
Test name
Test status
Simulation time 18663849672 ps
CPU time 155.16 seconds
Started Jun 07 08:10:36 PM PDT 24
Finished Jun 07 08:13:15 PM PDT 24
Peak memory 249008 kb
Host smart-2b36db3c-1efd-4a43-a303-033c9ab00a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733913835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2733913835
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2644516722
Short name T973
Test name
Test status
Simulation time 5747776141 ps
CPU time 25.79 seconds
Started Jun 07 08:10:34 PM PDT 24
Finished Jun 07 08:11:04 PM PDT 24
Peak memory 232608 kb
Host smart-3460e055-808d-49fd-a60c-565e16fa57ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644516722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2644516722
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1254071639
Short name T654
Test name
Test status
Simulation time 952591619 ps
CPU time 4.9 seconds
Started Jun 07 08:10:31 PM PDT 24
Finished Jun 07 08:10:41 PM PDT 24
Peak memory 224244 kb
Host smart-6776fd2f-2430-475c-98f3-5fd3bcf509f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254071639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1254071639
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3087813771
Short name T868
Test name
Test status
Simulation time 34504638446 ps
CPU time 68.89 seconds
Started Jun 07 08:10:40 PM PDT 24
Finished Jun 07 08:11:53 PM PDT 24
Peak memory 224348 kb
Host smart-b39b436e-8a13-4466-b6d9-97176eeb868b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087813771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3087813771
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2359302588
Short name T892
Test name
Test status
Simulation time 7736303844 ps
CPU time 12.29 seconds
Started Jun 07 08:10:36 PM PDT 24
Finished Jun 07 08:10:52 PM PDT 24
Peak memory 232620 kb
Host smart-25546c90-3c72-472f-a943-9387acb07753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359302588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2359302588
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3883905874
Short name T974
Test name
Test status
Simulation time 12476188759 ps
CPU time 20.7 seconds
Started Jun 07 08:10:29 PM PDT 24
Finished Jun 07 08:10:54 PM PDT 24
Peak memory 224384 kb
Host smart-4e128914-e8c5-4094-86b4-56e1c1ddd482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883905874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3883905874
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2481375372
Short name T674
Test name
Test status
Simulation time 5334104271 ps
CPU time 9.95 seconds
Started Jun 07 08:10:30 PM PDT 24
Finished Jun 07 08:10:44 PM PDT 24
Peak memory 220884 kb
Host smart-ae0faa33-24f3-471b-bfda-adebd1b5a8da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2481375372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2481375372
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.4045976635
Short name T145
Test name
Test status
Simulation time 665293237956 ps
CPU time 382.96 seconds
Started Jun 07 08:10:38 PM PDT 24
Finished Jun 07 08:17:05 PM PDT 24
Peak memory 264028 kb
Host smart-e84d7396-c00c-416d-87a7-9e653ea23f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045976635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.4045976635
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4128391262
Short name T766
Test name
Test status
Simulation time 60718396 ps
CPU time 0.73 seconds
Started Jun 07 08:10:31 PM PDT 24
Finished Jun 07 08:10:36 PM PDT 24
Peak memory 205340 kb
Host smart-aa7eeb5c-80df-4c2d-9285-9cbf04fc940d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128391262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4128391262
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.283261673
Short name T640
Test name
Test status
Simulation time 36034387 ps
CPU time 0.74 seconds
Started Jun 07 08:10:29 PM PDT 24
Finished Jun 07 08:10:34 PM PDT 24
Peak memory 205240 kb
Host smart-828c3de5-83cb-4499-bb64-e03aa0cf3698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283261673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.283261673
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1691408102
Short name T437
Test name
Test status
Simulation time 122752962 ps
CPU time 3.53 seconds
Started Jun 07 08:10:37 PM PDT 24
Finished Jun 07 08:10:45 PM PDT 24
Peak memory 216108 kb
Host smart-7b29347f-c343-4c1c-b80f-9637c7ce08c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691408102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1691408102
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.707498924
Short name T549
Test name
Test status
Simulation time 27758692 ps
CPU time 0.78 seconds
Started Jun 07 08:10:40 PM PDT 24
Finished Jun 07 08:10:44 PM PDT 24
Peak memory 205584 kb
Host smart-b8ad8e77-764e-44be-b094-631de5ef2059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707498924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.707498924
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.577306829
Short name T975
Test name
Test status
Simulation time 119074253 ps
CPU time 2.18 seconds
Started Jun 07 08:10:34 PM PDT 24
Finished Jun 07 08:10:40 PM PDT 24
Peak memory 223032 kb
Host smart-44480b7e-85c3-4776-824f-be764f2fa0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577306829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.577306829
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2738679744
Short name T616
Test name
Test status
Simulation time 11784503 ps
CPU time 0.69 seconds
Started Jun 07 08:10:37 PM PDT 24
Finished Jun 07 08:10:41 PM PDT 24
Peak memory 205500 kb
Host smart-fcb8aed5-9238-4566-87ba-3000ede83c83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738679744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2738679744
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3227871445
Short name T924
Test name
Test status
Simulation time 1262045332 ps
CPU time 4.3 seconds
Started Jun 07 08:10:35 PM PDT 24
Finished Jun 07 08:10:43 PM PDT 24
Peak memory 224320 kb
Host smart-5dd256d0-bd15-4813-bd4a-288cd8451070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227871445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3227871445
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2593970511
Short name T783
Test name
Test status
Simulation time 23239837 ps
CPU time 0.81 seconds
Started Jun 07 08:10:39 PM PDT 24
Finished Jun 07 08:10:43 PM PDT 24
Peak memory 206252 kb
Host smart-8c725108-329d-49ae-a3d3-92800c15d123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593970511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2593970511
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.671624671
Short name T411
Test name
Test status
Simulation time 13234710525 ps
CPU time 35.66 seconds
Started Jun 07 08:10:38 PM PDT 24
Finished Jun 07 08:11:18 PM PDT 24
Peak memory 235376 kb
Host smart-d4181ce8-fcbd-4cd0-9ae6-62753555b9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671624671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.671624671
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3771995706
Short name T686
Test name
Test status
Simulation time 7782180422 ps
CPU time 49.31 seconds
Started Jun 07 08:10:39 PM PDT 24
Finished Jun 07 08:11:32 PM PDT 24
Peak memory 241288 kb
Host smart-645a0d48-4d20-4e31-9971-186ab517bcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771995706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3771995706
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1950172492
Short name T283
Test name
Test status
Simulation time 132636736 ps
CPU time 7.24 seconds
Started Jun 07 08:10:34 PM PDT 24
Finished Jun 07 08:10:46 PM PDT 24
Peak memory 233508 kb
Host smart-4d97287f-b39f-4124-b31f-9813a37ab183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950172492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1950172492
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2164769685
Short name T732
Test name
Test status
Simulation time 6168744393 ps
CPU time 16.45 seconds
Started Jun 07 08:10:39 PM PDT 24
Finished Jun 07 08:11:00 PM PDT 24
Peak memory 232584 kb
Host smart-95defae6-c4bf-4094-806e-b761ef012e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164769685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2164769685
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2000502367
Short name T624
Test name
Test status
Simulation time 1757395381 ps
CPU time 20.03 seconds
Started Jun 07 08:10:36 PM PDT 24
Finished Jun 07 08:11:00 PM PDT 24
Peak memory 232512 kb
Host smart-41fb2853-38e3-4d2f-91f8-066bda426409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000502367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2000502367
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1633028134
Short name T860
Test name
Test status
Simulation time 1445703970 ps
CPU time 6.31 seconds
Started Jun 07 08:10:38 PM PDT 24
Finished Jun 07 08:10:49 PM PDT 24
Peak memory 232440 kb
Host smart-d55353b6-1b14-482a-bfd1-2f972a546ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633028134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1633028134
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.633262602
Short name T257
Test name
Test status
Simulation time 2046673932 ps
CPU time 5.68 seconds
Started Jun 07 08:10:37 PM PDT 24
Finished Jun 07 08:10:47 PM PDT 24
Peak memory 224328 kb
Host smart-c1949838-592a-40a5-b252-d794e03c516e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633262602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.633262602
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4202778213
Short name T477
Test name
Test status
Simulation time 7577385295 ps
CPU time 11.37 seconds
Started Jun 07 08:10:35 PM PDT 24
Finished Jun 07 08:10:50 PM PDT 24
Peak memory 223024 kb
Host smart-385cfd4a-3641-408d-ab98-f43da9a1965e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4202778213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4202778213
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1224264372
Short name T632
Test name
Test status
Simulation time 53921167 ps
CPU time 1.09 seconds
Started Jun 07 08:10:35 PM PDT 24
Finished Jun 07 08:10:40 PM PDT 24
Peak memory 206500 kb
Host smart-1b955b14-9a48-4b88-9ae3-16913136dacc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224264372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1224264372
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2007789590
Short name T488
Test name
Test status
Simulation time 1147459412 ps
CPU time 17.94 seconds
Started Jun 07 08:10:38 PM PDT 24
Finished Jun 07 08:10:59 PM PDT 24
Peak memory 216104 kb
Host smart-1754e407-fc51-45bc-828b-236ab1918c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007789590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2007789590
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.99275490
Short name T17
Test name
Test status
Simulation time 1117071783 ps
CPU time 2.38 seconds
Started Jun 07 08:10:35 PM PDT 24
Finished Jun 07 08:10:41 PM PDT 24
Peak memory 216096 kb
Host smart-6dc1c4e7-b8be-4d6e-96f0-c7ba0bb6a6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99275490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.99275490
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.97814266
Short name T447
Test name
Test status
Simulation time 325845698 ps
CPU time 5.46 seconds
Started Jun 07 08:10:39 PM PDT 24
Finished Jun 07 08:10:49 PM PDT 24
Peak memory 216144 kb
Host smart-6d30098d-6af3-459f-9118-54d19dc8ded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97814266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.97814266
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2767300421
Short name T295
Test name
Test status
Simulation time 675802595 ps
CPU time 0.92 seconds
Started Jun 07 08:10:38 PM PDT 24
Finished Jun 07 08:10:43 PM PDT 24
Peak memory 205824 kb
Host smart-8422a548-5f0b-4912-b09e-c59ab33b4b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767300421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2767300421
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1218649195
Short name T944
Test name
Test status
Simulation time 1355717482 ps
CPU time 7.32 seconds
Started Jun 07 08:10:35 PM PDT 24
Finished Jun 07 08:10:46 PM PDT 24
Peak memory 238728 kb
Host smart-2ddbc987-013a-4840-a378-f4918cda4c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218649195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1218649195
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3861384943
Short name T659
Test name
Test status
Simulation time 57083841 ps
CPU time 0.7 seconds
Started Jun 07 08:10:42 PM PDT 24
Finished Jun 07 08:10:46 PM PDT 24
Peak memory 205172 kb
Host smart-1f099289-9c1a-4ee9-bd29-35a5fd9fe9df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861384943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3861384943
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3775301429
Short name T915
Test name
Test status
Simulation time 323665253 ps
CPU time 2.43 seconds
Started Jun 07 08:10:41 PM PDT 24
Finished Jun 07 08:10:47 PM PDT 24
Peak memory 224336 kb
Host smart-1aa70cf7-f969-4834-8bff-e32a774947fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775301429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3775301429
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1519216573
Short name T878
Test name
Test status
Simulation time 18864255 ps
CPU time 0.8 seconds
Started Jun 07 08:10:38 PM PDT 24
Finished Jun 07 08:10:43 PM PDT 24
Peak memory 206204 kb
Host smart-f390fb09-6a82-4173-855f-6512e95f6feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519216573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1519216573
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.298154089
Short name T217
Test name
Test status
Simulation time 2156724447 ps
CPU time 43.28 seconds
Started Jun 07 08:10:39 PM PDT 24
Finished Jun 07 08:11:27 PM PDT 24
Peak memory 250024 kb
Host smart-ba973e1a-7aa5-4464-b693-b9c5b57ceda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298154089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.298154089
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1014487132
Short name T921
Test name
Test status
Simulation time 6081690701 ps
CPU time 85.65 seconds
Started Jun 07 08:10:42 PM PDT 24
Finished Jun 07 08:12:11 PM PDT 24
Peak memory 255024 kb
Host smart-f6121c56-b9c4-4a1d-8757-6b29c1cf814b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014487132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1014487132
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2212196117
Short name T259
Test name
Test status
Simulation time 78232774089 ps
CPU time 404.68 seconds
Started Jun 07 08:10:41 PM PDT 24
Finished Jun 07 08:17:29 PM PDT 24
Peak memory 238360 kb
Host smart-f48bf33b-1f30-493e-94d5-e473f26b8653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212196117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2212196117
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1814145580
Short name T681
Test name
Test status
Simulation time 2516066188 ps
CPU time 14.69 seconds
Started Jun 07 08:10:38 PM PDT 24
Finished Jun 07 08:10:57 PM PDT 24
Peak memory 240764 kb
Host smart-a311f7ff-e491-4734-b669-3b598ee4eb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814145580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1814145580
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.495564649
Short name T805
Test name
Test status
Simulation time 1499290035 ps
CPU time 4.96 seconds
Started Jun 07 08:10:34 PM PDT 24
Finished Jun 07 08:10:43 PM PDT 24
Peak memory 232508 kb
Host smart-b59758e7-d122-4de4-9672-62ef4fb3bef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495564649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.495564649
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2843581614
Short name T639
Test name
Test status
Simulation time 1014171348 ps
CPU time 7.38 seconds
Started Jun 07 08:10:38 PM PDT 24
Finished Jun 07 08:10:49 PM PDT 24
Peak memory 232524 kb
Host smart-e99c0d26-67d9-4c27-93c5-f62b4374c183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843581614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2843581614
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.742597487
Short name T265
Test name
Test status
Simulation time 8339501968 ps
CPU time 10.23 seconds
Started Jun 07 08:10:39 PM PDT 24
Finished Jun 07 08:10:53 PM PDT 24
Peak memory 232588 kb
Host smart-f0a84f44-c43f-4a1d-9439-e01821c6341e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742597487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.742597487
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1669814860
Short name T791
Test name
Test status
Simulation time 3054137066 ps
CPU time 9.58 seconds
Started Jun 07 08:10:38 PM PDT 24
Finished Jun 07 08:10:52 PM PDT 24
Peak memory 224360 kb
Host smart-e693d744-f851-4fe4-ab06-2cb9b9b41dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669814860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1669814860
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3295470757
Short name T527
Test name
Test status
Simulation time 21379564452 ps
CPU time 110.51 seconds
Started Jun 07 08:10:44 PM PDT 24
Finished Jun 07 08:12:38 PM PDT 24
Peak memory 237908 kb
Host smart-35d66b85-cfc2-4fa0-9887-a5ee8d7032d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295470757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3295470757
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2510175261
Short name T289
Test name
Test status
Simulation time 3403698367 ps
CPU time 14.24 seconds
Started Jun 07 08:10:38 PM PDT 24
Finished Jun 07 08:10:57 PM PDT 24
Peak memory 218780 kb
Host smart-ad4e2379-3caf-40d9-83e1-d57dbefff92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510175261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2510175261
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3508999813
Short name T927
Test name
Test status
Simulation time 10072236197 ps
CPU time 5.19 seconds
Started Jun 07 08:10:36 PM PDT 24
Finished Jun 07 08:10:45 PM PDT 24
Peak memory 216140 kb
Host smart-d8278801-0eae-457c-9cb2-8999764e91a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508999813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3508999813
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1944975769
Short name T446
Test name
Test status
Simulation time 71434763 ps
CPU time 0.97 seconds
Started Jun 07 08:10:37 PM PDT 24
Finished Jun 07 08:10:42 PM PDT 24
Peak memory 206368 kb
Host smart-abe7de67-aa9c-47f5-a61c-1d1493a4105f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944975769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1944975769
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2101224738
Short name T314
Test name
Test status
Simulation time 220680788 ps
CPU time 0.89 seconds
Started Jun 07 08:10:38 PM PDT 24
Finished Jun 07 08:10:43 PM PDT 24
Peak memory 205608 kb
Host smart-ec10ad42-0e38-4c8e-9f10-627fa08084c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101224738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2101224738
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3009867249
Short name T883
Test name
Test status
Simulation time 1154470689 ps
CPU time 5.27 seconds
Started Jun 07 08:10:36 PM PDT 24
Finished Jun 07 08:10:45 PM PDT 24
Peak memory 224288 kb
Host smart-491643e9-94cd-46a7-bf97-021865233b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009867249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3009867249
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3842150362
Short name T321
Test name
Test status
Simulation time 53875904 ps
CPU time 0.77 seconds
Started Jun 07 08:10:42 PM PDT 24
Finished Jun 07 08:10:46 PM PDT 24
Peak memory 205140 kb
Host smart-3135024c-b297-4078-9484-00ca10ca13c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842150362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3842150362
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2930226549
Short name T792
Test name
Test status
Simulation time 576807111 ps
CPU time 6.3 seconds
Started Jun 07 08:10:46 PM PDT 24
Finished Jun 07 08:10:55 PM PDT 24
Peak memory 232488 kb
Host smart-b3bef577-ff32-4387-ad76-bb9afa620c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930226549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2930226549
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.929772829
Short name T685
Test name
Test status
Simulation time 14399802 ps
CPU time 0.78 seconds
Started Jun 07 08:10:44 PM PDT 24
Finished Jun 07 08:10:48 PM PDT 24
Peak memory 206256 kb
Host smart-a183a806-38d0-4aa9-bc02-e68d7eaeaba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929772829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.929772829
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.246019185
Short name T825
Test name
Test status
Simulation time 33165227 ps
CPU time 0.81 seconds
Started Jun 07 08:10:44 PM PDT 24
Finished Jun 07 08:10:47 PM PDT 24
Peak memory 215700 kb
Host smart-a9f0b6d3-8b6d-42ad-a0c7-e3b3b2df0e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246019185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.246019185
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3209467245
Short name T770
Test name
Test status
Simulation time 5604265533 ps
CPU time 61.37 seconds
Started Jun 07 08:10:44 PM PDT 24
Finished Jun 07 08:11:49 PM PDT 24
Peak memory 251284 kb
Host smart-8890043d-1b96-43e0-a95c-95047db2a575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209467245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3209467245
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1832771806
Short name T462
Test name
Test status
Simulation time 42762007400 ps
CPU time 116.83 seconds
Started Jun 07 08:10:42 PM PDT 24
Finished Jun 07 08:12:43 PM PDT 24
Peak memory 250036 kb
Host smart-2b8f5ff0-d540-46a5-b7fd-a748f65745a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832771806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1832771806
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3675007621
Short name T280
Test name
Test status
Simulation time 639389674 ps
CPU time 14.92 seconds
Started Jun 07 08:10:43 PM PDT 24
Finished Jun 07 08:11:01 PM PDT 24
Peak memory 232512 kb
Host smart-85dfd816-7365-468f-87c9-c113619c3c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675007621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3675007621
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.575487912
Short name T304
Test name
Test status
Simulation time 100529889 ps
CPU time 2.14 seconds
Started Jun 07 08:10:43 PM PDT 24
Finished Jun 07 08:10:49 PM PDT 24
Peak memory 222872 kb
Host smart-6d863c83-de94-49a1-b03c-553f22c42f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575487912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.575487912
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2267071970
Short name T313
Test name
Test status
Simulation time 8305620774 ps
CPU time 67.39 seconds
Started Jun 07 08:10:44 PM PDT 24
Finished Jun 07 08:11:54 PM PDT 24
Peak memory 239556 kb
Host smart-d121efe5-25c7-47c8-845b-823d40fb5d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267071970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2267071970
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1813358525
Short name T785
Test name
Test status
Simulation time 4859121825 ps
CPU time 17.63 seconds
Started Jun 07 08:10:45 PM PDT 24
Finished Jun 07 08:11:05 PM PDT 24
Peak memory 232580 kb
Host smart-86e3ddba-6d9d-4922-92b2-5a0f36e67895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813358525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1813358525
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2929746229
Short name T522
Test name
Test status
Simulation time 1704820270 ps
CPU time 12.56 seconds
Started Jun 07 08:10:43 PM PDT 24
Finished Jun 07 08:10:59 PM PDT 24
Peak memory 240544 kb
Host smart-38732461-3bf8-4b5b-a0a8-9b2f695c741f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929746229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2929746229
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2609954767
Short name T660
Test name
Test status
Simulation time 204733721 ps
CPU time 5.42 seconds
Started Jun 07 08:10:46 PM PDT 24
Finished Jun 07 08:10:54 PM PDT 24
Peak memory 222652 kb
Host smart-d5df4d26-f50b-449c-a6bc-3c7acf94b009
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2609954767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2609954767
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2046414308
Short name T127
Test name
Test status
Simulation time 64858274799 ps
CPU time 298.73 seconds
Started Jun 07 08:10:43 PM PDT 24
Finished Jun 07 08:15:45 PM PDT 24
Peak memory 248964 kb
Host smart-82a80850-740c-4743-8044-fb23c6b8de23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046414308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2046414308
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3685895099
Short name T600
Test name
Test status
Simulation time 311700256 ps
CPU time 2.02 seconds
Started Jun 07 08:10:43 PM PDT 24
Finished Jun 07 08:10:48 PM PDT 24
Peak memory 216048 kb
Host smart-c78bc9f0-1904-4bf6-8bbe-41b28ffd9555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685895099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3685895099
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3944651269
Short name T578
Test name
Test status
Simulation time 26410781281 ps
CPU time 15.59 seconds
Started Jun 07 08:10:45 PM PDT 24
Finished Jun 07 08:11:04 PM PDT 24
Peak memory 216140 kb
Host smart-92c9c6f0-04bc-4e87-a03f-8a40f37972b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944651269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3944651269
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.709938306
Short name T309
Test name
Test status
Simulation time 146873067 ps
CPU time 6.34 seconds
Started Jun 07 08:10:43 PM PDT 24
Finished Jun 07 08:10:52 PM PDT 24
Peak memory 216132 kb
Host smart-e5cc3b7d-5b90-42a2-b959-b4f1759c6b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709938306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.709938306
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1073043923
Short name T834
Test name
Test status
Simulation time 43055634 ps
CPU time 0.74 seconds
Started Jun 07 08:10:43 PM PDT 24
Finished Jun 07 08:10:47 PM PDT 24
Peak memory 205584 kb
Host smart-754a3180-4314-41d5-8e6b-f24da2b1de11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073043923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1073043923
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2511091557
Short name T171
Test name
Test status
Simulation time 5121837067 ps
CPU time 18.38 seconds
Started Jun 07 08:10:44 PM PDT 24
Finished Jun 07 08:11:06 PM PDT 24
Peak memory 224432 kb
Host smart-121edb20-e363-405d-a764-91eaf72ee431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511091557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2511091557
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2898641144
Short name T705
Test name
Test status
Simulation time 35819049 ps
CPU time 0.72 seconds
Started Jun 07 08:10:52 PM PDT 24
Finished Jun 07 08:10:55 PM PDT 24
Peak memory 205184 kb
Host smart-782325de-37ad-4ee0-bced-8adedfef46fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898641144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2898641144
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2076541858
Short name T904
Test name
Test status
Simulation time 123974163 ps
CPU time 2.57 seconds
Started Jun 07 08:10:52 PM PDT 24
Finished Jun 07 08:10:57 PM PDT 24
Peak memory 224312 kb
Host smart-0f39bbeb-dd1a-49db-b573-4bc218e3eed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076541858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2076541858
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2728560714
Short name T652
Test name
Test status
Simulation time 69988010 ps
CPU time 0.79 seconds
Started Jun 07 08:10:43 PM PDT 24
Finished Jun 07 08:10:47 PM PDT 24
Peak memory 206236 kb
Host smart-10019f69-97e5-41ea-a88a-0dfe13d2eee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728560714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2728560714
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.966199792
Short name T964
Test name
Test status
Simulation time 45037304516 ps
CPU time 187.62 seconds
Started Jun 07 08:10:55 PM PDT 24
Finished Jun 07 08:14:04 PM PDT 24
Peak memory 251832 kb
Host smart-49569b1e-0c78-4051-b59b-0d1e9a804a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966199792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.966199792
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1818473143
Short name T20
Test name
Test status
Simulation time 27077373070 ps
CPU time 232.16 seconds
Started Jun 07 08:10:52 PM PDT 24
Finished Jun 07 08:14:46 PM PDT 24
Peak memory 249052 kb
Host smart-2075966e-9219-441a-a858-0c35afae0cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818473143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1818473143
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1142330266
Short name T206
Test name
Test status
Simulation time 200182767187 ps
CPU time 493.12 seconds
Started Jun 07 08:10:54 PM PDT 24
Finished Jun 07 08:19:09 PM PDT 24
Peak memory 253084 kb
Host smart-8588d0a1-fab1-4b22-8caa-e2d09abed00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142330266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1142330266
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2951013110
Short name T134
Test name
Test status
Simulation time 1116703684 ps
CPU time 11.07 seconds
Started Jun 07 08:10:57 PM PDT 24
Finished Jun 07 08:11:09 PM PDT 24
Peak memory 234844 kb
Host smart-315e83c9-09c2-4ce5-a0d2-af65d0df451b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951013110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2951013110
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1387399504
Short name T262
Test name
Test status
Simulation time 150092343 ps
CPU time 5.06 seconds
Started Jun 07 08:10:54 PM PDT 24
Finished Jun 07 08:11:01 PM PDT 24
Peak memory 232516 kb
Host smart-6fcafaab-be78-42ed-aaa0-44d29ebc711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387399504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1387399504
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2278029813
Short name T383
Test name
Test status
Simulation time 34892636363 ps
CPU time 21.66 seconds
Started Jun 07 08:10:53 PM PDT 24
Finished Jun 07 08:11:17 PM PDT 24
Peak memory 240636 kb
Host smart-a345397d-12d2-4fc2-b1d3-d1331adb0171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278029813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2278029813
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1007768258
Short name T669
Test name
Test status
Simulation time 583170297 ps
CPU time 2.78 seconds
Started Jun 07 08:10:44 PM PDT 24
Finished Jun 07 08:10:49 PM PDT 24
Peak memory 232468 kb
Host smart-13cb081b-c942-406f-983c-454752e49aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007768258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1007768258
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.575191792
Short name T618
Test name
Test status
Simulation time 3191804648 ps
CPU time 4.76 seconds
Started Jun 07 08:10:44 PM PDT 24
Finished Jun 07 08:10:52 PM PDT 24
Peak memory 224400 kb
Host smart-6dd1dc58-f774-4de3-b062-1c733b2f37c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575191792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.575191792
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2936445933
Short name T948
Test name
Test status
Simulation time 2241279645 ps
CPU time 23.36 seconds
Started Jun 07 08:10:52 PM PDT 24
Finished Jun 07 08:11:17 PM PDT 24
Peak memory 220164 kb
Host smart-617c84e4-bb10-4236-9873-58bcc1ad1835
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2936445933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2936445933
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3463852625
Short name T824
Test name
Test status
Simulation time 9361099436 ps
CPU time 94.53 seconds
Started Jun 07 08:10:54 PM PDT 24
Finished Jun 07 08:12:31 PM PDT 24
Peak memory 252316 kb
Host smart-046e908b-2ce4-4f8e-889d-ad0aba945c5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463852625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3463852625
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1501091906
Short name T298
Test name
Test status
Simulation time 6092259824 ps
CPU time 23.19 seconds
Started Jun 07 08:10:48 PM PDT 24
Finished Jun 07 08:11:12 PM PDT 24
Peak memory 220060 kb
Host smart-aff82354-e746-4215-b90a-94e42e4791fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501091906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1501091906
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1473646244
Short name T695
Test name
Test status
Simulation time 512208017 ps
CPU time 3.79 seconds
Started Jun 07 08:10:48 PM PDT 24
Finished Jun 07 08:10:53 PM PDT 24
Peak memory 216008 kb
Host smart-47dd8e79-13f9-48b8-8f4a-c223684d38b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473646244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1473646244
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2406967501
Short name T712
Test name
Test status
Simulation time 30867724 ps
CPU time 1.35 seconds
Started Jun 07 08:10:43 PM PDT 24
Finished Jun 07 08:10:47 PM PDT 24
Peak memory 216060 kb
Host smart-397af680-87de-4701-816c-5dd1d388deb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406967501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2406967501
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.577453710
Short name T496
Test name
Test status
Simulation time 48471669 ps
CPU time 0.77 seconds
Started Jun 07 08:10:42 PM PDT 24
Finished Jun 07 08:10:46 PM PDT 24
Peak memory 205644 kb
Host smart-397516e8-f749-44a7-8532-b7b8caf52a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577453710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.577453710
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1358020379
Short name T725
Test name
Test status
Simulation time 607893461 ps
CPU time 3.07 seconds
Started Jun 07 08:10:54 PM PDT 24
Finished Jun 07 08:10:59 PM PDT 24
Peak memory 232548 kb
Host smart-e2199c78-4b88-4d5e-affa-068655598171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358020379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1358020379
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3883988203
Short name T330
Test name
Test status
Simulation time 105837221 ps
CPU time 0.74 seconds
Started Jun 07 08:10:52 PM PDT 24
Finished Jun 07 08:10:54 PM PDT 24
Peak memory 205516 kb
Host smart-fa6e8093-f6d3-4f3b-9bc1-fa58fa70b669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883988203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3883988203
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1016379987
Short name T882
Test name
Test status
Simulation time 523941234 ps
CPU time 3.71 seconds
Started Jun 07 08:10:51 PM PDT 24
Finished Jun 07 08:10:56 PM PDT 24
Peak memory 224380 kb
Host smart-8e30f513-7bd2-4011-9760-4c0ac32a2ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016379987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1016379987
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2090314693
Short name T588
Test name
Test status
Simulation time 14661905 ps
CPU time 0.77 seconds
Started Jun 07 08:10:52 PM PDT 24
Finished Jun 07 08:10:55 PM PDT 24
Peak memory 205216 kb
Host smart-f665523e-beca-4966-881c-e8ab1a5d7df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090314693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2090314693
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.717935875
Short name T842
Test name
Test status
Simulation time 47435882653 ps
CPU time 122.8 seconds
Started Jun 07 08:10:52 PM PDT 24
Finished Jun 07 08:12:56 PM PDT 24
Peak memory 248892 kb
Host smart-63dd2bb4-db3f-438e-bb2f-968994aa1a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717935875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.717935875
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2363804183
Short name T25
Test name
Test status
Simulation time 3723221404 ps
CPU time 48.73 seconds
Started Jun 07 08:10:54 PM PDT 24
Finished Jun 07 08:11:45 PM PDT 24
Peak memory 252356 kb
Host smart-defa35de-646f-4c1c-bf91-b0d31192879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363804183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2363804183
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1266653948
Short name T553
Test name
Test status
Simulation time 21842338828 ps
CPU time 187.16 seconds
Started Jun 07 08:10:57 PM PDT 24
Finished Jun 07 08:14:05 PM PDT 24
Peak memory 249032 kb
Host smart-90adbd02-c7be-4ce3-8c80-4372a130d10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266653948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1266653948
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1763014944
Short name T545
Test name
Test status
Simulation time 131380978 ps
CPU time 4.14 seconds
Started Jun 07 08:10:51 PM PDT 24
Finished Jun 07 08:10:57 PM PDT 24
Peak memory 224340 kb
Host smart-48f77b94-c1cd-469e-b622-fdd1fd31ace3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763014944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1763014944
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2710654713
Short name T726
Test name
Test status
Simulation time 679992861 ps
CPU time 9.14 seconds
Started Jun 07 08:10:55 PM PDT 24
Finished Jun 07 08:11:06 PM PDT 24
Peak memory 232520 kb
Host smart-d56d06c6-550b-475c-936b-4e849142849c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710654713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2710654713
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.168352640
Short name T430
Test name
Test status
Simulation time 33182541 ps
CPU time 2.52 seconds
Started Jun 07 08:10:55 PM PDT 24
Finished Jun 07 08:10:59 PM PDT 24
Peak memory 226388 kb
Host smart-3252adfa-cd7a-4e3a-8808-985b0467972b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168352640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.168352640
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1427617088
Short name T46
Test name
Test status
Simulation time 5465418285 ps
CPU time 11.16 seconds
Started Jun 07 08:10:51 PM PDT 24
Finished Jun 07 08:11:03 PM PDT 24
Peak memory 232568 kb
Host smart-0fe134ea-f8b7-4c50-9020-9afac1620952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427617088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1427617088
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3188112224
Short name T248
Test name
Test status
Simulation time 212340214 ps
CPU time 3.89 seconds
Started Jun 07 08:10:53 PM PDT 24
Finished Jun 07 08:10:59 PM PDT 24
Peak memory 232640 kb
Host smart-5c2c9e8e-0fff-4287-8868-a94e47906f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188112224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3188112224
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2256040282
Short name T531
Test name
Test status
Simulation time 263713605 ps
CPU time 3.51 seconds
Started Jun 07 08:10:52 PM PDT 24
Finished Jun 07 08:10:57 PM PDT 24
Peak memory 222724 kb
Host smart-a63cd307-6160-4f34-a3f7-99915eec9a6f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2256040282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2256040282
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.4254351702
Short name T796
Test name
Test status
Simulation time 52453511529 ps
CPU time 121.48 seconds
Started Jun 07 08:10:55 PM PDT 24
Finished Jun 07 08:12:58 PM PDT 24
Peak memory 265420 kb
Host smart-549c66de-c913-40a9-bc1e-1ada1bd2c90e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254351702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.4254351702
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1955442529
Short name T653
Test name
Test status
Simulation time 17627324423 ps
CPU time 41.9 seconds
Started Jun 07 08:10:57 PM PDT 24
Finished Jun 07 08:11:40 PM PDT 24
Peak memory 216124 kb
Host smart-93b86fac-e720-45ef-b4c5-491589f7a2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955442529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1955442529
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2551546656
Short name T307
Test name
Test status
Simulation time 525981066 ps
CPU time 1.61 seconds
Started Jun 07 08:10:53 PM PDT 24
Finished Jun 07 08:10:57 PM PDT 24
Peak memory 206764 kb
Host smart-649f96ee-83fc-4349-aae3-5d9de0666846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551546656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2551546656
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1293136017
Short name T672
Test name
Test status
Simulation time 41205526 ps
CPU time 0.93 seconds
Started Jun 07 08:10:53 PM PDT 24
Finished Jun 07 08:10:56 PM PDT 24
Peak memory 206532 kb
Host smart-341059f6-fba4-417f-b55a-c030a3f7b065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293136017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1293136017
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1559401598
Short name T715
Test name
Test status
Simulation time 68421387 ps
CPU time 0.83 seconds
Started Jun 07 08:10:52 PM PDT 24
Finished Jun 07 08:10:54 PM PDT 24
Peak memory 205608 kb
Host smart-f8e9266b-95f2-49f9-9c28-676da772913f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559401598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1559401598
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4223179345
Short name T730
Test name
Test status
Simulation time 729554520 ps
CPU time 3.76 seconds
Started Jun 07 08:10:53 PM PDT 24
Finished Jun 07 08:10:59 PM PDT 24
Peak memory 224316 kb
Host smart-d011fbb7-f9d9-4d51-8980-cecab5bd5e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223179345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4223179345
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1717741546
Short name T67
Test name
Test status
Simulation time 40099413 ps
CPU time 0.78 seconds
Started Jun 07 08:11:03 PM PDT 24
Finished Jun 07 08:11:06 PM PDT 24
Peak memory 204528 kb
Host smart-494473ac-82cf-4d1d-8e52-c085d880474d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717741546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1717741546
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2338753244
Short name T633
Test name
Test status
Simulation time 405037691 ps
CPU time 2.95 seconds
Started Jun 07 08:10:59 PM PDT 24
Finished Jun 07 08:11:03 PM PDT 24
Peak memory 232464 kb
Host smart-09479918-79a0-4a0b-b5fa-0787270ae264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338753244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2338753244
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.958922563
Short name T896
Test name
Test status
Simulation time 56790171 ps
CPU time 0.75 seconds
Started Jun 07 08:10:52 PM PDT 24
Finished Jun 07 08:10:55 PM PDT 24
Peak memory 206180 kb
Host smart-0a08dec2-9db4-4ff1-ad8a-8c3b07cd5aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958922563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.958922563
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1169996115
Short name T267
Test name
Test status
Simulation time 5841869549 ps
CPU time 40 seconds
Started Jun 07 08:11:05 PM PDT 24
Finished Jun 07 08:11:47 PM PDT 24
Peak memory 248992 kb
Host smart-56021e45-c376-4e00-8c2e-ad4270342c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169996115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1169996115
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2897932510
Short name T37
Test name
Test status
Simulation time 16819824267 ps
CPU time 106.59 seconds
Started Jun 07 08:11:02 PM PDT 24
Finished Jun 07 08:12:51 PM PDT 24
Peak memory 265448 kb
Host smart-5f3cc3fa-8ff9-4cb8-ba61-bb7ac7b88649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897932510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2897932510
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1303260129
Short name T663
Test name
Test status
Simulation time 15328370111 ps
CPU time 65.15 seconds
Started Jun 07 08:11:00 PM PDT 24
Finished Jun 07 08:12:08 PM PDT 24
Peak memory 240964 kb
Host smart-afc2a92a-18dd-497b-b3e9-43a372b15562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303260129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1303260129
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3920369688
Short name T589
Test name
Test status
Simulation time 242339817 ps
CPU time 4.76 seconds
Started Jun 07 08:11:02 PM PDT 24
Finished Jun 07 08:11:09 PM PDT 24
Peak memory 224452 kb
Host smart-9ec083de-0f39-4f56-8d09-14d904bbfb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920369688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3920369688
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.940104405
Short name T718
Test name
Test status
Simulation time 212632257 ps
CPU time 2.63 seconds
Started Jun 07 08:11:03 PM PDT 24
Finished Jun 07 08:11:08 PM PDT 24
Peak memory 232500 kb
Host smart-c8d5e91b-6b26-4f76-8546-a8f86d0b05dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940104405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.940104405
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3534442616
Short name T638
Test name
Test status
Simulation time 1049968381 ps
CPU time 11.1 seconds
Started Jun 07 08:11:02 PM PDT 24
Finished Jun 07 08:11:16 PM PDT 24
Peak memory 224280 kb
Host smart-744da9a2-dd3f-4e88-9e5a-c544ac882fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534442616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3534442616
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3341431490
Short name T788
Test name
Test status
Simulation time 15892209810 ps
CPU time 19.07 seconds
Started Jun 07 08:11:02 PM PDT 24
Finished Jun 07 08:11:24 PM PDT 24
Peak memory 256516 kb
Host smart-5f199bc0-895b-45df-aace-e3f67ffdc62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341431490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3341431490
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3706536090
Short name T930
Test name
Test status
Simulation time 6283888294 ps
CPU time 8.21 seconds
Started Jun 07 08:11:01 PM PDT 24
Finished Jun 07 08:11:12 PM PDT 24
Peak memory 232640 kb
Host smart-7581f14b-9dec-498a-bff9-b4fbd30e0639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706536090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3706536090
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3007953617
Short name T587
Test name
Test status
Simulation time 3943641309 ps
CPU time 9.14 seconds
Started Jun 07 08:11:00 PM PDT 24
Finished Jun 07 08:11:11 PM PDT 24
Peak memory 219100 kb
Host smart-6d077f3c-531c-49df-8380-d90a8e9f81f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3007953617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3007953617
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.278752296
Short name T648
Test name
Test status
Simulation time 1035280049 ps
CPU time 15.01 seconds
Started Jun 07 08:11:01 PM PDT 24
Finished Jun 07 08:11:19 PM PDT 24
Peak memory 224428 kb
Host smart-d125b1ab-e55c-4c48-af4e-67c24d965ca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278752296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.278752296
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3755297562
Short name T499
Test name
Test status
Simulation time 393021273 ps
CPU time 3.32 seconds
Started Jun 07 08:10:50 PM PDT 24
Finished Jun 07 08:10:55 PM PDT 24
Peak memory 216028 kb
Host smart-bd9de815-3ae1-47f2-9fee-a98e8546ef4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755297562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3755297562
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3432392595
Short name T575
Test name
Test status
Simulation time 500921932 ps
CPU time 1.93 seconds
Started Jun 07 08:10:52 PM PDT 24
Finished Jun 07 08:10:56 PM PDT 24
Peak memory 215876 kb
Host smart-ffcf1f40-bf20-4c20-84a0-38a13c82b9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432392595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3432392595
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2354475632
Short name T13
Test name
Test status
Simulation time 180929603 ps
CPU time 7.11 seconds
Started Jun 07 08:10:58 PM PDT 24
Finished Jun 07 08:11:07 PM PDT 24
Peak memory 216172 kb
Host smart-c9c64cb0-e72a-44e3-99c6-544f90738d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354475632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2354475632
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3573280570
Short name T934
Test name
Test status
Simulation time 38687380 ps
CPU time 0.7 seconds
Started Jun 07 08:10:54 PM PDT 24
Finished Jun 07 08:10:56 PM PDT 24
Peak memory 205220 kb
Host smart-de6d2517-f1b7-4616-a9ad-c020d6a0b722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573280570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3573280570
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3714325709
Short name T702
Test name
Test status
Simulation time 1813427207 ps
CPU time 2.3 seconds
Started Jun 07 08:10:57 PM PDT 24
Finished Jun 07 08:11:00 PM PDT 24
Peak memory 224124 kb
Host smart-802db363-2e3b-4cc1-ab37-7f96e64dffe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714325709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3714325709
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3617742624
Short name T498
Test name
Test status
Simulation time 33502771 ps
CPU time 0.69 seconds
Started Jun 07 08:11:01 PM PDT 24
Finished Jun 07 08:11:04 PM PDT 24
Peak memory 204540 kb
Host smart-825e6385-2a14-442a-aa4e-87d5c354f4f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617742624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3617742624
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3962649933
Short name T310
Test name
Test status
Simulation time 43388143 ps
CPU time 2.58 seconds
Started Jun 07 08:11:04 PM PDT 24
Finished Jun 07 08:11:09 PM PDT 24
Peak memory 232552 kb
Host smart-f8ef8d3d-ab9a-4e8c-af31-dc38cbf66dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962649933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3962649933
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.713477014
Short name T840
Test name
Test status
Simulation time 19623699 ps
CPU time 0.75 seconds
Started Jun 07 08:11:01 PM PDT 24
Finished Jun 07 08:11:05 PM PDT 24
Peak memory 205272 kb
Host smart-d0f3077c-a127-4c31-b153-98284e38cbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713477014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.713477014
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3907967556
Short name T800
Test name
Test status
Simulation time 127323102670 ps
CPU time 221.87 seconds
Started Jun 07 08:11:02 PM PDT 24
Finished Jun 07 08:14:47 PM PDT 24
Peak memory 248980 kb
Host smart-1f80c8aa-cd1c-485e-82fd-330b530ab1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907967556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3907967556
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.163042113
Short name T54
Test name
Test status
Simulation time 25164443509 ps
CPU time 157.73 seconds
Started Jun 07 08:10:58 PM PDT 24
Finished Jun 07 08:13:37 PM PDT 24
Peak memory 251272 kb
Host smart-867e28d7-4cec-48a0-9bcc-6974df08a71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163042113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.163042113
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.110727259
Short name T914
Test name
Test status
Simulation time 5953071639 ps
CPU time 22.69 seconds
Started Jun 07 08:10:58 PM PDT 24
Finished Jun 07 08:11:21 PM PDT 24
Peak memory 224500 kb
Host smart-40a1a99d-c742-467a-a726-ced8b8bf6214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110727259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.110727259
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3420576468
Short name T611
Test name
Test status
Simulation time 2513950629 ps
CPU time 6.36 seconds
Started Jun 07 08:11:00 PM PDT 24
Finished Jun 07 08:11:08 PM PDT 24
Peak memory 232576 kb
Host smart-86b78264-7b45-4e08-9202-ee44b98bec7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420576468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3420576468
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.930034234
Short name T530
Test name
Test status
Simulation time 9747592559 ps
CPU time 36.11 seconds
Started Jun 07 08:11:04 PM PDT 24
Finished Jun 07 08:11:42 PM PDT 24
Peak memory 232556 kb
Host smart-6c3f164c-6054-492c-b5ee-a2dc2babd811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930034234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.930034234
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2837901869
Short name T709
Test name
Test status
Simulation time 2035234941 ps
CPU time 7.26 seconds
Started Jun 07 08:10:59 PM PDT 24
Finished Jun 07 08:11:08 PM PDT 24
Peak memory 224336 kb
Host smart-f6e880cb-42f8-410c-8c79-445929a68bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837901869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2837901869
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1045098444
Short name T401
Test name
Test status
Simulation time 490089383 ps
CPU time 7.82 seconds
Started Jun 07 08:11:01 PM PDT 24
Finished Jun 07 08:11:11 PM PDT 24
Peak memory 240688 kb
Host smart-ff5ee455-0c83-4934-8b08-f93c5536fb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045098444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1045098444
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.4181980844
Short name T535
Test name
Test status
Simulation time 36943222612 ps
CPU time 20.22 seconds
Started Jun 07 08:11:00 PM PDT 24
Finished Jun 07 08:11:21 PM PDT 24
Peak memory 220184 kb
Host smart-cb829edb-740f-48bb-af44-cbc80fd78e68
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4181980844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.4181980844
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4260743224
Short name T849
Test name
Test status
Simulation time 9158152661 ps
CPU time 58.28 seconds
Started Jun 07 08:10:57 PM PDT 24
Finished Jun 07 08:11:57 PM PDT 24
Peak memory 240676 kb
Host smart-32e8e833-8c09-4d4c-929c-4e9f6ae280d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260743224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4260743224
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2023254865
Short name T511
Test name
Test status
Simulation time 5402463839 ps
CPU time 27.83 seconds
Started Jun 07 08:11:01 PM PDT 24
Finished Jun 07 08:11:31 PM PDT 24
Peak memory 216112 kb
Host smart-46741e4b-60b5-42f7-971f-fd344996315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023254865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2023254865
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2178102003
Short name T364
Test name
Test status
Simulation time 165541940550 ps
CPU time 23.09 seconds
Started Jun 07 08:11:00 PM PDT 24
Finished Jun 07 08:11:25 PM PDT 24
Peak memory 216120 kb
Host smart-43d06a5e-419f-4487-ad9e-79827135320f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178102003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2178102003
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.591261066
Short name T312
Test name
Test status
Simulation time 66846897 ps
CPU time 1.12 seconds
Started Jun 07 08:10:59 PM PDT 24
Finished Jun 07 08:11:02 PM PDT 24
Peak memory 206680 kb
Host smart-ce9e26c0-d48d-4077-91f2-1016a43a58b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591261066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.591261066
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.680532217
Short name T899
Test name
Test status
Simulation time 47036676 ps
CPU time 0.77 seconds
Started Jun 07 08:11:03 PM PDT 24
Finished Jun 07 08:11:06 PM PDT 24
Peak memory 205584 kb
Host smart-514bf8ff-dca6-4df0-9a5b-a2c4e2d8a5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680532217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.680532217
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.448038864
Short name T517
Test name
Test status
Simulation time 5692740487 ps
CPU time 15.08 seconds
Started Jun 07 08:11:05 PM PDT 24
Finished Jun 07 08:11:23 PM PDT 24
Peak memory 232636 kb
Host smart-6306370c-c0df-4899-acc3-299c8f2f9d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448038864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.448038864
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1078531277
Short name T763
Test name
Test status
Simulation time 15554979 ps
CPU time 0.77 seconds
Started Jun 07 08:11:00 PM PDT 24
Finished Jun 07 08:11:03 PM PDT 24
Peak memory 204552 kb
Host smart-3700b28e-2e67-486a-8e36-62f333c7c6d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078531277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1078531277
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4114596693
Short name T820
Test name
Test status
Simulation time 6752586114 ps
CPU time 13.74 seconds
Started Jun 07 08:10:59 PM PDT 24
Finished Jun 07 08:11:15 PM PDT 24
Peak memory 232616 kb
Host smart-cde6c2c1-cde2-4aac-8329-6d15cb6b45e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114596693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4114596693
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.634893955
Short name T377
Test name
Test status
Simulation time 47051014 ps
CPU time 0.79 seconds
Started Jun 07 08:11:00 PM PDT 24
Finished Jun 07 08:11:03 PM PDT 24
Peak memory 206232 kb
Host smart-f90743db-de0a-4bee-9249-02d8434bf125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634893955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.634893955
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2039149590
Short name T510
Test name
Test status
Simulation time 64978034142 ps
CPU time 126.92 seconds
Started Jun 07 08:10:59 PM PDT 24
Finished Jun 07 08:13:07 PM PDT 24
Peak memory 250004 kb
Host smart-29b6f679-aec0-4146-bf1c-d540b9ec3485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039149590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2039149590
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3896413845
Short name T258
Test name
Test status
Simulation time 59816890169 ps
CPU time 254.5 seconds
Started Jun 07 08:11:00 PM PDT 24
Finished Jun 07 08:15:17 PM PDT 24
Peak memory 251676 kb
Host smart-1c04f11f-7dca-48cd-84a0-26146cfbce6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896413845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3896413845
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2733934175
Short name T277
Test name
Test status
Simulation time 2311999551 ps
CPU time 34.8 seconds
Started Jun 07 08:11:05 PM PDT 24
Finished Jun 07 08:11:42 PM PDT 24
Peak memory 240688 kb
Host smart-209e8be7-72c2-46bc-b8d2-38478ac8d33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733934175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2733934175
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3340247940
Short name T804
Test name
Test status
Simulation time 118277048 ps
CPU time 3.88 seconds
Started Jun 07 08:11:03 PM PDT 24
Finished Jun 07 08:11:10 PM PDT 24
Peak memory 224240 kb
Host smart-1eba8a19-2f8c-4e3c-b0b9-e898615dee0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340247940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3340247940
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2195484586
Short name T691
Test name
Test status
Simulation time 6232435009 ps
CPU time 10.46 seconds
Started Jun 07 08:10:58 PM PDT 24
Finished Jun 07 08:11:09 PM PDT 24
Peak memory 232600 kb
Host smart-f8bdc6e0-0b87-4f99-9d9e-1a2c589f720a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195484586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2195484586
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.199837038
Short name T666
Test name
Test status
Simulation time 5674071929 ps
CPU time 16.33 seconds
Started Jun 07 08:11:01 PM PDT 24
Finished Jun 07 08:11:20 PM PDT 24
Peak memory 232532 kb
Host smart-a761f9ff-975b-4d6e-a386-79476a14017e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199837038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.199837038
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1941871321
Short name T812
Test name
Test status
Simulation time 404847789 ps
CPU time 2.32 seconds
Started Jun 07 08:11:05 PM PDT 24
Finished Jun 07 08:11:10 PM PDT 24
Peak memory 224296 kb
Host smart-b1bd48de-1d18-4598-9be7-146ae5f966dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941871321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1941871321
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2481552018
Short name T845
Test name
Test status
Simulation time 1296839032 ps
CPU time 9.29 seconds
Started Jun 07 08:11:06 PM PDT 24
Finished Jun 07 08:11:17 PM PDT 24
Peak memory 222172 kb
Host smart-f6a30e21-80b5-4f41-bab1-8391110e3eae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2481552018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2481552018
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2380631745
Short name T704
Test name
Test status
Simulation time 15709047656 ps
CPU time 53.79 seconds
Started Jun 07 08:11:05 PM PDT 24
Finished Jun 07 08:12:01 PM PDT 24
Peak memory 232504 kb
Host smart-d2412e3f-203f-4988-8d84-f441b64690a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380631745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2380631745
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2380107194
Short name T299
Test name
Test status
Simulation time 14106985752 ps
CPU time 35.82 seconds
Started Jun 07 08:11:02 PM PDT 24
Finished Jun 07 08:11:40 PM PDT 24
Peak memory 216196 kb
Host smart-d5391068-b1c7-49a9-be1a-1b6922b58bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380107194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2380107194
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.187782385
Short name T455
Test name
Test status
Simulation time 3365247780 ps
CPU time 4.23 seconds
Started Jun 07 08:10:59 PM PDT 24
Finished Jun 07 08:11:05 PM PDT 24
Peak memory 216144 kb
Host smart-cb28f9d8-04f7-4600-b7c6-ae8c979985b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187782385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.187782385
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1124669306
Short name T692
Test name
Test status
Simulation time 137581543 ps
CPU time 1.17 seconds
Started Jun 07 08:10:59 PM PDT 24
Finished Jun 07 08:11:01 PM PDT 24
Peak memory 216112 kb
Host smart-ce148bbf-c3d2-45a8-aa52-3f5fd31f9617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124669306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1124669306
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1515678564
Short name T3
Test name
Test status
Simulation time 636779715 ps
CPU time 0.82 seconds
Started Jun 07 08:11:00 PM PDT 24
Finished Jun 07 08:11:03 PM PDT 24
Peak memory 205828 kb
Host smart-9e3ab2b0-bef9-4883-8d0a-aba4731a0f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515678564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1515678564
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.415131971
Short name T855
Test name
Test status
Simulation time 3674745350 ps
CPU time 6.04 seconds
Started Jun 07 08:11:02 PM PDT 24
Finished Jun 07 08:11:10 PM PDT 24
Peak memory 224428 kb
Host smart-9bcca344-387d-4091-97b2-a426d2857903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415131971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.415131971
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1578718728
Short name T520
Test name
Test status
Simulation time 27765591 ps
CPU time 0.72 seconds
Started Jun 07 08:11:05 PM PDT 24
Finished Jun 07 08:11:08 PM PDT 24
Peak memory 205180 kb
Host smart-3faa9924-353e-46e5-bcc6-885be47756d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578718728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1578718728
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2822716010
Short name T848
Test name
Test status
Simulation time 5913106895 ps
CPU time 25.68 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:11:36 PM PDT 24
Peak memory 232568 kb
Host smart-71cbb967-d476-4cd4-82e6-6c944603b6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822716010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2822716010
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2995655333
Short name T345
Test name
Test status
Simulation time 35179005 ps
CPU time 0.84 seconds
Started Jun 07 08:11:03 PM PDT 24
Finished Jun 07 08:11:06 PM PDT 24
Peak memory 206212 kb
Host smart-ad4a44e4-f3bd-4b4d-a322-ebd1345a12d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995655333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2995655333
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3437935407
Short name T338
Test name
Test status
Simulation time 37785898672 ps
CPU time 48.54 seconds
Started Jun 07 08:11:09 PM PDT 24
Finished Jun 07 08:12:00 PM PDT 24
Peak memory 252712 kb
Host smart-826f70f3-ba34-4dfb-87f1-e2ce24218054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437935407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3437935407
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1694307454
Short name T971
Test name
Test status
Simulation time 61536519916 ps
CPU time 622.87 seconds
Started Jun 07 08:11:06 PM PDT 24
Finished Jun 07 08:21:31 PM PDT 24
Peak memory 252704 kb
Host smart-b12dd9d7-7dca-4416-b22c-d158db8ddc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694307454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1694307454
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1267656840
Short name T195
Test name
Test status
Simulation time 6118200423 ps
CPU time 80.29 seconds
Started Jun 07 08:11:09 PM PDT 24
Finished Jun 07 08:12:32 PM PDT 24
Peak memory 256220 kb
Host smart-47a6f378-8e37-4155-9e5b-c211fcf29689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267656840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1267656840
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.338178435
Short name T596
Test name
Test status
Simulation time 545413177 ps
CPU time 4.86 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:11:14 PM PDT 24
Peak memory 224260 kb
Host smart-55db5615-8727-4b4f-bfad-360d5fb129da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338178435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.338178435
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1745052882
Short name T363
Test name
Test status
Simulation time 2723288312 ps
CPU time 3.76 seconds
Started Jun 07 08:11:09 PM PDT 24
Finished Jun 07 08:11:15 PM PDT 24
Peak memory 224336 kb
Host smart-20f3f724-1a59-42d4-93fa-93cf5d97e66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745052882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1745052882
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.850185550
Short name T492
Test name
Test status
Simulation time 186797562886 ps
CPU time 153.21 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:13:42 PM PDT 24
Peak memory 248912 kb
Host smart-1a3748c0-5463-4e6e-8c53-15e0739d565c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850185550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.850185550
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.114304728
Short name T719
Test name
Test status
Simulation time 811587172 ps
CPU time 9.7 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:11:19 PM PDT 24
Peak memory 224352 kb
Host smart-00ebb60c-135a-4610-ad73-a648e0f5fb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114304728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.114304728
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3982582193
Short name T190
Test name
Test status
Simulation time 14589622945 ps
CPU time 17.4 seconds
Started Jun 07 08:11:08 PM PDT 24
Finished Jun 07 08:11:28 PM PDT 24
Peak memory 240628 kb
Host smart-5e71b997-f877-4b28-8ff7-2ff0a9a8608a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982582193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3982582193
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.626143282
Short name T938
Test name
Test status
Simulation time 9534667613 ps
CPU time 12.07 seconds
Started Jun 07 08:11:05 PM PDT 24
Finished Jun 07 08:11:19 PM PDT 24
Peak memory 222900 kb
Host smart-76445462-b087-4798-bc7b-dcd2fa84a6fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=626143282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.626143282
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.395177309
Short name T761
Test name
Test status
Simulation time 48186932 ps
CPU time 0.96 seconds
Started Jun 07 08:11:08 PM PDT 24
Finished Jun 07 08:11:11 PM PDT 24
Peak memory 206560 kb
Host smart-8f98f010-66b5-49f3-b581-5958f5675893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395177309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.395177309
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.989677064
Short name T288
Test name
Test status
Simulation time 21818997576 ps
CPU time 36.04 seconds
Started Jun 07 08:11:01 PM PDT 24
Finished Jun 07 08:11:39 PM PDT 24
Peak memory 216164 kb
Host smart-ebe0f39d-b484-4041-a96e-bb980c61d8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989677064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.989677064
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3421140889
Short name T407
Test name
Test status
Simulation time 20202579084 ps
CPU time 11.45 seconds
Started Jun 07 08:11:01 PM PDT 24
Finished Jun 07 08:11:15 PM PDT 24
Peak memory 216160 kb
Host smart-66e2bcb4-e6a0-456c-8580-890e701147ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421140889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3421140889
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.720571340
Short name T951
Test name
Test status
Simulation time 36426342 ps
CPU time 1.53 seconds
Started Jun 07 08:11:08 PM PDT 24
Finished Jun 07 08:11:12 PM PDT 24
Peak memory 216072 kb
Host smart-eb4b9b82-3a45-4550-a9f1-acba1eca4f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720571340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.720571340
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3778635313
Short name T484
Test name
Test status
Simulation time 138786615 ps
CPU time 0.78 seconds
Started Jun 07 08:11:05 PM PDT 24
Finished Jun 07 08:11:07 PM PDT 24
Peak memory 205620 kb
Host smart-8f205ceb-6b16-4388-9006-e5e74c302688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778635313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3778635313
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2449131014
Short name T261
Test name
Test status
Simulation time 658135254 ps
CPU time 5.32 seconds
Started Jun 07 08:11:08 PM PDT 24
Finished Jun 07 08:11:16 PM PDT 24
Peak memory 224336 kb
Host smart-f815c383-a654-48cb-bd78-77f98cd526ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449131014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2449131014
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.732220634
Short name T777
Test name
Test status
Simulation time 13960271 ps
CPU time 0.71 seconds
Started Jun 07 08:09:17 PM PDT 24
Finished Jun 07 08:09:25 PM PDT 24
Peak memory 205048 kb
Host smart-ce581cf7-01d3-4642-99e6-7a24734a78cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732220634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.732220634
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2733346819
Short name T847
Test name
Test status
Simulation time 217362962 ps
CPU time 2.67 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:23 PM PDT 24
Peak memory 224060 kb
Host smart-4860fe93-9d27-4774-abed-1e848c00265f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733346819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2733346819
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1695844491
Short name T19
Test name
Test status
Simulation time 58361341 ps
CPU time 0.76 seconds
Started Jun 07 08:09:10 PM PDT 24
Finished Jun 07 08:09:12 PM PDT 24
Peak memory 205224 kb
Host smart-58eb57d7-802f-4723-a214-15b6fbf3374b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695844491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1695844491
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.544699853
Short name T818
Test name
Test status
Simulation time 65622595394 ps
CPU time 151.14 seconds
Started Jun 07 08:09:12 PM PDT 24
Finished Jun 07 08:11:47 PM PDT 24
Peak memory 256108 kb
Host smart-9e86e4d0-73b1-4ebb-9656-c35a08dae702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544699853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.544699853
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3527850615
Short name T41
Test name
Test status
Simulation time 40136081283 ps
CPU time 434.43 seconds
Started Jun 07 08:09:12 PM PDT 24
Finished Jun 07 08:16:30 PM PDT 24
Peak memory 253228 kb
Host smart-b6272695-b660-4bcf-a8ba-060b93fad46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527850615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3527850615
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2573369326
Short name T5
Test name
Test status
Simulation time 55090710 ps
CPU time 2.2 seconds
Started Jun 07 08:09:10 PM PDT 24
Finished Jun 07 08:09:14 PM PDT 24
Peak memory 224380 kb
Host smart-3d5c43f2-25b8-4e51-8c83-140e343b6acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573369326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2573369326
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.915844533
Short name T77
Test name
Test status
Simulation time 1611137207 ps
CPU time 7.02 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:22 PM PDT 24
Peak memory 232604 kb
Host smart-02596177-2b4c-4b3a-aa83-3528e0b73272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915844533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.915844533
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1551187364
Short name T623
Test name
Test status
Simulation time 1373436461 ps
CPU time 9.98 seconds
Started Jun 07 08:09:15 PM PDT 24
Finished Jun 07 08:09:32 PM PDT 24
Peak memory 224328 kb
Host smart-ebca91d6-9ef4-4e2e-aa48-696d42565e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551187364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1551187364
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.122743008
Short name T372
Test name
Test status
Simulation time 232801226 ps
CPU time 1.06 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:20 PM PDT 24
Peak memory 216380 kb
Host smart-d3f68486-d7f9-4762-808d-1b6a58e8e0b8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122743008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.122743008
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2294176768
Short name T542
Test name
Test status
Simulation time 7327404578 ps
CPU time 10.46 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:29 PM PDT 24
Peak memory 232548 kb
Host smart-d69d12fc-54e8-4b62-86f3-cb354ed11b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294176768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2294176768
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3859544958
Short name T662
Test name
Test status
Simulation time 6356274384 ps
CPU time 20.36 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:33 PM PDT 24
Peak memory 227884 kb
Host smart-9ffcc17b-ba11-4837-9649-c716678f648d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859544958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3859544958
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.633318148
Short name T567
Test name
Test status
Simulation time 2644284100 ps
CPU time 15.11 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:32 PM PDT 24
Peak memory 222000 kb
Host smart-9d448538-eb8d-45ee-8354-149a27f1a590
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=633318148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.633318148
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.4294061643
Short name T154
Test name
Test status
Simulation time 84718287576 ps
CPU time 741.79 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:21:42 PM PDT 24
Peak memory 269432 kb
Host smart-253ebf2d-be55-4386-a2f3-5b77f588f875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294061643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.4294061643
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1599643097
Short name T884
Test name
Test status
Simulation time 2316032738 ps
CPU time 8.2 seconds
Started Jun 07 08:09:16 PM PDT 24
Finished Jun 07 08:09:30 PM PDT 24
Peak memory 216444 kb
Host smart-311c966e-91ab-4cf2-b6c0-b49225cd4da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599643097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1599643097
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1481268154
Short name T738
Test name
Test status
Simulation time 2111868345 ps
CPU time 6.74 seconds
Started Jun 07 08:09:12 PM PDT 24
Finished Jun 07 08:09:22 PM PDT 24
Peak memory 216068 kb
Host smart-6c5cadbf-0d1a-454e-9a23-04d74110416d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481268154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1481268154
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.229411923
Short name T656
Test name
Test status
Simulation time 109223671 ps
CPU time 1.21 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:15 PM PDT 24
Peak memory 207100 kb
Host smart-d215bd3d-60e3-424b-a3db-cca8e91848b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229411923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.229411923
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3551393408
Short name T369
Test name
Test status
Simulation time 122410651 ps
CPU time 0.79 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:16 PM PDT 24
Peak memory 205596 kb
Host smart-6b6f07be-1b7c-48f9-a0ee-ca41b485eb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551393408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3551393408
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4110784507
Short name T582
Test name
Test status
Simulation time 3495686857 ps
CPU time 8.87 seconds
Started Jun 07 08:09:12 PM PDT 24
Finished Jun 07 08:09:26 PM PDT 24
Peak memory 232624 kb
Host smart-aa7a2f8a-13c9-45f0-9d1a-23ef82be9792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110784507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4110784507
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2024586528
Short name T334
Test name
Test status
Simulation time 11129619 ps
CPU time 0.73 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:11:09 PM PDT 24
Peak memory 205520 kb
Host smart-c409d493-ca08-45bb-ba42-1459b33b33ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024586528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2024586528
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.548248820
Short name T972
Test name
Test status
Simulation time 4639582986 ps
CPU time 11.02 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:11:21 PM PDT 24
Peak memory 224376 kb
Host smart-bf7e4dbc-d7d1-43c9-9cb7-ac5c1980e01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548248820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.548248820
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.228312901
Short name T443
Test name
Test status
Simulation time 50512481 ps
CPU time 0.75 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:11:10 PM PDT 24
Peak memory 206116 kb
Host smart-88d9b320-31f8-485b-aec1-d679a8cff63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228312901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.228312901
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3473574941
Short name T203
Test name
Test status
Simulation time 34426047329 ps
CPU time 291.14 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:16:01 PM PDT 24
Peak memory 254652 kb
Host smart-8a0c4661-bc2a-48f5-b703-6cd1374f8c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473574941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3473574941
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2843732047
Short name T750
Test name
Test status
Simulation time 8425131893 ps
CPU time 48.06 seconds
Started Jun 07 08:11:06 PM PDT 24
Finished Jun 07 08:11:56 PM PDT 24
Peak memory 232604 kb
Host smart-65838d9a-3410-44af-aee4-9022193e5af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843732047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2843732047
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.590605908
Short name T439
Test name
Test status
Simulation time 31571165 ps
CPU time 2.66 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:11:12 PM PDT 24
Peak memory 232280 kb
Host smart-1cef7066-1b12-4575-bab3-73f09e66cc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590605908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.590605908
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4178244650
Short name T811
Test name
Test status
Simulation time 249883363 ps
CPU time 7.5 seconds
Started Jun 07 08:11:09 PM PDT 24
Finished Jun 07 08:11:19 PM PDT 24
Peak memory 232488 kb
Host smart-5c16114d-fd38-497d-82db-d96c90ef2c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178244650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4178244650
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2597535347
Short name T480
Test name
Test status
Simulation time 5592213270 ps
CPU time 15.92 seconds
Started Jun 07 08:11:06 PM PDT 24
Finished Jun 07 08:11:24 PM PDT 24
Peak memory 224388 kb
Host smart-293f4942-d39a-40cc-be87-749d88dfbdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597535347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2597535347
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1941583410
Short name T657
Test name
Test status
Simulation time 2783616597 ps
CPU time 6 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:11:15 PM PDT 24
Peak memory 229040 kb
Host smart-5daee202-6f40-49ca-a985-cee9c16b705f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941583410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1941583410
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3160224758
Short name T359
Test name
Test status
Simulation time 80139072 ps
CPU time 3.77 seconds
Started Jun 07 08:11:08 PM PDT 24
Finished Jun 07 08:11:15 PM PDT 24
Peak memory 221732 kb
Host smart-36064eea-a91d-4755-bc25-65c8f8d3fe3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3160224758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3160224758
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3557649689
Short name T62
Test name
Test status
Simulation time 783180435 ps
CPU time 5.46 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:11:15 PM PDT 24
Peak memory 216068 kb
Host smart-71a97e50-906a-465d-8440-6190b4951d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557649689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3557649689
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2029031643
Short name T518
Test name
Test status
Simulation time 31000823189 ps
CPU time 20.75 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:11:30 PM PDT 24
Peak memory 216192 kb
Host smart-e398dbcc-3a79-4450-9d1c-2ecf340ce0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029031643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2029031643
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2046557080
Short name T843
Test name
Test status
Simulation time 17673492 ps
CPU time 0.84 seconds
Started Jun 07 08:11:08 PM PDT 24
Finished Jun 07 08:11:11 PM PDT 24
Peak memory 206460 kb
Host smart-b1e3bf21-34fd-492d-b9c7-a375c3748e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046557080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2046557080
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.245867658
Short name T398
Test name
Test status
Simulation time 111618108 ps
CPU time 0.84 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:11:11 PM PDT 24
Peak memory 205608 kb
Host smart-d4a2f0fd-782b-4c43-a18b-f33f76752659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245867658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.245867658
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3542248712
Short name T911
Test name
Test status
Simulation time 7560862856 ps
CPU time 5.81 seconds
Started Jun 07 08:11:08 PM PDT 24
Finished Jun 07 08:11:16 PM PDT 24
Peak memory 232608 kb
Host smart-c7eb2f25-4e7c-40fb-845a-b42a9a39fab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542248712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3542248712
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3591817112
Short name T326
Test name
Test status
Simulation time 16900686 ps
CPU time 0.67 seconds
Started Jun 07 08:11:13 PM PDT 24
Finished Jun 07 08:11:17 PM PDT 24
Peak memory 205192 kb
Host smart-33e76243-f450-48a8-a118-e1ec8ac9b452
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591817112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3591817112
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3135114603
Short name T703
Test name
Test status
Simulation time 368030688 ps
CPU time 2.41 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:11:11 PM PDT 24
Peak memory 224360 kb
Host smart-c22f913f-adb7-4d87-a099-2d8a92c59c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135114603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3135114603
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.10235201
Short name T931
Test name
Test status
Simulation time 158239602 ps
CPU time 0.8 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:11:10 PM PDT 24
Peak memory 206176 kb
Host smart-279303e7-9808-4ad9-8fc5-def762f303fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10235201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.10235201
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2010835794
Short name T960
Test name
Test status
Simulation time 74285313158 ps
CPU time 71.44 seconds
Started Jun 07 08:11:15 PM PDT 24
Finished Jun 07 08:12:30 PM PDT 24
Peak memory 248996 kb
Host smart-7a932ce6-24ad-41ea-8414-4f6341b7a618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010835794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2010835794
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.309998713
Short name T167
Test name
Test status
Simulation time 46589050744 ps
CPU time 440.66 seconds
Started Jun 07 08:11:17 PM PDT 24
Finished Jun 07 08:18:40 PM PDT 24
Peak memory 250188 kb
Host smart-aac74602-dc76-4f8e-9c8f-d64ee46091f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309998713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.309998713
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.523110038
Short name T727
Test name
Test status
Simulation time 59911419746 ps
CPU time 143.4 seconds
Started Jun 07 08:11:17 PM PDT 24
Finished Jun 07 08:13:43 PM PDT 24
Peak memory 239644 kb
Host smart-b3951e62-94f4-4b62-9013-23047fc20853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523110038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.523110038
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.4269728342
Short name T532
Test name
Test status
Simulation time 3408452390 ps
CPU time 39.19 seconds
Started Jun 07 08:11:13 PM PDT 24
Finished Jun 07 08:11:56 PM PDT 24
Peak memory 232596 kb
Host smart-ea5e4f57-30cb-451b-a04a-d145fac769f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269728342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.4269728342
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4230696070
Short name T605
Test name
Test status
Simulation time 63581339 ps
CPU time 2.27 seconds
Started Jun 07 08:11:08 PM PDT 24
Finished Jun 07 08:11:13 PM PDT 24
Peak memory 224252 kb
Host smart-c9a7dd6d-db2c-4e78-9ecc-ec57cbb487c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230696070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4230696070
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2151687043
Short name T399
Test name
Test status
Simulation time 7951830366 ps
CPU time 35.65 seconds
Started Jun 07 08:11:10 PM PDT 24
Finished Jun 07 08:11:48 PM PDT 24
Peak memory 232552 kb
Host smart-a31e037d-8e9a-4b2d-84ab-e2a3401ab583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151687043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2151687043
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1402159759
Short name T225
Test name
Test status
Simulation time 2498362471 ps
CPU time 5.3 seconds
Started Jun 07 08:11:06 PM PDT 24
Finished Jun 07 08:11:13 PM PDT 24
Peak memory 224396 kb
Host smart-83920f13-31bd-4c92-b5ca-dfdaff5c31eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402159759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1402159759
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4184977630
Short name T271
Test name
Test status
Simulation time 36614594254 ps
CPU time 50.33 seconds
Started Jun 07 08:11:05 PM PDT 24
Finished Jun 07 08:11:57 PM PDT 24
Peak memory 240572 kb
Host smart-315e0005-ee6e-4288-b6b8-c803e2c2532a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184977630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4184977630
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.187972717
Short name T323
Test name
Test status
Simulation time 4016534493 ps
CPU time 10.65 seconds
Started Jun 07 08:11:13 PM PDT 24
Finished Jun 07 08:11:27 PM PDT 24
Peak memory 218788 kb
Host smart-15cf23a6-477c-4ebd-b32c-67496e122c9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=187972717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.187972717
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3176880995
Short name T142
Test name
Test status
Simulation time 7784225089 ps
CPU time 90.69 seconds
Started Jun 07 08:11:16 PM PDT 24
Finished Jun 07 08:12:50 PM PDT 24
Peak memory 251536 kb
Host smart-4e0b5873-3d90-438d-a9ee-ef6cfaaea6d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176880995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3176880995
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1185698622
Short name T594
Test name
Test status
Simulation time 6947821798 ps
CPU time 24.59 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:11:35 PM PDT 24
Peak memory 216172 kb
Host smart-6f1c057f-ceb5-4f76-83e3-b1e30c4c7dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185698622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1185698622
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1596693747
Short name T830
Test name
Test status
Simulation time 6441240736 ps
CPU time 19.45 seconds
Started Jun 07 08:11:05 PM PDT 24
Finished Jun 07 08:11:27 PM PDT 24
Peak memory 216152 kb
Host smart-906f0fd2-d736-4e45-a1d7-fe9db7585950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596693747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1596693747
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.10681802
Short name T291
Test name
Test status
Simulation time 76994356 ps
CPU time 1.38 seconds
Started Jun 07 08:11:09 PM PDT 24
Finished Jun 07 08:11:13 PM PDT 24
Peak memory 216016 kb
Host smart-b9742ca3-e5c0-4113-b45b-d7ba10dda080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10681802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.10681802
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2542638367
Short name T512
Test name
Test status
Simulation time 33570947 ps
CPU time 0.77 seconds
Started Jun 07 08:11:06 PM PDT 24
Finished Jun 07 08:11:09 PM PDT 24
Peak memory 205664 kb
Host smart-13811ed1-f0db-41a0-86f5-44684a47318d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542638367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2542638367
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1533717628
Short name T272
Test name
Test status
Simulation time 856810398 ps
CPU time 12.09 seconds
Started Jun 07 08:11:07 PM PDT 24
Finished Jun 07 08:11:21 PM PDT 24
Peak memory 232528 kb
Host smart-f55b2e4b-62d1-4c93-b8c7-dade127ec2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533717628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1533717628
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.354446187
Short name T866
Test name
Test status
Simulation time 42972948 ps
CPU time 0.72 seconds
Started Jun 07 08:11:15 PM PDT 24
Finished Jun 07 08:11:19 PM PDT 24
Peak memory 204556 kb
Host smart-d2e83499-6458-4017-a7b9-ac04907dcf80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354446187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.354446187
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.707328304
Short name T540
Test name
Test status
Simulation time 4437936411 ps
CPU time 13.7 seconds
Started Jun 07 08:11:14 PM PDT 24
Finished Jun 07 08:11:32 PM PDT 24
Peak memory 224344 kb
Host smart-d74d9a78-23e7-47c3-90be-aa239a6d1b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707328304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.707328304
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3565891065
Short name T365
Test name
Test status
Simulation time 40925743 ps
CPU time 0.8 seconds
Started Jun 07 08:11:15 PM PDT 24
Finished Jun 07 08:11:19 PM PDT 24
Peak memory 206232 kb
Host smart-2b14ad55-1d72-44cd-99f7-deef00e0b86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565891065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3565891065
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1653966079
Short name T835
Test name
Test status
Simulation time 6365164108 ps
CPU time 81.49 seconds
Started Jun 07 08:11:12 PM PDT 24
Finished Jun 07 08:12:36 PM PDT 24
Peak memory 237600 kb
Host smart-1cabebaf-526f-40d8-a1dd-221e92856828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653966079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1653966079
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.331270847
Short name T166
Test name
Test status
Simulation time 29247755068 ps
CPU time 41.01 seconds
Started Jun 07 08:11:13 PM PDT 24
Finished Jun 07 08:11:57 PM PDT 24
Peak memory 239280 kb
Host smart-1e7d4861-bd07-4a3d-a19f-fd7002fff941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331270847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.331270847
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.4142033186
Short name T717
Test name
Test status
Simulation time 1081943087 ps
CPU time 12.19 seconds
Started Jun 07 08:11:14 PM PDT 24
Finished Jun 07 08:11:29 PM PDT 24
Peak memory 248928 kb
Host smart-fc171106-83f4-4a2a-87db-3c4af2a97175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142033186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.4142033186
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1458416233
Short name T438
Test name
Test status
Simulation time 39782545 ps
CPU time 2.07 seconds
Started Jun 07 08:11:10 PM PDT 24
Finished Jun 07 08:11:14 PM PDT 24
Peak memory 224288 kb
Host smart-f717e3d0-975e-4ed3-a986-617394a09b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458416233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1458416233
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.216165910
Short name T52
Test name
Test status
Simulation time 840277630 ps
CPU time 11.07 seconds
Started Jun 07 08:11:20 PM PDT 24
Finished Jun 07 08:11:33 PM PDT 24
Peak memory 224288 kb
Host smart-d5a5a999-b4d3-472b-b5f8-5f6a1b67194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216165910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.216165910
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4122680524
Short name T803
Test name
Test status
Simulation time 46436757543 ps
CPU time 11.26 seconds
Started Jun 07 08:11:16 PM PDT 24
Finished Jun 07 08:11:30 PM PDT 24
Peak memory 224368 kb
Host smart-3129430b-0e74-44e4-aada-b6b359a4cb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122680524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.4122680524
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1067062044
Short name T603
Test name
Test status
Simulation time 2483239118 ps
CPU time 9.24 seconds
Started Jun 07 08:11:13 PM PDT 24
Finished Jun 07 08:11:26 PM PDT 24
Peak memory 232616 kb
Host smart-b3365a64-9256-4afc-9e7d-111c157b6699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067062044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1067062044
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1912319727
Short name T331
Test name
Test status
Simulation time 77721781 ps
CPU time 3.61 seconds
Started Jun 07 08:11:16 PM PDT 24
Finished Jun 07 08:11:23 PM PDT 24
Peak memory 220444 kb
Host smart-49f9f739-79d2-4039-8a6e-5ef4f518ca51
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1912319727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1912319727
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.992696565
Short name T60
Test name
Test status
Simulation time 27914027389 ps
CPU time 272.07 seconds
Started Jun 07 08:11:13 PM PDT 24
Finished Jun 07 08:15:48 PM PDT 24
Peak memory 252828 kb
Host smart-fae9292d-8d07-44cf-9719-60ababa19bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992696565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.992696565
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1580001355
Short name T486
Test name
Test status
Simulation time 18244316496 ps
CPU time 18.55 seconds
Started Jun 07 08:11:13 PM PDT 24
Finished Jun 07 08:11:34 PM PDT 24
Peak memory 216340 kb
Host smart-777f51d6-45bc-4867-9275-59a2c9a4adcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580001355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1580001355
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.360233898
Short name T404
Test name
Test status
Simulation time 3531715161 ps
CPU time 7.77 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:33 PM PDT 24
Peak memory 216112 kb
Host smart-8b980aee-c1e0-4a4d-be0a-6ef3480ea5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360233898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.360233898
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1460281142
Short name T599
Test name
Test status
Simulation time 687130091 ps
CPU time 5.01 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:30 PM PDT 24
Peak memory 208444 kb
Host smart-ef9c4d2c-71bf-4d7b-ac5c-602d00a89c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460281142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1460281142
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3016326611
Short name T897
Test name
Test status
Simulation time 31546558 ps
CPU time 0.73 seconds
Started Jun 07 08:11:13 PM PDT 24
Finished Jun 07 08:11:16 PM PDT 24
Peak memory 205584 kb
Host smart-c4a5dcd6-41fc-49ef-85b3-5f92c6eab04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016326611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3016326611
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3954254395
Short name T470
Test name
Test status
Simulation time 716919827 ps
CPU time 6.12 seconds
Started Jun 07 08:11:15 PM PDT 24
Finished Jun 07 08:11:24 PM PDT 24
Peak memory 232540 kb
Host smart-c871d5d7-e785-4db6-b3a2-5d347ede4d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954254395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3954254395
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1600131515
Short name T752
Test name
Test status
Simulation time 25175423 ps
CPU time 0.75 seconds
Started Jun 07 08:11:22 PM PDT 24
Finished Jun 07 08:11:26 PM PDT 24
Peak memory 204524 kb
Host smart-bdb651cf-d899-40d8-aa0b-15938b8b4e59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600131515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1600131515
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1364829475
Short name T893
Test name
Test status
Simulation time 1003990007 ps
CPU time 5.66 seconds
Started Jun 07 08:11:15 PM PDT 24
Finished Jun 07 08:11:23 PM PDT 24
Peak memory 232532 kb
Host smart-794ffdc5-ee1c-41f6-bca0-0307a072dafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364829475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1364829475
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3312312678
Short name T920
Test name
Test status
Simulation time 21476366 ps
CPU time 0.79 seconds
Started Jun 07 08:11:14 PM PDT 24
Finished Jun 07 08:11:18 PM PDT 24
Peak memory 206320 kb
Host smart-79686bdd-460d-40c3-99c0-9bd853873997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312312678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3312312678
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1844218506
Short name T50
Test name
Test status
Simulation time 11600953351 ps
CPU time 37.09 seconds
Started Jun 07 08:11:20 PM PDT 24
Finished Jun 07 08:11:59 PM PDT 24
Peak memory 248984 kb
Host smart-f2ecd75c-4c40-47f4-bc4a-9f5d7ce7bc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844218506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1844218506
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2327040899
Short name T786
Test name
Test status
Simulation time 6833671340 ps
CPU time 106.47 seconds
Started Jun 07 08:11:14 PM PDT 24
Finished Jun 07 08:13:04 PM PDT 24
Peak memory 249064 kb
Host smart-3617e7bb-b055-4550-abda-79ae419c0ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327040899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2327040899
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3574981275
Short name T645
Test name
Test status
Simulation time 33130838383 ps
CPU time 72.51 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:12:38 PM PDT 24
Peak memory 250332 kb
Host smart-a536df89-b149-49f2-9a9d-8289ee9fb2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574981275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3574981275
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2063373517
Short name T12
Test name
Test status
Simulation time 13653161231 ps
CPU time 18.6 seconds
Started Jun 07 08:11:20 PM PDT 24
Finished Jun 07 08:11:41 PM PDT 24
Peak memory 224376 kb
Host smart-58a0b27e-c8ca-4046-a8b2-f551b56accde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063373517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2063373517
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1692865646
Short name T329
Test name
Test status
Simulation time 1265817259 ps
CPU time 2.3 seconds
Started Jun 07 08:11:13 PM PDT 24
Finished Jun 07 08:11:19 PM PDT 24
Peak memory 222852 kb
Host smart-a54b12b1-abe8-4c4b-9c29-ced25c1acb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692865646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1692865646
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2131331049
Short name T177
Test name
Test status
Simulation time 15614522955 ps
CPU time 34.45 seconds
Started Jun 07 08:11:14 PM PDT 24
Finished Jun 07 08:11:52 PM PDT 24
Peak memory 224352 kb
Host smart-8005df7f-3809-4d0a-813c-16a02b41e0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131331049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2131331049
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2775248515
Short name T435
Test name
Test status
Simulation time 425265402 ps
CPU time 2.43 seconds
Started Jun 07 08:11:13 PM PDT 24
Finished Jun 07 08:11:18 PM PDT 24
Peak memory 224288 kb
Host smart-45a9268d-8dec-4109-88da-0f03017fa839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775248515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2775248515
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.492955913
Short name T476
Test name
Test status
Simulation time 9298495295 ps
CPU time 8.49 seconds
Started Jun 07 08:11:20 PM PDT 24
Finished Jun 07 08:11:31 PM PDT 24
Peak memory 232584 kb
Host smart-7875b7f8-68b8-4ed2-8862-7f69d49bb6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492955913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.492955913
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1942453355
Short name T7
Test name
Test status
Simulation time 1072048497 ps
CPU time 6.43 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:32 PM PDT 24
Peak memory 220176 kb
Host smart-121ded2c-066b-41df-88c8-376b0672733e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1942453355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1942453355
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3430152796
Short name T829
Test name
Test status
Simulation time 965115097 ps
CPU time 9.67 seconds
Started Jun 07 08:11:16 PM PDT 24
Finished Jun 07 08:11:28 PM PDT 24
Peak memory 219696 kb
Host smart-c3256835-d8a1-4a81-85d8-963639084060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430152796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3430152796
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3470525666
Short name T646
Test name
Test status
Simulation time 8758805430 ps
CPU time 9.01 seconds
Started Jun 07 08:11:14 PM PDT 24
Finished Jun 07 08:11:27 PM PDT 24
Peak memory 216120 kb
Host smart-bb52e2cd-c006-41c5-a171-ce714f74a153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470525666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3470525666
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2159167580
Short name T690
Test name
Test status
Simulation time 540995744 ps
CPU time 2.13 seconds
Started Jun 07 08:11:14 PM PDT 24
Finished Jun 07 08:11:19 PM PDT 24
Peak memory 216124 kb
Host smart-fc0c92a9-d846-4229-8691-912db4d63460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159167580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2159167580
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.623537014
Short name T781
Test name
Test status
Simulation time 107652968 ps
CPU time 0.85 seconds
Started Jun 07 08:11:19 PM PDT 24
Finished Jun 07 08:11:22 PM PDT 24
Peak memory 205584 kb
Host smart-bd629117-720c-486a-9d59-6551914f83dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623537014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.623537014
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.776972505
Short name T760
Test name
Test status
Simulation time 341928714 ps
CPU time 3.54 seconds
Started Jun 07 08:11:14 PM PDT 24
Finished Jun 07 08:11:21 PM PDT 24
Peak memory 224296 kb
Host smart-d4aa7876-d53f-4917-89b7-70a6bd26c1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776972505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.776972505
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3822123125
Short name T693
Test name
Test status
Simulation time 54259759 ps
CPU time 0.79 seconds
Started Jun 07 08:11:24 PM PDT 24
Finished Jun 07 08:11:28 PM PDT 24
Peak memory 204528 kb
Host smart-1eeb59b8-f6ed-4071-af67-2fed28126d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822123125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3822123125
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3578732134
Short name T757
Test name
Test status
Simulation time 133945994 ps
CPU time 3.82 seconds
Started Jun 07 08:11:21 PM PDT 24
Finished Jun 07 08:11:28 PM PDT 24
Peak memory 232544 kb
Host smart-8c479746-c7cd-481f-8e2b-a71bbc3fd015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578732134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3578732134
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3362925748
Short name T568
Test name
Test status
Simulation time 62640096 ps
CPU time 0.74 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:27 PM PDT 24
Peak memory 205544 kb
Host smart-98602fca-b0de-4fcd-b204-856921f2b1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362925748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3362925748
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3009348718
Short name T157
Test name
Test status
Simulation time 38062203264 ps
CPU time 93.09 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:12:58 PM PDT 24
Peak memory 254248 kb
Host smart-79065e47-c211-4c5a-8b00-0cbaffd4e98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009348718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3009348718
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1471149468
Short name T198
Test name
Test status
Simulation time 41597989735 ps
CPU time 163.14 seconds
Started Jun 07 08:11:21 PM PDT 24
Finished Jun 07 08:14:07 PM PDT 24
Peak memory 256668 kb
Host smart-37bbb8c2-751c-46b1-b5e6-8c83da98ad40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471149468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1471149468
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1253388143
Short name T422
Test name
Test status
Simulation time 3285395682 ps
CPU time 41.22 seconds
Started Jun 07 08:11:32 PM PDT 24
Finished Jun 07 08:12:15 PM PDT 24
Peak memory 239888 kb
Host smart-e0b226b0-a12b-409f-a7ec-7431db4f1a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253388143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1253388143
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2379787640
Short name T247
Test name
Test status
Simulation time 315255903 ps
CPU time 4.44 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:30 PM PDT 24
Peak memory 224292 kb
Host smart-d022acea-7c9a-41e1-baa4-28edc6b2147d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379787640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2379787640
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3263562579
Short name T343
Test name
Test status
Simulation time 23500802408 ps
CPU time 22.19 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:48 PM PDT 24
Peak memory 240608 kb
Host smart-25d3ccb3-31e5-401e-9ad2-78f4fc06e047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263562579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3263562579
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.795494369
Short name T734
Test name
Test status
Simulation time 807799585 ps
CPU time 4.72 seconds
Started Jun 07 08:11:22 PM PDT 24
Finished Jun 07 08:11:30 PM PDT 24
Peak memory 229008 kb
Host smart-33bd8f83-6bbd-4253-a37c-89cf380ebb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795494369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.795494369
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2102279533
Short name T174
Test name
Test status
Simulation time 2429045753 ps
CPU time 12.36 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:38 PM PDT 24
Peak memory 232620 kb
Host smart-93764ef7-a755-4fed-bc3f-d6a79912b3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102279533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2102279533
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2685823696
Short name T10
Test name
Test status
Simulation time 1672592527 ps
CPU time 6.93 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:33 PM PDT 24
Peak memory 222744 kb
Host smart-08d248d4-f43f-414c-b169-78414c786290
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2685823696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2685823696
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.241521126
Short name T475
Test name
Test status
Simulation time 81643146 ps
CPU time 0.91 seconds
Started Jun 07 08:11:20 PM PDT 24
Finished Jun 07 08:11:22 PM PDT 24
Peak memory 206264 kb
Host smart-910c33f0-6642-4ff6-bc68-1ebad77d9b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241521126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.241521126
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2538525206
Short name T670
Test name
Test status
Simulation time 29719292466 ps
CPU time 33.98 seconds
Started Jun 07 08:11:22 PM PDT 24
Finished Jun 07 08:11:59 PM PDT 24
Peak memory 216180 kb
Host smart-84c19b91-db71-4d1a-b02d-6a38174862ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538525206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2538525206
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3911620304
Short name T744
Test name
Test status
Simulation time 3095805842 ps
CPU time 4.65 seconds
Started Jun 07 08:11:21 PM PDT 24
Finished Jun 07 08:11:29 PM PDT 24
Peak memory 216120 kb
Host smart-e9ee1a1a-9930-4002-ba70-26108249bf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911620304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3911620304
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.622049509
Short name T293
Test name
Test status
Simulation time 17115184 ps
CPU time 0.98 seconds
Started Jun 07 08:11:25 PM PDT 24
Finished Jun 07 08:11:28 PM PDT 24
Peak memory 206812 kb
Host smart-618aa28c-1a0d-4d4f-989f-197d2dcaa864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622049509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.622049509
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1121644875
Short name T536
Test name
Test status
Simulation time 49652755 ps
CPU time 0.8 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:26 PM PDT 24
Peak memory 205620 kb
Host smart-5e2b21f7-437c-4106-b2ef-ecff1cc9ac46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121644875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1121644875
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.4168164488
Short name T250
Test name
Test status
Simulation time 18361103761 ps
CPU time 47.78 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:12:14 PM PDT 24
Peak memory 234204 kb
Host smart-9677f1e4-0ab4-4876-b627-583b4a3fd951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168164488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4168164488
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2179839034
Short name T787
Test name
Test status
Simulation time 12944741 ps
CPU time 0.77 seconds
Started Jun 07 08:11:22 PM PDT 24
Finished Jun 07 08:11:25 PM PDT 24
Peak memory 205560 kb
Host smart-335aa7e9-bece-4374-ac29-86524c965d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179839034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2179839034
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3256563534
Short name T580
Test name
Test status
Simulation time 110068478 ps
CPU time 2.64 seconds
Started Jun 07 08:11:21 PM PDT 24
Finished Jun 07 08:11:27 PM PDT 24
Peak memory 224284 kb
Host smart-bfb94d38-a247-4c37-b48e-5e8ac2b8b49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256563534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3256563534
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1468107028
Short name T490
Test name
Test status
Simulation time 37859285 ps
CPU time 0.86 seconds
Started Jun 07 08:11:21 PM PDT 24
Finished Jun 07 08:11:24 PM PDT 24
Peak memory 206232 kb
Host smart-00938c33-01c0-4122-b907-69d1ca51d7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468107028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1468107028
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.76410677
Short name T164
Test name
Test status
Simulation time 13795725059 ps
CPU time 101.18 seconds
Started Jun 07 08:11:24 PM PDT 24
Finished Jun 07 08:13:08 PM PDT 24
Peak memory 252052 kb
Host smart-5d7bd08a-6ba3-4ec8-830d-5738371fdb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76410677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.76410677
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2149473227
Short name T844
Test name
Test status
Simulation time 4877415739 ps
CPU time 68.72 seconds
Started Jun 07 08:11:21 PM PDT 24
Finished Jun 07 08:12:32 PM PDT 24
Peak memory 224436 kb
Host smart-1c7f868b-acc8-46b7-9401-abc808cc6c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149473227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2149473227
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.481756401
Short name T159
Test name
Test status
Simulation time 98300260 ps
CPU time 3.29 seconds
Started Jun 07 08:11:20 PM PDT 24
Finished Jun 07 08:11:25 PM PDT 24
Peak memory 224348 kb
Host smart-fb4a2d03-5f95-488c-ad8a-5446f0d9cc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481756401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.481756401
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1239758200
Short name T59
Test name
Test status
Simulation time 6750060692 ps
CPU time 33.7 seconds
Started Jun 07 08:11:21 PM PDT 24
Finished Jun 07 08:11:57 PM PDT 24
Peak memory 233584 kb
Host smart-240147fe-3b18-4418-98e1-abed085b92bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239758200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1239758200
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3020247226
Short name T722
Test name
Test status
Simulation time 2285382633 ps
CPU time 6.73 seconds
Started Jun 07 08:11:20 PM PDT 24
Finished Jun 07 08:11:30 PM PDT 24
Peak memory 224368 kb
Host smart-3b9700a7-3299-409d-bfa2-bb6550286b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020247226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3020247226
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.175767711
Short name T489
Test name
Test status
Simulation time 306107916 ps
CPU time 4.68 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:30 PM PDT 24
Peak memory 232532 kb
Host smart-97faa079-aa6c-4df0-bf89-ec349549d2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175767711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.175767711
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1984042281
Short name T658
Test name
Test status
Simulation time 225307702 ps
CPU time 3.72 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:29 PM PDT 24
Peak memory 222736 kb
Host smart-36867101-4fdb-4655-beab-02134ea3d36d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1984042281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1984042281
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.33758623
Short name T675
Test name
Test status
Simulation time 21991821010 ps
CPU time 214.8 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:15:00 PM PDT 24
Peak memory 249984 kb
Host smart-697f0811-bdf0-4ec5-803d-2b75059b73b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33758623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress
_all.33758623
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3293088334
Short name T576
Test name
Test status
Simulation time 4449636447 ps
CPU time 10.8 seconds
Started Jun 07 08:11:20 PM PDT 24
Finished Jun 07 08:11:32 PM PDT 24
Peak memory 216116 kb
Host smart-87c5a595-54b3-4997-93d9-ca11f24ff359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293088334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3293088334
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.748289688
Short name T797
Test name
Test status
Simulation time 8149098900 ps
CPU time 7.88 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:33 PM PDT 24
Peak memory 216116 kb
Host smart-a548a78a-8473-4727-a248-6561415764cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748289688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.748289688
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3319063537
Short name T573
Test name
Test status
Simulation time 60336134 ps
CPU time 0.81 seconds
Started Jun 07 08:11:24 PM PDT 24
Finished Jun 07 08:11:27 PM PDT 24
Peak memory 205636 kb
Host smart-98620baa-921f-4226-a2da-f011e673de27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319063537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3319063537
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.609010562
Short name T620
Test name
Test status
Simulation time 50768879 ps
CPU time 0.75 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:27 PM PDT 24
Peak memory 205616 kb
Host smart-9a9ee7b0-76fd-4117-b1ff-c783b44a0f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609010562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.609010562
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.616636862
Short name T191
Test name
Test status
Simulation time 583710038 ps
CPU time 3.98 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:30 PM PDT 24
Peak memory 224316 kb
Host smart-d6b1e9d9-6fbc-4465-ae62-a0f2fb3d8017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616636862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.616636862
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.630372120
Short name T900
Test name
Test status
Simulation time 28129405 ps
CPU time 0.73 seconds
Started Jun 07 08:11:27 PM PDT 24
Finished Jun 07 08:11:30 PM PDT 24
Peak memory 205156 kb
Host smart-53de051a-b916-4a6c-a53f-4c9f29c63722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630372120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.630372120
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1808439115
Short name T821
Test name
Test status
Simulation time 890587495 ps
CPU time 5.61 seconds
Started Jun 07 08:11:31 PM PDT 24
Finished Jun 07 08:11:37 PM PDT 24
Peak memory 224308 kb
Host smart-3234a043-f945-475a-b49d-e683260953a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808439115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1808439115
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3398688786
Short name T888
Test name
Test status
Simulation time 20406741 ps
CPU time 0.77 seconds
Started Jun 07 08:11:24 PM PDT 24
Finished Jun 07 08:11:27 PM PDT 24
Peak memory 206248 kb
Host smart-93a6c180-629b-467d-8250-7407b46d1f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398688786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3398688786
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1481799216
Short name T213
Test name
Test status
Simulation time 95268484956 ps
CPU time 217.5 seconds
Started Jun 07 08:11:30 PM PDT 24
Finished Jun 07 08:15:09 PM PDT 24
Peak memory 253884 kb
Host smart-6f0f10b1-7a65-479b-bf6e-6e3b31708a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481799216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1481799216
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3702768546
Short name T606
Test name
Test status
Simulation time 14362885718 ps
CPU time 70.15 seconds
Started Jun 07 08:11:26 PM PDT 24
Finished Jun 07 08:12:38 PM PDT 24
Peak memory 237980 kb
Host smart-05830e6b-f061-4e1c-b232-6857eb5a3952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702768546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3702768546
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.212373305
Short name T753
Test name
Test status
Simulation time 60696711035 ps
CPU time 317.84 seconds
Started Jun 07 08:11:32 PM PDT 24
Finished Jun 07 08:16:51 PM PDT 24
Peak memory 264940 kb
Host smart-0159136b-6508-467c-ac96-2f8da9571dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212373305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.212373305
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2639559611
Short name T344
Test name
Test status
Simulation time 268732914 ps
CPU time 9.99 seconds
Started Jun 07 08:11:27 PM PDT 24
Finished Jun 07 08:11:39 PM PDT 24
Peak memory 238676 kb
Host smart-55a750f8-3a6c-40ad-919c-c5c3c6d3cc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639559611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2639559611
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.350583118
Short name T881
Test name
Test status
Simulation time 38323177286 ps
CPU time 30.52 seconds
Started Jun 07 08:11:28 PM PDT 24
Finished Jun 07 08:12:00 PM PDT 24
Peak memory 224392 kb
Host smart-c4a26516-1669-4c47-a21a-3048633cc9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350583118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.350583118
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2290456933
Short name T441
Test name
Test status
Simulation time 3118143073 ps
CPU time 11.27 seconds
Started Jun 07 08:11:38 PM PDT 24
Finished Jun 07 08:11:51 PM PDT 24
Peak memory 232516 kb
Host smart-024c086a-cad8-46ce-bfb5-f8cfc87a7144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290456933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2290456933
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.247872707
Short name T200
Test name
Test status
Simulation time 13755721961 ps
CPU time 17.34 seconds
Started Jun 07 08:11:24 PM PDT 24
Finished Jun 07 08:11:44 PM PDT 24
Peak memory 232604 kb
Host smart-2ec6dcad-6a7e-4dc4-887a-a21cdf15d3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247872707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.247872707
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1666267047
Short name T380
Test name
Test status
Simulation time 3982075325 ps
CPU time 8.85 seconds
Started Jun 07 08:11:22 PM PDT 24
Finished Jun 07 08:11:34 PM PDT 24
Peak memory 224328 kb
Host smart-007d3d9d-8310-4bed-9f08-41a7adea0ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666267047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1666267047
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.934102954
Short name T427
Test name
Test status
Simulation time 1949431016 ps
CPU time 5.89 seconds
Started Jun 07 08:11:26 PM PDT 24
Finished Jun 07 08:11:34 PM PDT 24
Peak memory 222744 kb
Host smart-f59ed63d-8968-40fd-b4c0-7a7343219d2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=934102954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.934102954
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3119083963
Short name T15
Test name
Test status
Simulation time 6100812392 ps
CPU time 16.55 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:42 PM PDT 24
Peak memory 216128 kb
Host smart-766747dd-2ed3-4d8d-b2b7-a2eeed4d5d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119083963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3119083963
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.758096737
Short name T731
Test name
Test status
Simulation time 3277409795 ps
CPU time 8.59 seconds
Started Jun 07 08:11:24 PM PDT 24
Finished Jun 07 08:11:35 PM PDT 24
Peak memory 216104 kb
Host smart-f68e3261-68ce-4227-9660-e0543b871a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758096737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.758096737
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.578513990
Short name T815
Test name
Test status
Simulation time 43783875 ps
CPU time 1.52 seconds
Started Jun 07 08:11:20 PM PDT 24
Finished Jun 07 08:11:24 PM PDT 24
Peak memory 216032 kb
Host smart-b3b1fd66-1f08-4183-b601-c551626d7e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578513990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.578513990
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.321286983
Short name T505
Test name
Test status
Simulation time 46610140 ps
CPU time 0.67 seconds
Started Jun 07 08:11:23 PM PDT 24
Finished Jun 07 08:11:27 PM PDT 24
Peak memory 205260 kb
Host smart-671879de-738e-447b-ac8b-6a0765926fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321286983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.321286983
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2409285524
Short name T302
Test name
Test status
Simulation time 146806073 ps
CPU time 2.51 seconds
Started Jun 07 08:11:31 PM PDT 24
Finished Jun 07 08:11:35 PM PDT 24
Peak memory 224072 kb
Host smart-19f4265b-a615-4216-8556-019937cd6126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409285524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2409285524
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1810727279
Short name T34
Test name
Test status
Simulation time 11331518 ps
CPU time 0.68 seconds
Started Jun 07 08:11:31 PM PDT 24
Finished Jun 07 08:11:33 PM PDT 24
Peak memory 204528 kb
Host smart-bbaa77f0-bebc-483f-b606-ee5ef0f97ff5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810727279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1810727279
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3819500728
Short name T836
Test name
Test status
Simulation time 136956900 ps
CPU time 3 seconds
Started Jun 07 08:11:29 PM PDT 24
Finished Jun 07 08:11:33 PM PDT 24
Peak memory 224316 kb
Host smart-36e4e0c5-8ee7-4fe8-a023-2fa7f8964922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819500728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3819500728
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.108725956
Short name T444
Test name
Test status
Simulation time 27425671 ps
CPU time 0.76 seconds
Started Jun 07 08:11:26 PM PDT 24
Finished Jun 07 08:11:29 PM PDT 24
Peak memory 205192 kb
Host smart-2df0a49f-8c48-42a8-8130-5fbc32483482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108725956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.108725956
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2193204182
Short name T617
Test name
Test status
Simulation time 15869235536 ps
CPU time 62.44 seconds
Started Jun 07 08:11:26 PM PDT 24
Finished Jun 07 08:12:31 PM PDT 24
Peak memory 249988 kb
Host smart-53d88aab-2f2d-4b8b-bdb2-7a8d719e7a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193204182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2193204182
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3112095707
Short name T264
Test name
Test status
Simulation time 10746192632 ps
CPU time 68.5 seconds
Started Jun 07 08:11:30 PM PDT 24
Finished Jun 07 08:12:39 PM PDT 24
Peak memory 256620 kb
Host smart-f973dc45-5889-4135-938a-ada76b60adc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112095707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3112095707
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2186610361
Short name T954
Test name
Test status
Simulation time 1158970421 ps
CPU time 6.88 seconds
Started Jun 07 08:11:27 PM PDT 24
Finished Jun 07 08:11:36 PM PDT 24
Peak memory 224356 kb
Host smart-a3224aa4-d5d3-443c-b1c2-45b3095785a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186610361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2186610361
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4132572207
Short name T713
Test name
Test status
Simulation time 151814369 ps
CPU time 4.49 seconds
Started Jun 07 08:11:27 PM PDT 24
Finished Jun 07 08:11:34 PM PDT 24
Peak memory 232540 kb
Host smart-afac5a96-a9ba-4309-97fd-9f3b02979c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132572207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4132572207
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.119612651
Short name T926
Test name
Test status
Simulation time 425254023 ps
CPU time 5.58 seconds
Started Jun 07 08:11:27 PM PDT 24
Finished Jun 07 08:11:34 PM PDT 24
Peak memory 224316 kb
Host smart-eff31ac7-9e27-4e83-b085-7d3c45f4f0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119612651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.119612651
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1787395651
Short name T688
Test name
Test status
Simulation time 1474967532 ps
CPU time 8.66 seconds
Started Jun 07 08:11:38 PM PDT 24
Finished Jun 07 08:11:49 PM PDT 24
Peak memory 232556 kb
Host smart-1b2ac862-c555-4cab-99a8-b3d971ae2a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787395651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1787395651
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.777614792
Short name T11
Test name
Test status
Simulation time 311480854 ps
CPU time 2.91 seconds
Started Jun 07 08:11:38 PM PDT 24
Finished Jun 07 08:11:43 PM PDT 24
Peak memory 232588 kb
Host smart-e7ca2f19-f88d-4421-8258-451e6aa663b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777614792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.777614792
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.254202536
Short name T316
Test name
Test status
Simulation time 128036565 ps
CPU time 4.34 seconds
Started Jun 07 08:11:27 PM PDT 24
Finished Jun 07 08:11:33 PM PDT 24
Peak memory 221448 kb
Host smart-b8293360-154b-45d5-bf8a-8fdfde432a00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=254202536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.254202536
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.348273239
Short name T793
Test name
Test status
Simulation time 5770191726 ps
CPU time 15.82 seconds
Started Jun 07 08:11:33 PM PDT 24
Finished Jun 07 08:11:50 PM PDT 24
Peak memory 216400 kb
Host smart-8ec834e2-b376-422e-84b7-084c88d0c74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348273239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.348273239
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.892950262
Short name T16
Test name
Test status
Simulation time 799157012 ps
CPU time 2.89 seconds
Started Jun 07 08:11:28 PM PDT 24
Finished Jun 07 08:11:32 PM PDT 24
Peak memory 216000 kb
Host smart-d78c37ee-2075-47ae-94be-282ea76b001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892950262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.892950262
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2113641815
Short name T677
Test name
Test status
Simulation time 695130924 ps
CPU time 2.31 seconds
Started Jun 07 08:11:31 PM PDT 24
Finished Jun 07 08:11:34 PM PDT 24
Peak memory 217260 kb
Host smart-5840c1b0-5f27-4ca0-95b8-8d967535f1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113641815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2113641815
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1279477472
Short name T706
Test name
Test status
Simulation time 16755066 ps
CPU time 0.73 seconds
Started Jun 07 08:11:31 PM PDT 24
Finished Jun 07 08:11:34 PM PDT 24
Peak memory 205600 kb
Host smart-46f72c5d-091e-4be9-99c9-83eb45b4ac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279477472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1279477472
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1125312219
Short name T838
Test name
Test status
Simulation time 850955817 ps
CPU time 2.9 seconds
Started Jun 07 08:11:38 PM PDT 24
Finished Jun 07 08:11:43 PM PDT 24
Peak memory 232480 kb
Host smart-acbdf68a-d018-4ac6-bb3d-54ecb572610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125312219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1125312219
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.490117371
Short name T308
Test name
Test status
Simulation time 13955481 ps
CPU time 0.73 seconds
Started Jun 07 08:11:37 PM PDT 24
Finished Jun 07 08:11:40 PM PDT 24
Peak memory 205080 kb
Host smart-a9458df4-5c9b-4a11-9cc6-534c35489ce4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490117371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.490117371
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3758601198
Short name T416
Test name
Test status
Simulation time 42335522 ps
CPU time 2.33 seconds
Started Jun 07 08:11:31 PM PDT 24
Finished Jun 07 08:11:35 PM PDT 24
Peak memory 224308 kb
Host smart-77d283d8-89df-4074-8834-0a6e4407d49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758601198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3758601198
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3245445008
Short name T523
Test name
Test status
Simulation time 20584698 ps
CPU time 0.9 seconds
Started Jun 07 08:11:24 PM PDT 24
Finished Jun 07 08:11:27 PM PDT 24
Peak memory 206196 kb
Host smart-4d14ee50-86fc-4889-856a-19b2f85a1574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245445008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3245445008
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2083663367
Short name T216
Test name
Test status
Simulation time 42580235276 ps
CPU time 294.72 seconds
Started Jun 07 08:11:37 PM PDT 24
Finished Jun 07 08:16:33 PM PDT 24
Peak memory 251044 kb
Host smart-588f5f5f-2419-485a-9fbd-ca7a5f22937f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083663367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2083663367
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3333476217
Short name T169
Test name
Test status
Simulation time 21192603950 ps
CPU time 126.88 seconds
Started Jun 07 08:11:35 PM PDT 24
Finished Jun 07 08:13:44 PM PDT 24
Peak memory 257248 kb
Host smart-f19cb1b4-fe28-49f8-bc98-675417805520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333476217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3333476217
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1155289143
Short name T208
Test name
Test status
Simulation time 245213317595 ps
CPU time 488.9 seconds
Started Jun 07 08:11:38 PM PDT 24
Finished Jun 07 08:19:49 PM PDT 24
Peak memory 256300 kb
Host smart-10531791-03fd-4d28-8e08-02a948987473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155289143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1155289143
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1865333776
Short name T350
Test name
Test status
Simulation time 1812156270 ps
CPU time 11.4 seconds
Started Jun 07 08:11:27 PM PDT 24
Finished Jun 07 08:11:40 PM PDT 24
Peak memory 224308 kb
Host smart-0773448f-42a7-4d1f-8f37-d673933ea547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865333776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1865333776
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2907862698
Short name T735
Test name
Test status
Simulation time 2429789913 ps
CPU time 20.61 seconds
Started Jun 07 08:11:31 PM PDT 24
Finished Jun 07 08:11:54 PM PDT 24
Peak memory 224376 kb
Host smart-be6835d0-9a71-4677-80d2-7e40c2596918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907862698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2907862698
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3984154053
Short name T188
Test name
Test status
Simulation time 7824592587 ps
CPU time 24.34 seconds
Started Jun 07 08:11:26 PM PDT 24
Finished Jun 07 08:11:52 PM PDT 24
Peak memory 224376 kb
Host smart-5eb2ce06-fb89-4a6e-bc5b-3a516fb776e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984154053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3984154053
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.196031195
Short name T449
Test name
Test status
Simulation time 92397116 ps
CPU time 2.26 seconds
Started Jun 07 08:11:38 PM PDT 24
Finished Jun 07 08:11:43 PM PDT 24
Peak memory 223020 kb
Host smart-7480109f-cf8f-4c91-9057-a974c28a2d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196031195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.196031195
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2740870150
Short name T481
Test name
Test status
Simulation time 16656608683 ps
CPU time 25.9 seconds
Started Jun 07 08:11:31 PM PDT 24
Finished Jun 07 08:11:59 PM PDT 24
Peak memory 232600 kb
Host smart-410570a6-04fa-4797-8748-4885e49670f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740870150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2740870150
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4049415486
Short name T552
Test name
Test status
Simulation time 439735594 ps
CPU time 6.67 seconds
Started Jun 07 08:11:37 PM PDT 24
Finished Jun 07 08:11:46 PM PDT 24
Peak memory 221776 kb
Host smart-31226c43-07ba-4649-9f5f-239a5a1c1237
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4049415486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4049415486
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2099350505
Short name T665
Test name
Test status
Simulation time 9303486360 ps
CPU time 32.36 seconds
Started Jun 07 08:11:36 PM PDT 24
Finished Jun 07 08:12:11 PM PDT 24
Peak memory 249016 kb
Host smart-9555b52b-d0a1-4a7c-b871-f794ad772c35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099350505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2099350505
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2278386254
Short name T636
Test name
Test status
Simulation time 3793246547 ps
CPU time 13.52 seconds
Started Jun 07 08:11:25 PM PDT 24
Finished Jun 07 08:11:41 PM PDT 24
Peak memory 216208 kb
Host smart-d556b13c-e153-4219-9d1b-a0a7b9beb555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278386254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2278386254
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.4212302670
Short name T368
Test name
Test status
Simulation time 1389075126 ps
CPU time 6.92 seconds
Started Jun 07 08:11:29 PM PDT 24
Finished Jun 07 08:11:37 PM PDT 24
Peak memory 215992 kb
Host smart-c29cc098-3212-4776-822d-714fe8b75707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212302670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4212302670
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2238788364
Short name T514
Test name
Test status
Simulation time 454304997 ps
CPU time 1.67 seconds
Started Jun 07 08:11:29 PM PDT 24
Finished Jun 07 08:11:32 PM PDT 24
Peak memory 216076 kb
Host smart-a0c52b85-8e7b-46e8-9182-5d043cdb85c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238788364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2238788364
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1034304411
Short name T319
Test name
Test status
Simulation time 87328497 ps
CPU time 0.83 seconds
Started Jun 07 08:11:30 PM PDT 24
Finished Jun 07 08:11:32 PM PDT 24
Peak memory 205576 kb
Host smart-e0d74c5d-e930-42c2-8b8e-ebda8e15aca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034304411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1034304411
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2403841974
Short name T810
Test name
Test status
Simulation time 995269838 ps
CPU time 6 seconds
Started Jun 07 08:11:31 PM PDT 24
Finished Jun 07 08:11:39 PM PDT 24
Peak memory 220948 kb
Host smart-570798a7-cb70-411c-a1b8-815bc355f40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403841974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2403841974
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2420628884
Short name T768
Test name
Test status
Simulation time 14955034 ps
CPU time 0.7 seconds
Started Jun 07 08:11:35 PM PDT 24
Finished Jun 07 08:11:37 PM PDT 24
Peak memory 205520 kb
Host smart-cfe95c6b-7689-42e5-8ebf-e73c54f45890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420628884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2420628884
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2324897749
Short name T814
Test name
Test status
Simulation time 55954890 ps
CPU time 1.94 seconds
Started Jun 07 08:11:35 PM PDT 24
Finished Jun 07 08:11:38 PM PDT 24
Peak memory 222984 kb
Host smart-6ee8b642-2f38-4197-83d7-4fcbddbd5e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324897749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2324897749
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.802370720
Short name T745
Test name
Test status
Simulation time 13178926 ps
CPU time 0.72 seconds
Started Jun 07 08:11:37 PM PDT 24
Finished Jun 07 08:11:40 PM PDT 24
Peak memory 205540 kb
Host smart-78a0a3ea-6796-4cef-aa96-61d9d93d81ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802370720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.802370720
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3477303545
Short name T210
Test name
Test status
Simulation time 3654462187 ps
CPU time 64.99 seconds
Started Jun 07 08:11:36 PM PDT 24
Finished Jun 07 08:12:43 PM PDT 24
Peak memory 248984 kb
Host smart-c9dca632-fee4-4318-a04b-11d926ee50d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477303545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3477303545
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3304760574
Short name T126
Test name
Test status
Simulation time 32028019110 ps
CPU time 318.54 seconds
Started Jun 07 08:11:35 PM PDT 24
Finished Jun 07 08:16:56 PM PDT 24
Peak memory 265436 kb
Host smart-a44deb8e-1250-49c5-9661-fb13f03a28aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304760574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3304760574
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3740377839
Short name T440
Test name
Test status
Simulation time 4217738357 ps
CPU time 25.19 seconds
Started Jun 07 08:11:39 PM PDT 24
Finished Jun 07 08:12:09 PM PDT 24
Peak memory 217164 kb
Host smart-c798fa94-a3f3-4d4a-b730-a67b90362bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740377839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3740377839
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.378678026
Short name T284
Test name
Test status
Simulation time 589580445 ps
CPU time 3.61 seconds
Started Jun 07 08:11:35 PM PDT 24
Finished Jun 07 08:11:41 PM PDT 24
Peak memory 224336 kb
Host smart-c8d6d969-5bb7-4a59-aa25-7ab9e0c1aff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378678026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.378678026
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3536946191
Short name T456
Test name
Test status
Simulation time 142961509 ps
CPU time 2.81 seconds
Started Jun 07 08:11:36 PM PDT 24
Finished Jun 07 08:11:41 PM PDT 24
Peak memory 224304 kb
Host smart-57624869-c4f7-408e-8cd4-936f39dbb4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536946191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3536946191
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.905640342
Short name T186
Test name
Test status
Simulation time 9522132607 ps
CPU time 49.57 seconds
Started Jun 07 08:11:34 PM PDT 24
Finished Jun 07 08:12:25 PM PDT 24
Peak memory 240208 kb
Host smart-fe696861-544b-4dfd-b19e-8084310f9ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905640342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.905640342
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3350688029
Short name T544
Test name
Test status
Simulation time 625631281 ps
CPU time 4.11 seconds
Started Jun 07 08:11:37 PM PDT 24
Finished Jun 07 08:11:43 PM PDT 24
Peak memory 232512 kb
Host smart-c1a5b00a-90a1-42f1-ac92-3d9bc19ddb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350688029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3350688029
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3054190424
Short name T457
Test name
Test status
Simulation time 535345296 ps
CPU time 3.36 seconds
Started Jun 07 08:11:36 PM PDT 24
Finished Jun 07 08:11:41 PM PDT 24
Peak memory 224332 kb
Host smart-12bd1eda-2760-4d1d-a878-205454b9bbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054190424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3054190424
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.690893080
Short name T817
Test name
Test status
Simulation time 832479271 ps
CPU time 9.92 seconds
Started Jun 07 08:11:40 PM PDT 24
Finished Jun 07 08:11:54 PM PDT 24
Peak memory 219832 kb
Host smart-2c5399a9-e7ec-4e2a-8596-575d98df990c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=690893080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.690893080
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.398532178
Short name T384
Test name
Test status
Simulation time 60127328537 ps
CPU time 260.9 seconds
Started Jun 07 08:11:39 PM PDT 24
Finished Jun 07 08:16:03 PM PDT 24
Peak memory 252592 kb
Host smart-63a75f0c-a9c3-42dd-be51-63c91e206184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398532178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.398532178
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.544625909
Short name T347
Test name
Test status
Simulation time 4884087112 ps
CPU time 17.12 seconds
Started Jun 07 08:11:36 PM PDT 24
Finished Jun 07 08:11:56 PM PDT 24
Peak memory 216172 kb
Host smart-2496162b-b919-4e8d-a94f-43ba335fa0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544625909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.544625909
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1312450108
Short name T348
Test name
Test status
Simulation time 1166153023 ps
CPU time 2.62 seconds
Started Jun 07 08:11:36 PM PDT 24
Finished Jun 07 08:11:41 PM PDT 24
Peak memory 216064 kb
Host smart-e59872ac-a9b7-438d-b83e-7ff5bbd1d71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312450108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1312450108
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1605183509
Short name T546
Test name
Test status
Simulation time 378721726 ps
CPU time 1.47 seconds
Started Jun 07 08:11:38 PM PDT 24
Finished Jun 07 08:11:42 PM PDT 24
Peak memory 216044 kb
Host smart-7b9fb388-d944-4a3f-a416-01667ad98c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605183509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1605183509
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.468324253
Short name T78
Test name
Test status
Simulation time 28384472 ps
CPU time 0.77 seconds
Started Jun 07 08:11:35 PM PDT 24
Finished Jun 07 08:11:37 PM PDT 24
Peak memory 205508 kb
Host smart-7a265f1c-e301-4751-bcb2-c7cb8409d260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468324253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.468324253
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1893337110
Short name T354
Test name
Test status
Simulation time 758368748 ps
CPU time 3.58 seconds
Started Jun 07 08:11:35 PM PDT 24
Finished Jun 07 08:11:40 PM PDT 24
Peak memory 232556 kb
Host smart-61f009e7-6434-4e57-9d3b-6b32169677c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893337110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1893337110
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1631960014
Short name T801
Test name
Test status
Simulation time 13907794 ps
CPU time 0.71 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:14 PM PDT 24
Peak memory 204416 kb
Host smart-1e5c392c-43a0-438b-b27d-381e55603749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631960014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
631960014
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1873557941
Short name T551
Test name
Test status
Simulation time 88880067 ps
CPU time 2.74 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:23 PM PDT 24
Peak memory 218440 kb
Host smart-dc53f0f5-7203-4dc8-9cb2-70aa69d31887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873557941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1873557941
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2462642434
Short name T434
Test name
Test status
Simulation time 20737268 ps
CPU time 0.85 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:20 PM PDT 24
Peak memory 206220 kb
Host smart-a8bd6cb2-7a21-4c60-98a0-774c6db1e347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462642434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2462642434
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1821548528
Short name T63
Test name
Test status
Simulation time 32225538812 ps
CPU time 56.41 seconds
Started Jun 07 08:09:12 PM PDT 24
Finished Jun 07 08:10:13 PM PDT 24
Peak memory 224372 kb
Host smart-eddb6ac9-8a1e-4ca4-8004-d4b5f01c72d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821548528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1821548528
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2362079561
Short name T22
Test name
Test status
Simulation time 3404953193 ps
CPU time 14.34 seconds
Started Jun 07 08:09:12 PM PDT 24
Finished Jun 07 08:09:30 PM PDT 24
Peak memory 217084 kb
Host smart-db647e38-450b-4204-90c2-805e8ac404ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362079561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2362079561
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2359258946
Short name T233
Test name
Test status
Simulation time 41980687719 ps
CPU time 82.59 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:10:40 PM PDT 24
Peak memory 221240 kb
Host smart-939b95ed-afc9-47fc-9e91-a838d8b7a088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359258946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2359258946
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1812448311
Short name T736
Test name
Test status
Simulation time 419932067 ps
CPU time 5.76 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:25 PM PDT 24
Peak memory 224344 kb
Host smart-2c2b0da9-a4d0-43ec-94ca-0ea89d879c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812448311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1812448311
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.813169428
Short name T341
Test name
Test status
Simulation time 494418357 ps
CPU time 4.32 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:24 PM PDT 24
Peak memory 232548 kb
Host smart-6534f2b2-e824-45c9-9b70-aa0d8f1c9310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813169428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.813169428
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.15673952
Short name T479
Test name
Test status
Simulation time 220014747 ps
CPU time 2.3 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:20 PM PDT 24
Peak memory 223640 kb
Host smart-247e42fb-f1f1-4a15-9de9-1f3b028a4935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15673952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.15673952
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.762371422
Short name T509
Test name
Test status
Simulation time 28875487 ps
CPU time 1.01 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:15 PM PDT 24
Peak memory 216260 kb
Host smart-f5e05119-a227-4f54-92e8-21bf723820d9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762371422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.762371422
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2845691049
Short name T780
Test name
Test status
Simulation time 8379884129 ps
CPU time 25.74 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:44 PM PDT 24
Peak memory 240596 kb
Host smart-db4d7504-13a7-49db-a8fb-96ae03df21c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845691049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2845691049
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1433677589
Short name T590
Test name
Test status
Simulation time 59682172 ps
CPU time 2.79 seconds
Started Jun 07 08:09:16 PM PDT 24
Finished Jun 07 08:09:26 PM PDT 24
Peak memory 232268 kb
Host smart-46813d8d-d046-4700-84be-d51b109d12ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433677589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1433677589
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.381815486
Short name T81
Test name
Test status
Simulation time 660017883 ps
CPU time 4.15 seconds
Started Jun 07 08:09:12 PM PDT 24
Finished Jun 07 08:09:20 PM PDT 24
Peak memory 218736 kb
Host smart-058315dd-c41f-4ff5-8e32-22e172258baf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=381815486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.381815486
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3601948199
Short name T71
Test name
Test status
Simulation time 4178721753 ps
CPU time 25.91 seconds
Started Jun 07 08:09:09 PM PDT 24
Finished Jun 07 08:09:37 PM PDT 24
Peak memory 232644 kb
Host smart-7d5cf2e2-a384-4c4f-a3fc-7be8da360c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601948199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3601948199
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3294129547
Short name T729
Test name
Test status
Simulation time 17107584643 ps
CPU time 12.16 seconds
Started Jun 07 08:09:12 PM PDT 24
Finished Jun 07 08:09:27 PM PDT 24
Peak memory 216116 kb
Host smart-052ebc13-4548-4db6-a327-3ff03b929940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294129547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3294129547
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2299578718
Short name T400
Test name
Test status
Simulation time 13112298194 ps
CPU time 9.42 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:23 PM PDT 24
Peak memory 216084 kb
Host smart-b9690046-dbf4-45ff-a265-01c1a6bf363f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299578718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2299578718
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1427897797
Short name T956
Test name
Test status
Simulation time 21791081 ps
CPU time 0.93 seconds
Started Jun 07 08:09:17 PM PDT 24
Finished Jun 07 08:09:24 PM PDT 24
Peak memory 206524 kb
Host smart-1794b534-e943-4c33-935d-39f65f93694f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427897797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1427897797
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1691667336
Short name T324
Test name
Test status
Simulation time 23347893 ps
CPU time 0.83 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:18 PM PDT 24
Peak memory 205612 kb
Host smart-0dda2e91-f730-440a-ade2-5afda220d23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691667336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1691667336
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1042271444
Short name T782
Test name
Test status
Simulation time 98100176 ps
CPU time 2.06 seconds
Started Jun 07 08:09:10 PM PDT 24
Finished Jun 07 08:09:14 PM PDT 24
Peak memory 216360 kb
Host smart-96a11765-022b-4d4f-b9e8-b6c886c3d116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042271444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1042271444
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3141288762
Short name T762
Test name
Test status
Simulation time 11249316 ps
CPU time 0.67 seconds
Started Jun 07 08:09:12 PM PDT 24
Finished Jun 07 08:09:16 PM PDT 24
Peak memory 205192 kb
Host smart-88831b09-b26e-4fc4-acfb-965413fd62a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141288762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
141288762
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3519606042
Short name T794
Test name
Test status
Simulation time 612892707 ps
CPU time 7.32 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:28 PM PDT 24
Peak memory 224348 kb
Host smart-a07205a8-d000-4fbd-836d-471c585eeb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519606042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3519606042
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1513052640
Short name T743
Test name
Test status
Simulation time 49834982 ps
CPU time 0.79 seconds
Started Jun 07 08:09:12 PM PDT 24
Finished Jun 07 08:09:16 PM PDT 24
Peak memory 205228 kb
Host smart-3b2f42c7-ed7e-4d09-8a11-3fe4ed71f5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513052640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1513052640
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1057928200
Short name T155
Test name
Test status
Simulation time 14253464035 ps
CPU time 94.54 seconds
Started Jun 07 08:09:16 PM PDT 24
Finished Jun 07 08:10:57 PM PDT 24
Peak memory 248952 kb
Host smart-3b895dc9-7ad2-4593-83c0-8849eb6fc2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057928200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1057928200
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.338050881
Short name T53
Test name
Test status
Simulation time 10086244646 ps
CPU time 153.92 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:11:54 PM PDT 24
Peak memory 267096 kb
Host smart-4a47ea58-01c5-4d4d-adfc-6a9f26b2c877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338050881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.338050881
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3532941021
Short name T822
Test name
Test status
Simulation time 44410177817 ps
CPU time 214.71 seconds
Started Jun 07 08:09:15 PM PDT 24
Finished Jun 07 08:12:55 PM PDT 24
Peak memory 256184 kb
Host smart-9265b77d-217c-4ebe-b0f7-400988eac616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532941021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3532941021
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.194674481
Short name T759
Test name
Test status
Simulation time 3417988244 ps
CPU time 40.78 seconds
Started Jun 07 08:09:16 PM PDT 24
Finished Jun 07 08:10:03 PM PDT 24
Peak memory 240768 kb
Host smart-4adb6246-9ef6-493a-bda3-cb9ab15450aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194674481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.194674481
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.4103655642
Short name T450
Test name
Test status
Simulation time 3561850729 ps
CPU time 13.03 seconds
Started Jun 07 08:09:15 PM PDT 24
Finished Jun 07 08:09:34 PM PDT 24
Peak memory 224360 kb
Host smart-66eb6fc9-7b9f-469e-a41c-6134fdc6ebad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103655642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4103655642
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.420211045
Short name T253
Test name
Test status
Simulation time 4625304218 ps
CPU time 10.86 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:31 PM PDT 24
Peak memory 224132 kb
Host smart-fa380339-235c-4648-827b-be59727ae3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420211045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.420211045
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2348135080
Short name T436
Test name
Test status
Simulation time 46505745 ps
CPU time 1.06 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:15 PM PDT 24
Peak memory 216384 kb
Host smart-325f3c3a-8b69-43e1-8512-874026995685
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348135080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2348135080
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.732474808
Short name T178
Test name
Test status
Simulation time 1264246325 ps
CPU time 8.57 seconds
Started Jun 07 08:09:15 PM PDT 24
Finished Jun 07 08:09:30 PM PDT 24
Peak memory 224120 kb
Host smart-6ce6f972-195d-4866-b140-f11b28136a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732474808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
732474808
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.4281253109
Short name T36
Test name
Test status
Simulation time 1239533832 ps
CPU time 6.37 seconds
Started Jun 07 08:09:17 PM PDT 24
Finished Jun 07 08:09:30 PM PDT 24
Peak memory 224296 kb
Host smart-88766fb6-deae-4584-ac76-fa6478576922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281253109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.4281253109
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.439389145
Short name T47
Test name
Test status
Simulation time 274070242 ps
CPU time 3.5 seconds
Started Jun 07 08:09:16 PM PDT 24
Finished Jun 07 08:09:26 PM PDT 24
Peak memory 221984 kb
Host smart-66b9ebee-7503-4b7c-bf4e-6997aa3623e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=439389145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.439389145
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2461628266
Short name T69
Test name
Test status
Simulation time 169845175 ps
CPU time 1.14 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:19 PM PDT 24
Peak memory 206728 kb
Host smart-edd5f2b0-4471-481b-8f65-35b5723d67d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461628266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2461628266
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.608836149
Short name T459
Test name
Test status
Simulation time 395517031 ps
CPU time 7.55 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:26 PM PDT 24
Peak memory 216052 kb
Host smart-4138987d-0d20-4a61-800b-3500f25bb185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608836149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.608836149
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.760990205
Short name T328
Test name
Test status
Simulation time 14406957057 ps
CPU time 12.96 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:27 PM PDT 24
Peak memory 216164 kb
Host smart-0fd33428-a40c-4290-ac2e-3891bc1a4cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760990205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.760990205
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3766173736
Short name T352
Test name
Test status
Simulation time 27463597 ps
CPU time 0.88 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:21 PM PDT 24
Peak memory 205612 kb
Host smart-9ad2adfa-d84e-45ce-858c-2c21d62ac825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766173736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3766173736
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.359757856
Short name T676
Test name
Test status
Simulation time 137141131 ps
CPU time 0.8 seconds
Started Jun 07 08:09:15 PM PDT 24
Finished Jun 07 08:09:23 PM PDT 24
Peak memory 205616 kb
Host smart-b25ea189-2cc4-40ab-810d-36f7de771fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359757856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.359757856
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1317127558
Short name T245
Test name
Test status
Simulation time 1906873972 ps
CPU time 6.3 seconds
Started Jun 07 08:09:11 PM PDT 24
Finished Jun 07 08:09:20 PM PDT 24
Peak memory 224320 kb
Host smart-b9759dda-84ca-451c-b29d-be013758d131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317127558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1317127558
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4260810268
Short name T886
Test name
Test status
Simulation time 49756864 ps
CPU time 0.74 seconds
Started Jun 07 08:09:19 PM PDT 24
Finished Jun 07 08:09:26 PM PDT 24
Peak memory 205164 kb
Host smart-4789555c-bb07-420e-a841-ce1dd0e61f72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260810268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
260810268
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3281601741
Short name T273
Test name
Test status
Simulation time 850980199 ps
CPU time 6.39 seconds
Started Jun 07 08:09:18 PM PDT 24
Finished Jun 07 08:09:31 PM PDT 24
Peak memory 224360 kb
Host smart-0dc9d463-3058-4110-875a-0916825d8524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281601741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3281601741
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3137805946
Short name T370
Test name
Test status
Simulation time 25360459 ps
CPU time 0.76 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:09:27 PM PDT 24
Peak memory 206540 kb
Host smart-6b0df520-8744-4cc3-b255-a255376148d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137805946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3137805946
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3183155949
Short name T571
Test name
Test status
Simulation time 21074518867 ps
CPU time 87.31 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:10:45 PM PDT 24
Peak memory 249088 kb
Host smart-06e800ae-1d43-4fe0-9c33-9ad067e4655c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183155949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3183155949
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.585895760
Short name T694
Test name
Test status
Simulation time 1688861542 ps
CPU time 25.52 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:44 PM PDT 24
Peak memory 237004 kb
Host smart-2f8b4cd3-8b91-477f-af60-2d8f09fa6e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585895760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
585895760
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3276423695
Short name T776
Test name
Test status
Simulation time 4816845381 ps
CPU time 25.7 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:43 PM PDT 24
Peak memory 224404 kb
Host smart-5989321d-e1b9-4fe2-97ed-0569fc6bcb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276423695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3276423695
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.707454372
Short name T772
Test name
Test status
Simulation time 7072358400 ps
CPU time 20.42 seconds
Started Jun 07 08:09:16 PM PDT 24
Finished Jun 07 08:09:43 PM PDT 24
Peak memory 232644 kb
Host smart-6b87d5e0-3e61-44d5-90ef-1387617b8aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707454372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.707454372
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3188036820
Short name T591
Test name
Test status
Simulation time 43277817419 ps
CPU time 78.53 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:10:37 PM PDT 24
Peak memory 224380 kb
Host smart-41d41898-f810-4065-8149-34c0f9dc2bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188036820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3188036820
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2182619630
Short name T358
Test name
Test status
Simulation time 17720312 ps
CPU time 1.1 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:09:28 PM PDT 24
Peak memory 216356 kb
Host smart-baa0dcf1-4c99-49cd-84f5-b876088cbcf4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182619630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2182619630
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2272625848
Short name T521
Test name
Test status
Simulation time 28096349734 ps
CPU time 21.28 seconds
Started Jun 07 08:09:18 PM PDT 24
Finished Jun 07 08:09:46 PM PDT 24
Peak memory 232488 kb
Host smart-7026f241-939d-4502-8640-cf66eba6c237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272625848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2272625848
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.4117032944
Short name T266
Test name
Test status
Simulation time 1118691739 ps
CPU time 4.95 seconds
Started Jun 07 08:09:16 PM PDT 24
Finished Jun 07 08:09:28 PM PDT 24
Peak memory 232508 kb
Host smart-0b5901b8-a11f-4f35-b073-148ac5571826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117032944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.4117032944
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1714700566
Short name T723
Test name
Test status
Simulation time 415649101 ps
CPU time 3.8 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:24 PM PDT 24
Peak memory 218640 kb
Host smart-9f8c2154-1fa3-48fc-ab88-fb09da3bbe47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1714700566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1714700566
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.317325481
Short name T220
Test name
Test status
Simulation time 7811096614 ps
CPU time 103.26 seconds
Started Jun 07 08:09:19 PM PDT 24
Finished Jun 07 08:11:09 PM PDT 24
Peak memory 250032 kb
Host smart-0bec6271-9d8f-4a24-b66e-a72b3d359529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317325481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.317325481
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4221284661
Short name T525
Test name
Test status
Simulation time 7465559378 ps
CPU time 15.85 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:34 PM PDT 24
Peak memory 216144 kb
Host smart-c3b837ed-14b6-4380-9283-de6f23bce683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221284661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4221284661
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3065949622
Short name T516
Test name
Test status
Simulation time 327265117 ps
CPU time 1.21 seconds
Started Jun 07 08:09:13 PM PDT 24
Finished Jun 07 08:09:19 PM PDT 24
Peak memory 206680 kb
Host smart-a6448998-b516-4c63-9a5e-2b6d9b4b5d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065949622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3065949622
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4083397818
Short name T802
Test name
Test status
Simulation time 32159289 ps
CPU time 1.23 seconds
Started Jun 07 08:09:17 PM PDT 24
Finished Jun 07 08:09:25 PM PDT 24
Peak memory 207652 kb
Host smart-1708c8d3-d616-433b-8e0d-b5a8c439b316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083397818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4083397818
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3361052280
Short name T907
Test name
Test status
Simulation time 118237535 ps
CPU time 0.78 seconds
Started Jun 07 08:09:14 PM PDT 24
Finished Jun 07 08:09:21 PM PDT 24
Peak memory 205620 kb
Host smart-62e24e42-aa33-4ef0-80e4-dd6e3f799ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361052280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3361052280
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.4048305884
Short name T862
Test name
Test status
Simulation time 2508247527 ps
CPU time 5.76 seconds
Started Jun 07 08:09:18 PM PDT 24
Finished Jun 07 08:09:31 PM PDT 24
Peak memory 240772 kb
Host smart-c7f6a830-ef96-4ba6-aed4-a67d78a0345d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048305884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.4048305884
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.4199894746
Short name T917
Test name
Test status
Simulation time 38003339 ps
CPU time 0.76 seconds
Started Jun 07 08:09:23 PM PDT 24
Finished Jun 07 08:09:29 PM PDT 24
Peak memory 205200 kb
Host smart-cc1bdb77-70cd-40fa-845a-3391e8d011ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199894746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.4
199894746
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.570157707
Short name T429
Test name
Test status
Simulation time 69510095 ps
CPU time 2.67 seconds
Started Jun 07 08:09:25 PM PDT 24
Finished Jun 07 08:09:33 PM PDT 24
Peak memory 232496 kb
Host smart-a0c8776c-0656-4297-917c-c665e314edf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570157707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.570157707
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2811652175
Short name T300
Test name
Test status
Simulation time 25426234 ps
CPU time 0.79 seconds
Started Jun 07 08:09:17 PM PDT 24
Finished Jun 07 08:09:25 PM PDT 24
Peak memory 206268 kb
Host smart-168362ae-cb72-44e7-8292-aafe68e73267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811652175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2811652175
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2341964398
Short name T957
Test name
Test status
Simulation time 13161695106 ps
CPU time 61.67 seconds
Started Jun 07 08:09:22 PM PDT 24
Finished Jun 07 08:10:30 PM PDT 24
Peak memory 249128 kb
Host smart-49e898f7-473e-4145-80ac-c359c4465070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341964398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2341964398
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.4127908860
Short name T563
Test name
Test status
Simulation time 45779272141 ps
CPU time 115.8 seconds
Started Jun 07 08:09:27 PM PDT 24
Finished Jun 07 08:11:27 PM PDT 24
Peak memory 240868 kb
Host smart-868315a3-a52f-4168-8de0-a644b37902c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127908860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.4127908860
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.4111974817
Short name T841
Test name
Test status
Simulation time 70421565 ps
CPU time 3.19 seconds
Started Jun 07 08:09:21 PM PDT 24
Finished Jun 07 08:09:31 PM PDT 24
Peak memory 224348 kb
Host smart-edcf1676-3d7e-4e5f-9598-69e7f4e93e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111974817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4111974817
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3868403865
Short name T635
Test name
Test status
Simulation time 695260148 ps
CPU time 7.57 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:09:34 PM PDT 24
Peak memory 224288 kb
Host smart-7930e02e-90a7-4eed-aaf4-b1a363008e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868403865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3868403865
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3787643412
Short name T809
Test name
Test status
Simulation time 11271333389 ps
CPU time 42.11 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:10:09 PM PDT 24
Peak memory 224352 kb
Host smart-43aa196a-ad74-4406-ad3b-00ed268c4599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787643412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3787643412
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.4057168353
Short name T863
Test name
Test status
Simulation time 221860507 ps
CPU time 1.05 seconds
Started Jun 07 08:09:21 PM PDT 24
Finished Jun 07 08:09:28 PM PDT 24
Peak memory 216392 kb
Host smart-0450636d-9782-46d6-bf31-b6ff5b23d6d0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057168353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.4057168353
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3399226717
Short name T275
Test name
Test status
Simulation time 2024390813 ps
CPU time 5.41 seconds
Started Jun 07 08:09:19 PM PDT 24
Finished Jun 07 08:09:31 PM PDT 24
Peak memory 232572 kb
Host smart-5dd573df-f8dc-4b91-898f-b8f44cb25fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399226717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3399226717
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.733136980
Short name T56
Test name
Test status
Simulation time 12627999985 ps
CPU time 9.94 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:09:36 PM PDT 24
Peak memory 232580 kb
Host smart-72040a4c-ae4c-49b5-b3a5-4929714a3637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733136980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.733136980
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1968819880
Short name T507
Test name
Test status
Simulation time 372610352 ps
CPU time 4.18 seconds
Started Jun 07 08:09:24 PM PDT 24
Finished Jun 07 08:09:33 PM PDT 24
Peak memory 222752 kb
Host smart-d814484b-fc43-4a27-9d2e-d142c9e339e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1968819880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1968819880
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.323589541
Short name T918
Test name
Test status
Simulation time 9610683368 ps
CPU time 22.54 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:09:49 PM PDT 24
Peak memory 216160 kb
Host smart-c6c3254b-4cee-45f5-89cc-ab45f207f73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323589541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.323589541
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3421885746
Short name T608
Test name
Test status
Simulation time 1635706839 ps
CPU time 7.22 seconds
Started Jun 07 08:09:21 PM PDT 24
Finished Jun 07 08:09:35 PM PDT 24
Peak memory 216028 kb
Host smart-858cc39c-7a13-4f55-842d-5007a241856b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421885746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3421885746
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.211654972
Short name T857
Test name
Test status
Simulation time 69343300 ps
CPU time 1.1 seconds
Started Jun 07 08:09:21 PM PDT 24
Finished Jun 07 08:09:28 PM PDT 24
Peak memory 207840 kb
Host smart-9e49d2af-2dd2-4b38-a7a5-30760731ee1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211654972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.211654972
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.448472590
Short name T630
Test name
Test status
Simulation time 303119566 ps
CPU time 0.92 seconds
Started Jun 07 08:09:21 PM PDT 24
Finished Jun 07 08:09:28 PM PDT 24
Peak memory 205620 kb
Host smart-273803ae-1cba-4472-9d36-49c08d19b09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448472590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.448472590
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1389169333
Short name T61
Test name
Test status
Simulation time 85927745916 ps
CPU time 13.32 seconds
Started Jun 07 08:09:17 PM PDT 24
Finished Jun 07 08:09:37 PM PDT 24
Peak memory 224272 kb
Host smart-f0753c9f-1ca3-43c6-9b3b-7c92750e79e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389169333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1389169333
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1465927081
Short name T548
Test name
Test status
Simulation time 13750760 ps
CPU time 0.71 seconds
Started Jun 07 08:09:24 PM PDT 24
Finished Jun 07 08:09:30 PM PDT 24
Peak memory 205160 kb
Host smart-a557e4e9-8cab-4384-be5b-019cbd53eb59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465927081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
465927081
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1224510755
Short name T394
Test name
Test status
Simulation time 101619252 ps
CPU time 2.78 seconds
Started Jun 07 08:09:21 PM PDT 24
Finished Jun 07 08:09:30 PM PDT 24
Peak memory 232140 kb
Host smart-c4991f46-d8b1-415a-ad5a-ca88ea78ceb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224510755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1224510755
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2484492813
Short name T387
Test name
Test status
Simulation time 36413999 ps
CPU time 0.82 seconds
Started Jun 07 08:09:19 PM PDT 24
Finished Jun 07 08:09:27 PM PDT 24
Peak memory 206244 kb
Host smart-f2bc5695-b2c4-41d3-a00a-bf22afe677e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484492813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2484492813
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1769685214
Short name T223
Test name
Test status
Simulation time 100496229473 ps
CPU time 82.87 seconds
Started Jun 07 08:09:24 PM PDT 24
Finished Jun 07 08:10:52 PM PDT 24
Peak memory 251588 kb
Host smart-ecce7b86-69c7-4923-879f-00425a22e440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769685214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1769685214
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1365407881
Short name T748
Test name
Test status
Simulation time 13740168604 ps
CPU time 142.15 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:11:49 PM PDT 24
Peak memory 256900 kb
Host smart-c329faf4-b387-4dfb-953a-26324a2a41dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365407881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1365407881
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4282625368
Short name T204
Test name
Test status
Simulation time 9109192709 ps
CPU time 62.03 seconds
Started Jun 07 08:09:23 PM PDT 24
Finished Jun 07 08:10:31 PM PDT 24
Peak memory 251064 kb
Host smart-355e967f-6715-48c9-9c0c-61552a44b9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282625368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4282625368
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2678729423
Short name T493
Test name
Test status
Simulation time 1597896345 ps
CPU time 19.69 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:09:46 PM PDT 24
Peak memory 237172 kb
Host smart-68da583d-70d0-4d1e-9f16-3379302a7216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678729423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2678729423
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.883320139
Short name T325
Test name
Test status
Simulation time 46206094 ps
CPU time 2.57 seconds
Started Jun 07 08:09:22 PM PDT 24
Finished Jun 07 08:09:31 PM PDT 24
Peak memory 224244 kb
Host smart-e80d26e8-2c97-41dd-8680-17b82e0914d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883320139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.883320139
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1682659831
Short name T51
Test name
Test status
Simulation time 594250126 ps
CPU time 13.87 seconds
Started Jun 07 08:09:22 PM PDT 24
Finished Jun 07 08:09:42 PM PDT 24
Peak memory 232604 kb
Host smart-90b0b450-6a35-483c-818d-71532ff484dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682659831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1682659831
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.4173124774
Short name T402
Test name
Test status
Simulation time 49274411 ps
CPU time 1.07 seconds
Started Jun 07 08:09:21 PM PDT 24
Finished Jun 07 08:09:29 PM PDT 24
Peak memory 217636 kb
Host smart-2a6bcf79-de23-496d-8252-c7a9a8535b25
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173124774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.4173124774
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3767896706
Short name T557
Test name
Test status
Simulation time 2110597353 ps
CPU time 10.62 seconds
Started Jun 07 08:09:23 PM PDT 24
Finished Jun 07 08:09:39 PM PDT 24
Peak memory 232532 kb
Host smart-f1be2616-4f8c-4f2c-9550-d9dbe8cda8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767896706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3767896706
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4092379741
Short name T474
Test name
Test status
Simulation time 961089484 ps
CPU time 9.14 seconds
Started Jun 07 08:09:25 PM PDT 24
Finished Jun 07 08:09:39 PM PDT 24
Peak memory 237604 kb
Host smart-4b09260e-aa9f-4126-b7e8-e1311b4b3df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092379741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4092379741
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.965500508
Short name T846
Test name
Test status
Simulation time 766425196 ps
CPU time 10.5 seconds
Started Jun 07 08:09:25 PM PDT 24
Finished Jun 07 08:09:41 PM PDT 24
Peak memory 222344 kb
Host smart-da730f03-160b-45a0-a34f-d70849411f5d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=965500508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.965500508
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3237083797
Short name T889
Test name
Test status
Simulation time 600228035 ps
CPU time 1.03 seconds
Started Jun 07 08:09:20 PM PDT 24
Finished Jun 07 08:09:28 PM PDT 24
Peak memory 206556 kb
Host smart-d7a8b51d-3531-44e3-903f-7de423268296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237083797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3237083797
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1684860148
Short name T286
Test name
Test status
Simulation time 4784166438 ps
CPU time 30.51 seconds
Started Jun 07 08:09:19 PM PDT 24
Finished Jun 07 08:09:57 PM PDT 24
Peak memory 216260 kb
Host smart-ffdf4879-0fa1-41a8-8f7d-17fd792ee038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684860148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1684860148
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1377121134
Short name T642
Test name
Test status
Simulation time 1639634457 ps
CPU time 6.25 seconds
Started Jun 07 08:09:23 PM PDT 24
Finished Jun 07 08:09:35 PM PDT 24
Peak memory 215996 kb
Host smart-b573d296-acb0-4401-afce-00eeec1ffb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377121134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1377121134
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1363315406
Short name T351
Test name
Test status
Simulation time 173975113 ps
CPU time 3.52 seconds
Started Jun 07 08:09:21 PM PDT 24
Finished Jun 07 08:09:31 PM PDT 24
Peak memory 215608 kb
Host smart-8a24d29c-56ae-4223-880a-192d23160dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363315406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1363315406
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3151348443
Short name T561
Test name
Test status
Simulation time 123930890 ps
CPU time 1.11 seconds
Started Jun 07 08:09:21 PM PDT 24
Finished Jun 07 08:09:29 PM PDT 24
Peak memory 205584 kb
Host smart-85eb7450-5976-4c46-9226-f3780e0ceb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151348443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3151348443
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.676995802
Short name T898
Test name
Test status
Simulation time 1752414403 ps
CPU time 4.87 seconds
Started Jun 07 08:09:19 PM PDT 24
Finished Jun 07 08:09:30 PM PDT 24
Peak memory 232564 kb
Host smart-a94f70e4-f808-4ed5-abd2-05eb3276388f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676995802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.676995802
Directory /workspace/9.spi_device_upload/latest
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