Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2826525	1			T1	90315		T2	1		T3	1
all_values[1]	2826525	1			T1	90315		T2	1		T3	1
all_values[2]	2826525	1			T1	90315		T2	1		T3	1
all_values[3]	2826525	1			T1	90315		T2	1		T3	1
all_values[4]	2826525	1			T1	90315		T2	1		T3	1
all_values[5]	2826525	1			T1	90315		T2	1		T3	1
all_values[6]	2826525	1			T1	90315		T2	1		T3	1
all_values[7]	2826525	1			T1	90315		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20479259

1

T1

428356

T2

8

T3

8

auto[1]

2132941

1

T1

294164

T11

42

T18

43

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22588278

1

T1

722214

T2

8

T3

8

auto[1]

23922

1

T1

306

T10

5

T11

585

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2604508	1			T1	23074		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	11073	1			T1	142		T10	5		T11	368
all_values[0]	auto[1]	auto[0]	210097	1			T1	67047		T11	4		T26	9
all_values[0]	auto[1]	auto[1]	847	1			T1	52		T11	3		T18	2
all_values[1]	auto[0]	auto[0]	2559086	1			T1	67082		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	6161	1			T1	18		T11	135		T13	71
all_values[1]	auto[1]	auto[0]	260602	1			T1	23185		T11	4		T18	3
all_values[1]	auto[1]	auto[1]	676	1			T1	30		T11	3		T18	5
all_values[2]	auto[0]	auto[0]	2603650	1			T1	90299		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2471	1			T1	12		T11	43		T14	13
all_values[2]	auto[1]	auto[0]	219938	1			T1	2		T11	4		T18	5
all_values[2]	auto[1]	auto[1]	466	1			T1	2		T11	5		T18	4
all_values[3]	auto[0]	auto[0]	2680643	1			T1	67094		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	220	1			T1	6		T11	4		T18	5
all_values[3]	auto[1]	auto[0]	145443	1			T1	23211		T18	4		T26	4
all_values[3]	auto[1]	auto[1]	219	1			T1	4		T11	2		T26	4
all_values[4]	auto[0]	auto[0]	2525582	1			T2	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	217	1			T1	5		T11	3		T18	5
all_values[4]	auto[1]	auto[0]	300487	1			T1	90302		T18	2		T26	4
all_values[4]	auto[1]	auto[1]	239	1			T1	8		T11	6		T18	1
all_values[5]	auto[0]	auto[0]	2599606	1			T1	67095		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	334	1			T1	7		T11	1		T18	4
all_values[5]	auto[1]	auto[0]	226373	1			T1	23210		T11	4		T18	1
all_values[5]	auto[1]	auto[1]	212	1			T1	3		T11	1		T26	5
all_values[6]	auto[0]	auto[0]	2403973	1			T1	23208		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	171	1			T1	4		T11	4		T35	1
all_values[6]	auto[1]	auto[0]	422166	1			T1	67099		T11	2		T18	8
all_values[6]	auto[1]	auto[1]	215	1			T1	4		T11	1		T18	2
all_values[7]	auto[0]	auto[0]	2481369	1			T1	90303		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	195	1			T1	7		T11	5		T18	5
all_values[7]	auto[1]	auto[0]	344755	1			T1	3		T11	2		T18	5
all_values[7]	auto[1]	auto[1]	206	1			T1	2		T11	1		T18	1