Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	31637	1			T1	150		T3	8		T5	2
auto[SpiFlashAddrCfg]	6893	1			T1	73		T2	4		T5	2
auto[SpiFlashAddr3b]	8221	1			T1	79		T2	2		T5	2
auto[SpiFlashAddr4b]	6672	1			T1	43		T2	2		T8	17

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30452

1

T1

189

T2

8

T3

8

auto[1]

22971

1

T1

156

T8

53

T10

32

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28155

1

T1

189

T2

2

T3

8

auto[1]

25268

1

T1

156

T2

6

T5

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	35560	1			T1	180		T3	8		T5	2
values[1]	989	1			T1	12		T11	16		T14	1
values[2]	1275	1			T1	14		T8	3		T10	3
values[3]	1340	1			T1	8		T2	2		T5	2
values[4]	1397	1			T1	13		T8	1		T10	6
values[5]	1254	1			T1	14		T8	3		T10	4
values[6]	1353	1			T1	7		T2	4		T8	1
values[7]	1288	1			T1	5		T8	3		T10	3
values[8]	8967	1			T1	92		T2	2		T5	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30030

1

T1

168

T2

8

T3

8

auto[1]

23393

1

T1

177

T8

101

T11

322

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

51535

1

T1

330

T2

8

T3

8

write

1888

1

T1

15

T8

6

T10

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

17714

1

T1

182

T2

6

T3

8

valids[0x1]

35709

1

T1

163

T2

2

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1341	1			T1	14		T8	5		T10	2
internal_process_ops[0x5a]	1375	1			T1	12		T8	2		T10	2
internal_process_ops[0x05]	19446	1			T1	35		T8	28		T10	9
internal_process_ops[0x35]	1355	1			T1	14		T8	1		T10	4
internal_process_ops[0x15]	1349	1			T1	12		T5	2		T8	6
internal_process_ops[0x03]	906	1			T1	5		T10	1		T11	8
internal_process_ops[0x0b]	969	1			T1	12		T2	2		T11	13
internal_process_ops[0x3b]	1025	1			T1	10		T5	2		T8	1
internal_process_ops[0x6b]	982	1			T1	5		T2	4		T8	1
internal_process_ops[0xbb]	973	1			T1	6		T5	2		T10	3
internal_process_ops[0xeb]	1020	1			T1	14		T2	2		T10	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52460

1

T1

332

T2

8

T3

8

auto[1]

963

1

T1

13

T8

1

T11

15

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51652

1

T1

329

T2

8

T3

8

auto[1]

1771

1

T1

16

T8

3

T10

5

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10516

1

T1

31

T3

8

T5

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6419

1

T1

27

T10

14

T11

24

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2141

1

T1

16

T2

4

T5

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1737

1

T1

24

T10

3

T11

19

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2409

1

T1

21

T2

2

T5

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2055

1

T1

18

T10

5

T11

27

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2045

1

T1

14

T2

2

T10

11

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1710

1

T1

12

T10

9

T11

19

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

80

1

T62

2

T28

1

T150

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

57

1

T1

2

T28

2

T33

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

36

1

T1

1

T30

1

T151

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

73

1

T28

4

T32

2

T33

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

87

1

T10

2

T11

2

T25

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

56

1

T28

1

T31

2

T33

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

67

1

T10

1

T11

2

T35

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

51

1

T1

1

T11

2

T25

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

82

1

T11

1

T63

2

T152

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

57

1

T1

1

T25

1

T35

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

51

1

T11

2

T25

1

T35

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

62

1

T11

3

T29

2

T30

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

79

1

T10

1

T11

3

T27

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

59

1

T32

3

T34

3

T151

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

43

1

T25

2

T35

1

T30

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

58

1

T33

1

T34

3

T153

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8085

1

T1

61

T8

31

T11

117

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6165

1

T1

23

T8

29

T11

54

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1306

1

T1

9

T8

3

T11

21

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1216

1

T1

21

T8

10

T11

26

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1638

1

T1

20

T8

4

T11

24

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1624

1

T1

16

T8

3

T11

30

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1311

1

T1

11

T8

6

T11

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1158

1

T1

6

T8

9

T11

15

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

49

1

T13

1

T35

1

T36

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

47

1

T1

1

T8

1

T13

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

56

1

T1

1

T11

2

T18

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

54

1

T1

3

T14

1

T18

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

52

1

T8

1

T11

1

T14

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

77

1

T1

2

T11

4

T14

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

48

1

T8

2

T17

2

T36

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

55

1

T11

1

T14

4

T154

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

65

1

T11

1

T41

2

T36

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

62

1

T11

1

T41

3

T36

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

44

1

T35

1

T36

1

T120

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

72

1

T1

3

T11

3

T41

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

41

1

T8

2

T11

2

T18

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

51

1

T11

1

T13

1

T17

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

45

1

T17

2

T18

1

T154

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

72

1

T41

2

T121

3

T155

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3844	1			T1	31		T3	8		T10	22
auto[0]	values[0]	valids[0x1]	15480	1			T1	50		T5	2		T10	27
auto[0]	values[1]	valids[0x1]	545	1			T1	7		T11	7		T25	3
auto[0]	values[2]	valids[0x0]	494	1			T1	8		T10	1		T11	5
auto[0]	values[2]	valids[0x1]	263	1			T1	1		T10	2		T11	2
auto[0]	values[3]	valids[0x0]	530	1			T1	4		T2	2		T5	2
auto[0]	values[3]	valids[0x1]	274	1			T1	1		T11	6		T25	3
auto[0]	values[4]	valids[0x0]	541	1			T1	1		T10	3		T11	4
auto[0]	values[4]	valids[0x1]	301	1			T1	8		T10	3		T11	4
auto[0]	values[5]	valids[0x0]	497	1			T1	2		T10	3		T12	2
auto[0]	values[5]	valids[0x1]	271	1			T1	1		T10	1		T11	3
auto[0]	values[6]	valids[0x0]	549	1			T1	5		T2	4		T10	2
auto[0]	values[6]	valids[0x1]	274	1			T11	4		T25	2		T152	2
auto[0]	values[7]	valids[0x0]	518	1			T1	2		T10	3		T11	4
auto[0]	values[7]	valids[0x1]	263	1			T11	3		T25	5		T28	3
auto[0]	values[8]	valids[0x0]	3344	1			T1	34		T5	2		T10	12
auto[0]	values[8]	valids[0x1]	2042	1			T1	13		T2	2		T10	5
auto[1]	values[0]	valids[0x0]	3410	1			T1	37		T8	18		T11	62
auto[1]	values[0]	valids[0x1]	12826	1			T1	62		T8	51		T11	156
auto[1]	values[1]	valids[0x1]	444	1			T1	5		T11	9		T14	1
auto[1]	values[2]	valids[0x0]	305	1			T1	4		T8	1		T11	3
auto[1]	values[2]	valids[0x1]	213	1			T1	1		T8	2		T11	3
auto[1]	values[3]	valids[0x0]	312	1			T1	1		T8	6		T11	1
auto[1]	values[3]	valids[0x1]	224	1			T1	2		T11	5		T13	3
auto[1]	values[4]	valids[0x0]	342	1			T1	3		T8	1		T11	8
auto[1]	values[4]	valids[0x1]	213	1			T1	1		T11	7		T14	2
auto[1]	values[5]	valids[0x0]	284	1			T1	10		T8	3		T11	2
auto[1]	values[5]	valids[0x1]	202	1			T1	1		T11	3		T13	2
auto[1]	values[6]	valids[0x0]	328	1			T1	2		T11	7		T14	5
auto[1]	values[6]	valids[0x1]	202	1			T8	1		T11	1		T14	3
auto[1]	values[7]	valids[0x0]	289	1			T1	2		T8	2		T11	8
auto[1]	values[7]	valids[0x1]	218	1			T1	1		T8	1		T13	1
auto[1]	values[8]	valids[0x0]	2127	1			T1	36		T8	6		T11	32
auto[1]	values[8]	valids[0x1]	1454	1			T1	9		T8	9		T11	15