Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2991667

1

T1

28546

T2

4322

T3

2553

auto[1]

18074

1

T1

25

T8

21

T10

5

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

878718

1

T1

98

T2

4322

T3

2553

auto[1]

2131023

1

T1

28473

T5

4

T8

6006

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	518272	1			T1	3601		T2	10		T3	949
auto[524288:1048575]	331134	1			T1	14		T2	877		T3	798
auto[1048576:1572863]	331777	1			T1	5045		T2	11		T5	76
auto[1572864:2097151]	349187	1			T1	15		T2	237		T3	1
auto[2097152:2621439]	414877	1			T1	887		T2	1373		T5	79
auto[2621440:3145727]	368700	1			T1	9780		T3	11		T4	4
auto[3145728:3670015]	374347	1			T1	5541		T2	1569		T3	794
auto[3670016:4194303]	321447	1			T1	3688		T2	245		T8	15

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2149649

1

T1

28569

T2

27

T3

192

auto[1]

860092

1

T1

2

T2

4295

T3

2361

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2644491

1

T1

15719

T2

4322

T3

2553

auto[1]

365250

1

T1

12852

T8

4314

T10

1684

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	176629	1			T1	6		T2	10		T3	949
auto[0]	auto[0]	auto[0:524287]	auto[1]	299078	1			T1	3593		T8	1311		T11	497
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	88174	1			T1	6		T2	877		T3	798
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	205501	1			T1	6		T10	2		T11	5313
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	95297	1			T1	14		T2	11		T5	76
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	201354	1			T1	3024		T8	1		T11	1716
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	92887	1			T1	8		T2	237		T3	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	196071	1			T1	2		T10	2937		T11	6615
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	115195	1			T1	8		T2	1373		T5	77
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	239492	1			T1	874		T5	2		T8	256
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	118836	1			T1	6		T3	11		T4	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	194651	1			T1	3256		T10	1		T11	822
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	102775	1			T1	4		T2	1569		T3	794
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	226443	1			T1	4759		T5	2		T8	110
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	73896	1			T1	3		T2	245		T8	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	203436	1			T1	129		T8	1		T10	2155
auto[0]	auto[1]	auto[0:524287]	auto[0]	591	1			T8	2		T11	5		T14	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	38729	1			T8	2		T11	2		T14	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	327	1			T1	1		T11	3		T14	5
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	34808	1			T10	256		T11	708		T14	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2615	1			T1	1		T8	1		T11	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	30421	1			T1	2001		T10	5		T18	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2914	1			T8	1		T11	10		T13	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	55194	1			T8	3283		T11	2837		T13	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	2931	1			T1	2		T11	1		T14	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	55297	1			T1	3		T8	1024		T11	262
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	278	1			T1	13		T10	6		T11	6
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	53117	1			T1	6499		T10	1415		T13	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1273	1			T1	4		T11	4		T18	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	41203	1			T1	769		T11	2733		T36	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2324	1			T1	6		T8	1		T11	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	39930	1			T1	3549		T13	4		T25	512
auto[1]	auto[0]	auto[0:524287]	auto[0]	232	1			T1	2		T8	1		T11	6
auto[1]	auto[0]	auto[0:524287]	auto[1]	2378	1			T8	9		T11	46		T13	6
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	181	1			T1	1		T10	2		T11	4
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1789	1			T11	30		T25	19		T18	7
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	166	1			T1	3		T8	1		T11	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1527	1			T1	2		T8	1		T11	25
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	154	1			T1	2		T11	2		T13	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1472	1			T1	3		T11	7		T13	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	164	1			T11	2		T14	1		T25	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1522	1			T11	6		T14	7		T25	44
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	187	1			T1	1		T10	1		T11	10
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1272	1			T1	2		T11	34		T13	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	182	1			T1	2		T11	1		T14	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2062	1			T1	2		T11	1		T14	15
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	173	1			T1	1		T8	1		T11	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1315	1			T8	8		T41	3		T36	3
auto[1]	auto[1]	auto[0:524287]	auto[0]	60	1			T11	2		T14	1		T18	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	575	1			T11	1		T154	10		T120	19
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	38	1			T11	1		T14	1		T28	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	316	1			T11	2		T14	3		T28	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	31	1			T41	2		T120	2		T32	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	366	1			T41	7		T120	3		T32	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	48	1			T11	2		T13	2		T41	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	447	1			T11	33		T13	6		T41	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	39	1			T11	1		T14	1		T18	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	237	1			T11	1		T14	7		T18	9
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	46	1			T1	3		T10	2		T13	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	313	1			T13	2		T17	1		T259	6
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	47	1			T1	1		T36	1		T121	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	362	1			T121	93		T155	5		T175	7
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	28	1			T31	1		T33	1		T165	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	345	1			T31	27		T33	14		T165	4

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1780879	1			T1	15698		T2	27		T3	192
auto[0]	auto[0]	auto[1]	848836	1			T2	4295		T3	2361		T4	410
auto[0]	auto[1]	auto[0]	350988	1			T1	12848		T8	4314		T10	1682
auto[0]	auto[1]	auto[1]	10964	1			T11	2		T74	9		T75	11
auto[1]	auto[0]	auto[0]	14527	1			T1	19		T8	19		T10	3
auto[1]	auto[0]	auto[1]	249	1			T1	2		T8	2		T11	3
auto[1]	auto[1]	auto[0]	3255	1			T1	4		T10	2		T11	42
auto[1]	auto[1]	auto[1]	43	1			T11	1		T32	3		T33	1