Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17668

1

T1

85

T2

8

T3

8

auto[1]

12362

1

T1

83

T10

32

T11

98

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2927	1			T10	43		T62	24		T25	46
values[1]	3870	1			T1	22		T10	22		T11	40
values[2]	4239	1			T1	63		T3	8		T25	42
values[3]	4290	1			T1	22		T5	6		T11	192
values[4]	3675	1			T1	20		T11	20		T27	6
values[5]	3376	1			T11	65		T12	12		T137	8
values[6]	3547	1			T1	21		T11	78		T25	35
values[7]	4106	1			T1	20		T2	8		T10	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3863	1			T5	6		T11	58		T12	12
values[1]	3404	1			T1	45		T11	40		T150	16
values[2]	4313	1			T1	41		T11	40		T28	25
values[3]	3660	1			T1	20		T10	21		T11	23
values[4]	3798	1			T1	20		T11	37		T27	6
values[5]	3780	1			T1	22		T3	8		T10	42
values[6]	3249	1			T2	8		T11	40		T25	53
values[7]	3963	1			T1	20		T10	22		T11	83

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	213	1			T62	24		T32	8		T33	11
auto[0]	values[0]	values[1]	160	1			T265	19		T266	26		T216	14
auto[0]	values[0]	values[2]	216	1			T31	8		T33	14		T175	21
auto[0]	values[0]	values[3]	193	1			T10	14		T25	11		T166	12
auto[0]	values[0]	values[4]	209	1			T30	38		T33	11		T174	10
auto[0]	values[0]	values[5]	194	1			T10	18		T180	48		T191	11
auto[0]	values[0]	values[6]	127	1			T25	13		T33	30		T174	15
auto[0]	values[0]	values[7]	325	1			T75	16		T33	22		T174	16
auto[0]	values[1]	values[0]	421	1			T147	2		T34	23		T149	10
auto[0]	values[1]	values[1]	169	1			T11	14		T267	14		T175	11
auto[0]	values[1]	values[2]	232	1			T11	9		T28	19		T34	18
auto[0]	values[1]	values[3]	191	1			T161	17		T258	20		T163	8
auto[0]	values[1]	values[4]	357	1			T30	16		T31	16		T165	16
auto[0]	values[1]	values[5]	278	1			T1	14		T30	25		T165	8
auto[0]	values[1]	values[6]	229	1			T32	31		T33	13		T34	21
auto[0]	values[1]	values[7]	263	1			T10	9		T31	10		T151	6
auto[0]	values[2]	values[0]	494	1			T25	8		T28	12		T81	26
auto[0]	values[2]	values[1]	254	1			T1	13		T169	4		T31	11
auto[0]	values[2]	values[2]	354	1			T1	11		T35	10		T166	15
auto[0]	values[2]	values[3]	142	1			T165	8		T149	8		T166	18
auto[0]	values[2]	values[4]	181	1			T28	13		T183	10		T151	11
auto[0]	values[2]	values[5]	215	1			T3	8		T32	44		T153	39
auto[0]	values[2]	values[6]	299	1			T153	12		T188	15		T143	22
auto[0]	values[2]	values[7]	312	1			T1	7		T165	30		T161	14
auto[0]	values[3]	values[0]	156	1			T5	6		T63	22		T30	10
auto[0]	values[3]	values[1]	177	1			T1	8		T11	13		T33	7
auto[0]	values[3]	values[2]	425	1			T11	14		T165	16		T151	8
auto[0]	values[3]	values[3]	278	1			T101	6		T182	14		T179	2
auto[0]	values[3]	values[4]	376	1			T30	13		T34	54		T174	10
auto[0]	values[3]	values[5]	320	1			T11	66		T102	2		T33	13
auto[0]	values[3]	values[6]	302	1			T11	18		T25	6		T28	10
auto[0]	values[3]	values[7]	536	1			T11	47		T28	11		T160	14
auto[0]	values[4]	values[0]	256	1			T174	11		T149	12		T260	14
auto[0]	values[4]	values[1]	297	1			T150	16		T151	9		T180	20
auto[0]	values[4]	values[2]	201	1			T33	11		T165	14		T34	12
auto[0]	values[4]	values[3]	611	1			T165	10		T160	12		T161	11
auto[0]	values[4]	values[4]	205	1			T1	15		T27	6		T165	7
auto[0]	values[4]	values[5]	329	1			T11	11		T74	12		T152	8
auto[0]	values[4]	values[6]	301	1			T26	17		T34	11		T153	14
auto[0]	values[4]	values[7]	188	1			T186	8		T165	11		T175	14
auto[0]	values[5]	values[0]	280	1			T12	12		T31	80		T153	10
auto[0]	values[5]	values[1]	320	1			T149	11		T181	11		T188	29
auto[0]	values[5]	values[2]	232	1			T268	18		T175	15		T192	14
auto[0]	values[5]	values[3]	206	1			T28	7		T32	22		T151	7
auto[0]	values[5]	values[4]	303	1			T11	33		T25	10		T33	9
auto[0]	values[5]	values[5]	160	1			T34	14		T162	12		T181	24
auto[0]	values[5]	values[6]	176	1			T34	12		T153	10		T180	8
auto[0]	values[5]	values[7]	245	1			T11	17		T149	29		T193	13
auto[0]	values[6]	values[0]	435	1			T11	50		T151	61		T188	11
auto[0]	values[6]	values[1]	123	1			T172	26		T190	20		T261	20
auto[0]	values[6]	values[2]	364	1			T1	6		T197	8		T174	14
auto[0]	values[6]	values[3]	135	1			T76	20		T269	6		T216	10
auto[0]	values[6]	values[4]	282	1			T32	13		T151	11		T149	17
auto[0]	values[6]	values[5]	306	1			T25	12		T35	9		T33	10
auto[0]	values[6]	values[6]	295	1			T11	16		T35	10		T34	6
auto[0]	values[6]	values[7]	280	1			T270	4		T166	28		T77	24
auto[0]	values[7]	values[0]	244	1			T161	10		T271	8		T206	17
auto[0]	values[7]	values[1]	393	1			T31	41		T151	10		T153	27
auto[0]	values[7]	values[2]	328	1			T32	56		T185	6		T153	33
auto[0]	values[7]	values[3]	227	1			T1	11		T11	12		T31	11
auto[0]	values[7]	values[4]	259	1			T25	26		T32	14		T194	6
auto[0]	values[7]	values[5]	531	1			T10	12		T180	160		T175	14
auto[0]	values[7]	values[6]	324	1			T2	8		T28	13		T272	18
auto[0]	values[7]	values[7]	234	1			T103	4		T35	11		T161	12
auto[1]	values[0]	values[0]	136	1			T32	12		T33	9		T163	5
auto[1]	values[0]	values[1]	134	1			T216	30		T273	10		T177	14
auto[1]	values[0]	values[2]	154	1			T31	21		T33	12		T175	7
auto[1]	values[0]	values[3]	316	1			T10	7		T25	15		T166	8
auto[1]	values[0]	values[4]	126	1			T30	4		T33	25		T174	32
auto[1]	values[0]	values[5]	146	1			T10	4		T180	8		T191	13
auto[1]	values[0]	values[6]	84	1			T25	7		T33	20		T174	5
auto[1]	values[0]	values[7]	194	1			T33	64		T174	4		T191	9
auto[1]	values[1]	values[0]	94	1			T34	17		T178	10		T149	10
auto[1]	values[1]	values[1]	153	1			T11	6		T175	9		T171	12
auto[1]	values[1]	values[2]	541	1			T11	11		T28	6		T34	13
auto[1]	values[1]	values[3]	234	1			T196	24		T161	5		T163	12
auto[1]	values[1]	values[4]	224	1			T30	8		T31	67		T165	7
auto[1]	values[1]	values[5]	172	1			T1	8		T30	15		T165	21
auto[1]	values[1]	values[6]	107	1			T32	9		T33	11		T34	8
auto[1]	values[1]	values[7]	205	1			T10	13		T31	19		T151	14
auto[1]	values[2]	values[0]	473	1			T25	34		T28	8		T34	16
auto[1]	values[2]	values[1]	307	1			T1	10		T31	9		T34	78
auto[1]	values[2]	values[2]	299	1			T1	9		T187	14		T35	14
auto[1]	values[2]	values[3]	264	1			T254	8		T165	30		T274	12
auto[1]	values[2]	values[4]	87	1			T28	7		T151	9		T181	7
auto[1]	values[2]	values[5]	307	1			T32	26		T153	6		T160	8
auto[1]	values[2]	values[6]	141	1			T153	36		T188	9		T143	18
auto[1]	values[2]	values[7]	110	1			T1	13		T165	9		T161	6
auto[1]	values[3]	values[0]	113	1			T30	10		T157	16		T34	11
auto[1]	values[3]	values[1]	318	1			T1	14		T11	7		T33	22
auto[1]	values[3]	values[2]	301	1			T11	6		T165	4		T151	69
auto[1]	values[3]	values[3]	233	1			T32	9		T33	30		T34	8
auto[1]	values[3]	values[4]	244	1			T30	9		T34	8		T174	10
auto[1]	values[3]	values[5]	142	1			T11	11		T33	8		T149	8
auto[1]	values[3]	values[6]	115	1			T11	2		T25	27		T28	11
auto[1]	values[3]	values[7]	254	1			T11	8		T28	13		T160	6
auto[1]	values[4]	values[0]	73	1			T174	10		T149	8		T167	7
auto[1]	values[4]	values[1]	213	1			T198	6		T151	11		T180	3
auto[1]	values[4]	values[2]	142	1			T33	9		T165	6		T34	15
auto[1]	values[4]	values[3]	203	1			T165	15		T160	11		T161	9
auto[1]	values[4]	values[4]	131	1			T1	5		T165	27		T223	24
auto[1]	values[4]	values[5]	121	1			T11	9		T30	9		T32	3
auto[1]	values[4]	values[6]	188	1			T26	3		T34	44		T153	13
auto[1]	values[4]	values[7]	216	1			T165	46		T175	6		T181	19
auto[1]	values[5]	values[0]	155	1			T31	7		T153	10		T166	8
auto[1]	values[5]	values[1]	86	1			T149	9		T181	12		T188	21
auto[1]	values[5]	values[2]	145	1			T175	5		T192	6		T163	4
auto[1]	values[5]	values[3]	152	1			T137	8		T28	13		T32	13
auto[1]	values[5]	values[4]	407	1			T11	4		T25	48		T158	18
auto[1]	values[5]	values[5]	186	1			T34	6		T162	71		T181	18
auto[1]	values[5]	values[6]	185	1			T34	10		T153	10		T180	12
auto[1]	values[5]	values[7]	138	1			T11	11		T149	2		T193	7
auto[1]	values[6]	values[0]	178	1			T11	8		T151	62		T188	11
auto[1]	values[6]	values[1]	71	1			T222	12		T275	30		T276	8
auto[1]	values[6]	values[2]	124	1			T1	15		T174	8		T151	7
auto[1]	values[6]	values[3]	88	1			T216	30		T145	12		T273	26
auto[1]	values[6]	values[4]	246	1			T32	7		T151	74		T149	3
auto[1]	values[6]	values[5]	202	1			T25	23		T35	11		T33	10
auto[1]	values[6]	values[6]	118	1			T11	4		T35	12		T34	14
auto[1]	values[6]	values[7]	300	1			T166	13		T162	11		T181	4
auto[1]	values[7]	values[0]	142	1			T29	12		T161	10		T206	9
auto[1]	values[7]	values[1]	229	1			T31	3		T151	10		T153	28
auto[1]	values[7]	values[2]	255	1			T32	11		T153	10		T161	11
auto[1]	values[7]	values[3]	187	1			T1	9		T11	11		T31	9
auto[1]	values[7]	values[4]	161	1			T25	8		T32	6		T153	11
auto[1]	values[7]	values[5]	171	1			T10	8		T277	14		T180	9
auto[1]	values[7]	values[6]	258	1			T28	7		T34	20		T191	6
auto[1]	values[7]	values[7]	163	1			T35	9		T161	16		T163	12