Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2826525	1			T1	90315		T2	1		T3	1
all_pins[1]	2826525	1			T1	90315		T2	1		T3	1
all_pins[2]	2826525	1			T1	90315		T2	1		T3	1
all_pins[3]	2826525	1			T1	90315		T2	1		T3	1
all_pins[4]	2826525	1			T1	90315		T2	1		T3	1
all_pins[5]	2826525	1			T1	90315		T2	1		T3	1
all_pins[6]	2826525	1			T1	90315		T2	1		T3	1
all_pins[7]	2826525	1			T1	90315		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22183755	1			T1	655023		T2	8		T3	8
values[0x1]	428445	1			T1	67497		T11	22		T18	15
transitions[0x0=>0x1]	425624	1			T1	67488		T11	14		T18	13
transitions[0x1=>0x0]	425639	1			T1	67488		T11	14		T18	13

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2825610	1			T1	90257		T2	1		T3	1
all_pins[0]	values[0x1]	915	1			T1	58		T11	3		T18	2
all_pins[0]	transitions[0x0=>0x1]	679	1			T1	56		T11	1		T18	2
all_pins[0]	transitions[0x1=>0x0]	491	1			T1	31		T11	1		T18	5
all_pins[1]	values[0x0]	2825798	1			T1	90282		T2	1		T3	1
all_pins[1]	values[0x1]	727	1			T1	33		T11	3		T18	5
all_pins[1]	transitions[0x0=>0x1]	638	1			T1	32		T11	1		T18	3
all_pins[1]	transitions[0x1=>0x0]	393	1			T1	1		T11	3		T18	2
all_pins[2]	values[0x0]	2826043	1			T1	90313		T2	1		T3	1
all_pins[2]	values[0x1]	482	1			T1	2		T11	5		T18	4
all_pins[2]	transitions[0x0=>0x1]	416	1			T1	1		T11	3		T18	4
all_pins[2]	transitions[0x1=>0x0]	153	1			T1	3		T26	4		T35	3
all_pins[3]	values[0x0]	2826306	1			T1	90311		T2	1		T3	1
all_pins[3]	values[0x1]	219	1			T1	4		T11	2		T26	4
all_pins[3]	transitions[0x0=>0x1]	158	1			T1	2		T26	3		T35	3
all_pins[3]	transitions[0x1=>0x0]	178	1			T1	6		T11	4		T18	1
all_pins[4]	values[0x0]	2826286	1			T1	90307		T2	1		T3	1
all_pins[4]	values[0x1]	239	1			T1	8		T11	6		T18	1
all_pins[4]	transitions[0x0=>0x1]	189	1			T1	7		T11	6		T18	1
all_pins[4]	transitions[0x1=>0x0]	3838	1			T1	304		T11	1		T26	2
all_pins[5]	values[0x0]	2822637	1			T1	90010		T2	1		T3	1
all_pins[5]	values[0x1]	3888	1			T1	305		T11	1		T26	5
all_pins[5]	transitions[0x0=>0x1]	1681	1			T1	305		T11	1		T26	3
all_pins[5]	transitions[0x1=>0x0]	419562	1			T1	67085		T11	1		T18	2
all_pins[6]	values[0x0]	2404756	1			T1	23230		T2	1		T3	1
all_pins[6]	values[0x1]	421769	1			T1	67085		T11	1		T18	2
all_pins[6]	transitions[0x0=>0x1]	421717	1			T1	67084		T11	1		T18	2
all_pins[6]	transitions[0x1=>0x0]	154	1			T1	1		T11	1		T18	1
all_pins[7]	values[0x0]	2826319	1			T1	90313		T2	1		T3	1
all_pins[7]	values[0x1]	206	1			T1	2		T11	1		T18	1
all_pins[7]	transitions[0x0=>0x1]	146	1			T1	1		T11	1		T18	1
all_pins[7]	transitions[0x1=>0x0]	870	1			T1	57		T11	3		T18	2