Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	351	1			T1	6		T10	1		T11	4
auto[ReadAddrCrossIntoMailbox]	321	1			T1	8		T2	2		T10	1
auto[ReadAddrCrossOutOfMailbox]	311	1			T1	6		T10	1		T11	5
auto[ReadAddrCrossAllMailbox]	194	1			T1	1		T11	2		T28	4
auto[ReadAddrOutsideMailbox]	3399	1			T1	23		T2	4		T5	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2288

1

T1

25

T2

3

T5

2

auto[1]

2288

1

T1

19

T2

3

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	702	1			T1	4		T10	1		T11	7
read_ops[0x0b]	733	1			T1	10		T2	2		T11	9
read_ops[0x3b]	795	1			T1	7		T5	2		T10	4
read_ops[0x6b]	769	1			T1	5		T2	4		T10	1
read_ops[0xbb]	771	1			T1	4		T5	2		T10	3
read_ops[0xeb]	806	1			T1	14		T10	4		T11	13

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T34	1		T174	1		T151	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T1	1		T28	1		T180	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T11	1		T151	2		T153	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T165	1		T77	1		T161	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T11	1		T33	1		T151	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T1	2		T25	1		T149	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T11	1		T165	1		T145	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T28	1		T151	1		T149	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	238	1			T1	1		T11	1		T25	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T10	1		T11	3		T25	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T25	1		T199	2		T180	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T11	2		T35	1		T199	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T1	2		T2	1		T33	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T1	1		T2	1		T165	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T1	1		T30	1		T151	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T1	1		T11	1		T30	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T1	1		T32	1		T33	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T34	1		T162	1		T278	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	289	1			T1	1		T11	3		T27	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	259	1			T1	3		T11	3		T27	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T1	2		T35	1		T32	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T10	1		T32	1		T33	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T1	1		T11	1		T32	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T11	1		T31	1		T34	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T1	1		T35	1		T199	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T10	1		T199	2		T34	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T199	1		T32	1		T151	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T199	1		T31	1		T77	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	306	1			T1	3		T5	1		T10	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	286	1			T5	1		T11	2		T25	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T35	1		T33	1		T165	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T1	1		T32	1		T165	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	39	1			T1	1		T25	1		T32	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T10	1		T11	1		T33	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T35	1		T30	1		T33	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T32	2		T149	1		T153	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T151	1		T149	1		T77	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T11	1		T33	1		T153	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T1	2		T2	2		T11	6
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	300	1			T1	1		T2	2		T11	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T11	1		T165	1		T34	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T1	1		T31	1		T151	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T28	1		T31	1		T32	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T25	1		T31	2		T174	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T1	1		T199	2		T32	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T11	2		T199	2		T32	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T28	1		T199	1		T151	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T28	1		T35	1		T30	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	288	1			T5	1		T10	1		T11	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	275	1			T1	2		T5	1		T10	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T11	1		T35	1		T199	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T1	1		T199	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T11	1		T149	2		T193	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T1	3		T11	1		T31	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T25	1		T149	1		T279	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T11	1		T31	1		T34	3
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T28	1		T160	1		T143	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T34	1		T162	1		T181	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	307	1			T1	8		T10	2		T11	5
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	297	1			T1	2		T10	2		T11	4