Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.63	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	2	126	98.44

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	2	126	98.44	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4360	1			T1	64		T2	8		T11	55
values[1]	3326	1			T10	22		T11	81		T101	6
values[2]	3722	1			T1	20		T11	20		T62	24
values[3]	4552	1			T1	42		T5	6		T11	165
values[4]	3358	1			T1	20		T3	8		T11	20
values[5]	3607	1			T10	20		T11	37		T63	22
values[6]	3479	1			T10	43		T11	40		T25	20
values[7]	3626	1			T1	22		T28	20		T156	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4073	1			T1	22		T10	22		T11	75
values[1]	3927	1			T10	21		T11	20		T28	20
values[2]	3193	1			T10	22		T11	172		T25	58
values[3]	3608	1			T3	8		T5	6		T27	6
values[4]	4547	1			T1	40		T11	63		T137	8
values[5]	3343	1			T1	62		T62	24		T25	35
values[6]	3760	1			T1	21		T10	20		T11	68
values[7]	3579	1			T1	23		T2	8		T11	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29557

1

T1

164

T2

8

T3

8

auto[1]

473

1

T1

4

T11

5

T25

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	2	126	98.44	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[2]]	[values[2] , values[3]]	--	--	2

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	556	1			T11	55		T157	16		T33	29
auto[0]	values[0]	values[1]	527	1			T158	18		T159	2		T153	19
auto[0]	values[0]	values[2]	323	1			T160	23		T145	21		T65	20
auto[0]	values[0]	values[3]	518	1			T30	20		T161	19		T162	62
auto[0]	values[0]	values[4]	704	1			T1	20		T137	8		T30	20
auto[0]	values[0]	values[5]	282	1			T102	2		T31	20		T163	21
auto[0]	values[0]	values[6]	898	1			T1	21		T33	25		T151	50
auto[0]	values[0]	values[7]	496	1			T1	22		T2	8		T35	20
auto[0]	values[1]	values[0]	490	1			T10	22		T81	26		T33	64
auto[0]	values[1]	values[1]	431	1			T164	46		T165	24		T166	20
auto[0]	values[1]	values[2]	353	1			T11	57		T167	20		T168	14
auto[0]	values[1]	values[3]	524	1			T34	28		T149	29		T161	20
auto[0]	values[1]	values[4]	448	1			T11	23		T152	8		T150	16
auto[0]	values[1]	values[5]	324	1			T101	6		T169	4		T33	31
auto[0]	values[1]	values[6]	349	1			T28	45		T153	48		T160	20
auto[0]	values[1]	values[7]	362	1			T76	20		T170	8		T171	19
auto[0]	values[2]	values[0]	489	1			T172	26		T173	6		T165	20
auto[0]	values[2]	values[1]	795	1			T28	20		T174	62		T161	28
auto[0]	values[2]	values[2]	280	1			T175	28		T176	20		T177	20
auto[0]	values[2]	values[3]	197	1			T25	42		T151	32		T178	10
auto[0]	values[2]	values[4]	599	1			T11	20		T74	12		T179	2
auto[0]	values[2]	values[5]	442	1			T1	20		T62	24		T30	20
auto[0]	values[2]	values[6]	434	1			T25	32		T151	67		T180	25
auto[0]	values[2]	values[7]	418	1			T163	72		T181	57		T143	24
auto[0]	values[3]	values[0]	579	1			T30	24		T165	34		T151	84
auto[0]	values[3]	values[1]	521	1			T11	20		T33	24		T162	19
auto[0]	values[3]	values[2]	485	1			T11	75		T25	58		T174	39
auto[0]	values[3]	values[3]	514	1			T5	6		T27	6		T34	27
auto[0]	values[3]	values[4]	704	1			T11	20		T32	111		T174	20
auto[0]	values[3]	values[5]	780	1			T1	40		T33	18		T34	20
auto[0]	values[3]	values[6]	266	1			T11	48		T147	2		T28	18
auto[0]	values[3]	values[7]	636	1			T12	12		T182	14		T165	38
auto[0]	values[4]	values[0]	536	1			T25	59		T31	86		T180	23
auto[0]	values[4]	values[1]	344	1			T32	20		T151	56		T149	18
auto[0]	values[4]	values[2]	580	1			T26	20		T183	10		T31	44
auto[0]	values[4]	values[3]	372	1			T3	8		T32	19		T33	34
auto[0]	values[4]	values[4]	364	1			T1	20		T184	16		T162	20
auto[0]	values[4]	values[5]	296	1			T185	6		T180	19		T161	35
auto[0]	values[4]	values[6]	411	1			T28	21		T32	25		T34	20
auto[0]	values[4]	values[7]	398	1			T11	20		T32	20		T153	43
auto[0]	values[5]	values[0]	333	1			T149	32		T160	20		T163	20
auto[0]	values[5]	values[1]	570	1			T30	19		T186	8		T32	23
auto[0]	values[5]	values[2]	470	1			T11	37		T165	38		T34	108
auto[0]	values[5]	values[3]	562	1			T28	19		T187	14		T33	66
auto[0]	values[5]	values[4]	273	1			T63	22		T34	21		T151	20
auto[0]	values[5]	values[5]	453	1			T25	35		T181	20		T188	45
auto[0]	values[5]	values[6]	461	1			T10	20		T35	20		T32	17
auto[0]	values[5]	values[7]	428	1			T151	20		T175	20		T189	8
auto[0]	values[6]	values[0]	445	1			T11	18		T29	10		T33	20
auto[0]	values[6]	values[1]	432	1			T10	21		T190	20		T180	168
auto[0]	values[6]	values[2]	337	1			T10	22		T191	20		T192	19
auto[0]	values[6]	values[3]	472	1			T31	81		T151	20		T193	20
auto[0]	values[6]	values[4]	565	1			T194	6		T153	63		T195	23
auto[0]	values[6]	values[5]	332	1			T165	43		T174	21		T166	21
auto[0]	values[6]	values[6]	380	1			T11	20		T25	20		T34	20
auto[0]	values[6]	values[7]	444	1			T103	4		T32	19		T174	42
auto[0]	values[7]	values[0]	587	1			T1	21		T156	2		T32	20
auto[0]	values[7]	values[1]	236	1			T196	24		T197	8		T166	20
auto[0]	values[7]	values[2]	328	1			T28	20		T31	29		T198	6
auto[0]	values[7]	values[3]	406	1			T35	21		T32	35		T151	19
auto[0]	values[7]	values[4]	808	1			T75	16		T31	20		T165	56
auto[0]	values[7]	values[5]	377	1			T35	24		T34	55		T161	28
auto[0]	values[7]	values[6]	497	1			T30	22		T199	22		T165	26
auto[0]	values[7]	values[7]	336	1			T31	29		T165	29		T34	30
auto[1]	values[0]	values[0]	5	1			T34	2		T200	1		T201	2
auto[1]	values[0]	values[1]	7	1			T153	1		T202	1		T203	1
auto[1]	values[0]	values[2]	3	1			T200	2		T204	1		-	-
auto[1]	values[0]	values[3]	5	1			T161	1		T175	1		T181	1
auto[1]	values[0]	values[4]	11	1			T192	2		T171	4		T205	5
auto[1]	values[0]	values[5]	4	1			T163	1		T206	1		T207	1
auto[1]	values[0]	values[6]	16	1			T33	1		T151	3		T163	1
auto[1]	values[0]	values[7]	5	1			T1	1		T208	2		T209	2
auto[1]	values[1]	values[0]	5	1			T210	5		-	-		-	-
auto[1]	values[1]	values[1]	9	1			T165	1		T166	2		T211	1
auto[1]	values[1]	values[2]	3	1			T11	1		T212	1		T213	1
auto[1]	values[1]	values[3]	4	1			T34	1		T149	1		T181	1
auto[1]	values[1]	values[4]	10	1			T166	1		T161	1		T175	2
auto[1]	values[1]	values[5]	4	1			T33	1		T208	1		T214	1
auto[1]	values[1]	values[6]	6	1			T160	1		T188	2		T215	2
auto[1]	values[1]	values[7]	4	1			T171	1		T210	1		T207	1
auto[1]	values[2]	values[0]	7	1			T34	2		T208	1		T214	2
auto[1]	values[2]	values[1]	12	1			T174	2		T161	1		T163	1
auto[1]	values[2]	values[4]	14	1			T30	2		T33	2		T175	1
auto[1]	values[2]	values[5]	11	1			T192	1		T171	3		T216	2
auto[1]	values[2]	values[6]	9	1			T25	2		T145	2		T125	1
auto[1]	values[2]	values[7]	15	1			T217	2		T218	10		T205	3
auto[1]	values[3]	values[0]	6	1			T151	1		T211	2		T207	1
auto[1]	values[3]	values[1]	14	1			T162	1		T195	2		T65	1
auto[1]	values[3]	values[2]	8	1			T11	2		T151	3		T153	2
auto[1]	values[3]	values[3]	3	1			T219	1		T220	1		T221	1
auto[1]	values[3]	values[4]	7	1			T32	1		T162	2		T216	2
auto[1]	values[3]	values[5]	14	1			T1	2		T33	2		T163	6
auto[1]	values[3]	values[6]	3	1			T28	2		T205	1		-	-
auto[1]	values[3]	values[7]	12	1			T34	1		T160	1		T181	1
auto[1]	values[4]	values[0]	12	1			T31	1		T188	2		T214	2
auto[1]	values[4]	values[1]	8	1			T149	2		T143	2		T222	2
auto[1]	values[4]	values[2]	8	1			T33	1		T223	3		T125	2
auto[1]	values[4]	values[3]	8	1			T32	1		T33	2		T188	1
auto[1]	values[4]	values[4]	7	1			T163	1		T217	1		T205	3
auto[1]	values[4]	values[5]	3	1			T180	1		T214	1		T207	1
auto[1]	values[4]	values[6]	5	1			T28	3		T224	1		T66	1
auto[1]	values[4]	values[7]	6	1			T153	2		T162	2		T225	2
auto[1]	values[5]	values[0]	5	1			T145	1		T201	2		T226	2
auto[1]	values[5]	values[1]	11	1			T30	1		T195	3		T202	1
auto[1]	values[5]	values[2]	6	1			T165	1		T161	2		T167	1
auto[1]	values[5]	values[3]	7	1			T28	2		T149	1		T161	1
auto[1]	values[5]	values[4]	7	1			T34	1		T167	2		T219	2
auto[1]	values[5]	values[5]	9	1			T188	5		T227	1		T65	2
auto[1]	values[5]	values[6]	9	1			T32	3		T33	1		T217	2
auto[1]	values[5]	values[7]	3	1			T176	1		T209	2		-	-
auto[1]	values[6]	values[0]	12	1			T11	2		T29	2		T161	1
auto[1]	values[6]	values[1]	9	1			T180	1		T228	4		T229	2
auto[1]	values[6]	values[2]	6	1			T192	1		T208	1		T202	1
auto[1]	values[6]	values[3]	10	1			T31	2		T208	1		T217	4
auto[1]	values[6]	values[4]	8	1			T153	1		T195	1		T230	2
auto[1]	values[6]	values[5]	6	1			T188	2		T143	2		T202	1
auto[1]	values[6]	values[6]	7	1			T231	1		T225	1		T232	1
auto[1]	values[6]	values[7]	14	1			T32	1		T151	3		T233	3
auto[1]	values[7]	values[0]	6	1			T1	1		T202	1		T207	2
auto[1]	values[7]	values[1]	1	1			T201	1		-	-		-	-
auto[1]	values[7]	values[2]	3	1			T234	2		T235	1		-	-
auto[1]	values[7]	values[3]	6	1			T35	1		T151	1		T188	2
auto[1]	values[7]	values[4]	18	1			T165	1		T180	2		T191	2
auto[1]	values[7]	values[5]	6	1			T167	2		T212	1		T209	2
auto[1]	values[7]	values[6]	9	1			T214	2		T235	1		T219	3
auto[1]	values[7]	values[7]	2	1			T216	1		T232	1		-	-