Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1780

1

T1

9

T10

4

T11

17

auto[1]

1748

1

T1

16

T9

4

T10

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1971

1

T1

25

T9

2

T10

5

auto[1]

1557

1

T9

2

T11

7

T14

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2761

1

T1

20

T9

3

T10

4

auto[1]

767

1

T1

5

T9

1

T10

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	649	1			T1	6		T9	2		T10	1
valid[1]	712	1			T1	8		T9	1		T11	2
valid[2]	719	1			T1	4		T10	2		T11	5
valid[3]	732	1			T1	5		T9	1		T10	1
valid[4]	716	1			T1	2		T10	1		T11	10

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	112	1			T1	2		T10	1		T11	2
auto[0]	auto[0]	valid[0]	auto[1]	140	1			T11	1		T71	1		T73	1
auto[0]	auto[0]	valid[1]	auto[0]	143	1			T1	1		T11	2		T13	2
auto[0]	auto[0]	valid[1]	auto[1]	138	1			T41	1		T71	3		T300	1
auto[0]	auto[0]	valid[2]	auto[0]	111	1			T10	2		T11	2		T28	1
auto[0]	auto[0]	valid[2]	auto[1]	160	1			T300	1		T120	2		T301	2
auto[0]	auto[0]	valid[3]	auto[0]	118	1			T1	1		T11	1		T14	1
auto[0]	auto[0]	valid[3]	auto[1]	157	1			T11	2		T300	1		T35	1
auto[0]	auto[0]	valid[4]	auto[0]	116	1			T1	2		T10	1		T11	1
auto[0]	auto[0]	valid[4]	auto[1]	189	1			T11	1		T14	1		T73	3
auto[0]	auto[1]	valid[0]	auto[0]	107	1			T1	3		T9	1		T13	1
auto[0]	auto[1]	valid[0]	auto[1]	142	1			T9	1		T71	1		T73	1
auto[0]	auto[1]	valid[1]	auto[0]	111	1			T1	5		T14	1		T17	2
auto[0]	auto[1]	valid[1]	auto[1]	167	1			T18	1		T73	1		T300	3
auto[0]	auto[1]	valid[2]	auto[0]	126	1			T1	4		T14	1		T16	1
auto[0]	auto[1]	valid[2]	auto[1]	155	1			T71	1		T73	2		T300	1
auto[0]	auto[1]	valid[3]	auto[0]	138	1			T1	2		T11	2		T17	2
auto[0]	auto[1]	valid[3]	auto[1]	151	1			T9	1		T14	1		T71	1
auto[0]	auto[1]	valid[4]	auto[0]	122	1			T11	3		T13	2		T17	6
auto[0]	auto[1]	valid[4]	auto[1]	158	1			T11	3		T73	4		T300	4
auto[1]	auto[0]	valid[0]	auto[0]	74	1			T13	1		T14	2		T18	1
auto[1]	auto[0]	valid[1]	auto[0]	88	1			T1	2		T13	2		T14	3
auto[1]	auto[0]	valid[2]	auto[0]	86	1			T11	3		T16	1		T17	1
auto[1]	auto[0]	valid[3]	auto[0]	82	1			T1	1		T11	2		T16	2
auto[1]	auto[0]	valid[4]	auto[0]	66	1			T14	1		T16	2		T18	1
auto[1]	auto[1]	valid[0]	auto[0]	74	1			T1	1		T11	1		T13	1
auto[1]	auto[1]	valid[1]	auto[0]	65	1			T9	1		T13	1		T14	1
auto[1]	auto[1]	valid[2]	auto[0]	81	1			T14	1		T17	1		T294	1
auto[1]	auto[1]	valid[3]	auto[0]	86	1			T1	1		T10	1		T17	2
auto[1]	auto[1]	valid[4]	auto[0]	65	1			T11	2		T14	2		T28	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal