Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	880	1			T1	14		T11	10		T18	11
all_values[1]	880	1			T1	14		T11	10		T18	11
all_values[2]	880	1			T1	14		T11	10		T18	11
all_values[3]	880	1			T1	14		T11	10		T18	11
all_values[4]	880	1			T1	14		T11	10		T18	11
all_values[5]	880	1			T1	14		T11	10		T18	11
all_values[6]	880	1			T1	14		T11	10		T18	11
all_values[7]	880	1			T1	14		T11	10		T18	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3631

1

T1

56

T11

49

T18

55

auto[1]

3409

1

T1

56

T11

31

T18

33

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2808

1

T1

25

T11

27

T18

28

auto[1]

4232

1

T1

87

T11

53

T18

60

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3983

1

T1

51

T11

36

T18

44

auto[1]

3057

1

T1

61

T11

44

T18

44

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	195	1			T1	3		T11	1		T18	2
all_values[0]	auto[0]	auto[0]	auto[1]	86	1			T1	1		T11	1		T18	2
all_values[0]	auto[0]	auto[1]	auto[0]	147	1			T11	2		T26	6		T35	2
all_values[0]	auto[0]	auto[1]	auto[1]	84	1			T1	3		T11	1		T18	1
all_values[0]	auto[1]	auto[0]	auto[1]	202	1			T1	4		T11	2		T18	6
all_values[0]	auto[1]	auto[1]	auto[1]	166	1			T1	3		T11	3		T26	4
all_values[1]	auto[0]	auto[0]	auto[0]	182	1			T1	1		T11	3		T18	1
all_values[1]	auto[0]	auto[0]	auto[1]	82	1			T1	2		T18	2		T36	1
all_values[1]	auto[0]	auto[1]	auto[0]	163	1			T1	1		T11	2		T18	1
all_values[1]	auto[0]	auto[1]	auto[1]	71	1			T1	2		T11	1		T18	2
all_values[1]	auto[1]	auto[0]	auto[1]	203	1			T1	2		T11	2		T18	3
all_values[1]	auto[1]	auto[1]	auto[1]	179	1			T1	6		T11	2		T18	2
all_values[2]	auto[0]	auto[0]	auto[0]	169	1			T1	3		T11	2		T18	1
all_values[2]	auto[0]	auto[0]	auto[1]	80	1			T1	2		T18	1		T26	1
all_values[2]	auto[0]	auto[1]	auto[0]	160	1			T1	2		T11	1		T18	2
all_values[2]	auto[0]	auto[1]	auto[1]	97	1			T11	1		T18	1		T26	1
all_values[2]	auto[1]	auto[0]	auto[1]	189	1			T1	4		T11	2		T18	2
all_values[2]	auto[1]	auto[1]	auto[1]	185	1			T1	3		T11	4		T18	4
all_values[3]	auto[0]	auto[0]	auto[0]	148	1			T11	2		T18	3		T26	2
all_values[3]	auto[0]	auto[0]	auto[1]	90	1			T1	2		T18	1		T26	2
all_values[3]	auto[0]	auto[1]	auto[0]	164	1			T1	2		T18	1		T26	3
all_values[3]	auto[0]	auto[1]	auto[1]	75	1			T1	1		T26	1		T35	1
all_values[3]	auto[1]	auto[0]	auto[1]	198	1			T1	3		T11	7		T18	3
all_values[3]	auto[1]	auto[1]	auto[1]	205	1			T1	6		T11	1		T18	3
all_values[4]	auto[0]	auto[0]	auto[0]	163	1			T18	2		T26	4		T35	2
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T1	2		T11	3		T18	1
all_values[4]	auto[0]	auto[1]	auto[0]	141	1			T1	1		T18	1		T26	3
all_values[4]	auto[0]	auto[1]	auto[1]	96	1			T1	4		T18	1		T26	2
all_values[4]	auto[1]	auto[0]	auto[1]	196	1			T1	4		T11	2		T18	5
all_values[4]	auto[1]	auto[1]	auto[1]	197	1			T1	3		T11	5		T18	1
all_values[5]	auto[0]	auto[0]	auto[0]	248	1			T1	2		T11	5		T18	7
all_values[5]	auto[0]	auto[1]	auto[0]	229	1			T1	2		T11	3		T26	6
all_values[5]	auto[1]	auto[0]	auto[1]	202	1			T1	7		T11	1		T18	4
all_values[5]	auto[1]	auto[1]	auto[1]	201	1			T1	3		T11	1		T26	5
all_values[6]	auto[0]	auto[0]	auto[0]	188	1			T11	3		T18	3		T26	7
all_values[6]	auto[0]	auto[0]	auto[1]	69	1			T1	1		T11	1		T35	1
all_values[6]	auto[0]	auto[1]	auto[0]	155	1			T1	4		T18	3		T26	3
all_values[6]	auto[0]	auto[1]	auto[1]	91	1			T1	2		T11	1		T18	2
all_values[6]	auto[1]	auto[0]	auto[1]	183	1			T1	3		T11	5		T18	1
all_values[6]	auto[1]	auto[1]	auto[1]	194	1			T1	4		T18	2		T26	1
all_values[7]	auto[0]	auto[0]	auto[0]	201	1			T1	2		T11	2		T26	5
all_values[7]	auto[0]	auto[0]	auto[1]	76	1			T1	4		T18	2		T35	1
all_values[7]	auto[0]	auto[1]	auto[0]	155	1			T1	2		T11	1		T18	1
all_values[7]	auto[0]	auto[1]	auto[1]	91	1			T26	1		T35	2		T149	2
all_values[7]	auto[1]	auto[0]	auto[1]	194	1			T1	4		T11	5		T18	3
all_values[7]	auto[1]	auto[1]	auto[1]	163	1			T1	2		T11	2		T18	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal