Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49589

1

T1

668

T9

195

T10

135

auto[1]

16415

1

T1

8

T9

58

T11

173

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47853

1

T1

475

T9

176

T10

93

auto[1]

18151

1

T1

201

T9

77

T10

42

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33924	1			T1	355		T9	127		T10	68
others[1]	5581	1			T1	60		T9	26		T10	11
others[2]	5499	1			T1	52		T9	24		T10	10
others[3]	6334	1			T1	68		T9	18		T10	14
interest[1]	3724	1			T1	34		T9	17		T10	6
interest[4]	22272	1			T1	248		T9	91		T10	46
interest[64]	10942	1			T1	107		T9	41		T10	26

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16037	1			T1	254		T9	57		T10	47
auto[0]	auto[0]	others[1]	2734	1			T1	39		T9	15		T10	7
auto[0]	auto[0]	others[2]	2645	1			T1	30		T9	11		T10	8
auto[0]	auto[0]	others[3]	3039	1			T1	47		T9	6		T10	7
auto[0]	auto[0]	interest[1]	1739	1			T1	23		T9	11		T10	4
auto[0]	auto[0]	interest[4]	10384	1			T1	179		T9	40		T10	35
auto[0]	auto[0]	interest[64]	5244	1			T1	74		T9	18		T10	20
auto[0]	auto[1]	others[0]	8596	1			T1	4		T9	31		T11	82
auto[0]	auto[1]	others[1]	1354	1			T1	1		T9	8		T11	10
auto[0]	auto[1]	others[2]	1311	1			T9	5		T11	16		T14	10
auto[0]	auto[1]	others[3]	1542	1			T1	2		T9	5		T11	14
auto[0]	auto[1]	interest[1]	967	1			T9	3		T11	12		T14	4
auto[0]	auto[1]	interest[4]	5738	1			T1	2		T9	24		T11	54
auto[0]	auto[1]	interest[64]	2645	1			T1	1		T9	6		T11	39
auto[1]	auto[0]	others[0]	9291	1			T1	97		T9	39		T10	21
auto[1]	auto[0]	others[1]	1493	1			T1	20		T9	3		T10	4
auto[1]	auto[0]	others[2]	1543	1			T1	22		T9	8		T10	2
auto[1]	auto[0]	others[3]	1753	1			T1	19		T9	7		T10	7
auto[1]	auto[0]	interest[1]	1018	1			T1	11		T9	3		T10	2
auto[1]	auto[0]	interest[4]	6150	1			T1	67		T9	27		T10	11
auto[1]	auto[0]	interest[64]	3053	1			T1	32		T9	17		T10	6

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal