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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.10 98.35 94.20 98.61 89.36 97.23 95.82 99.15


Total test records in report: 1100
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1010 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3927702251 Jun 09 12:43:59 PM PDT 24 Jun 09 12:44:02 PM PDT 24 279801152 ps
T1011 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2301867269 Jun 09 12:44:14 PM PDT 24 Jun 09 12:44:20 PM PDT 24 500374078 ps
T1012 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2476722800 Jun 09 12:44:14 PM PDT 24 Jun 09 12:44:15 PM PDT 24 26213905 ps
T1013 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.372060108 Jun 09 12:43:50 PM PDT 24 Jun 09 12:43:51 PM PDT 24 10558484 ps
T1014 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1027821741 Jun 09 12:43:51 PM PDT 24 Jun 09 12:43:55 PM PDT 24 228313267 ps
T1015 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3746948047 Jun 09 12:43:44 PM PDT 24 Jun 09 12:43:45 PM PDT 24 71551418 ps
T95 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4144344089 Jun 09 12:43:48 PM PDT 24 Jun 09 12:43:52 PM PDT 24 2791111077 ps
T1016 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.575898339 Jun 09 12:44:13 PM PDT 24 Jun 09 12:44:17 PM PDT 24 131664797 ps
T1017 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2434556908 Jun 09 12:43:53 PM PDT 24 Jun 09 12:43:54 PM PDT 24 25692766 ps
T1018 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4074350281 Jun 09 12:43:45 PM PDT 24 Jun 09 12:43:45 PM PDT 24 13951379 ps
T1019 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2527531100 Jun 09 12:44:06 PM PDT 24 Jun 09 12:44:07 PM PDT 24 53331405 ps
T1020 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1863684142 Jun 09 12:44:13 PM PDT 24 Jun 09 12:44:14 PM PDT 24 40887311 ps
T1021 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.975412960 Jun 09 12:43:49 PM PDT 24 Jun 09 12:43:50 PM PDT 24 13050384 ps
T1022 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4066108809 Jun 09 12:44:03 PM PDT 24 Jun 09 12:44:07 PM PDT 24 721120487 ps
T1023 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3478408378 Jun 09 12:43:51 PM PDT 24 Jun 09 12:43:52 PM PDT 24 36272616 ps
T1024 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1498541820 Jun 09 12:44:08 PM PDT 24 Jun 09 12:44:11 PM PDT 24 115141582 ps
T1025 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2970549961 Jun 09 12:44:09 PM PDT 24 Jun 09 12:44:12 PM PDT 24 196152940 ps
T1026 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3524726925 Jun 09 12:44:04 PM PDT 24 Jun 09 12:44:06 PM PDT 24 60322599 ps
T1027 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1445398294 Jun 09 12:44:07 PM PDT 24 Jun 09 12:44:11 PM PDT 24 432961044 ps
T1028 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.501016929 Jun 09 12:43:57 PM PDT 24 Jun 09 12:44:02 PM PDT 24 59587103 ps
T1029 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3641343074 Jun 09 12:44:14 PM PDT 24 Jun 09 12:44:16 PM PDT 24 51003332 ps
T237 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3899748162 Jun 09 12:44:15 PM PDT 24 Jun 09 12:44:27 PM PDT 24 193884946 ps
T1030 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3392824550 Jun 09 12:44:12 PM PDT 24 Jun 09 12:44:14 PM PDT 24 68296544 ps
T1031 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1683574446 Jun 09 12:44:09 PM PDT 24 Jun 09 12:44:12 PM PDT 24 192281465 ps
T1032 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3100367331 Jun 09 12:44:14 PM PDT 24 Jun 09 12:44:15 PM PDT 24 42573357 ps
T236 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.312202559 Jun 09 12:44:09 PM PDT 24 Jun 09 12:44:14 PM PDT 24 192536366 ps
T1033 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3266803849 Jun 09 12:44:13 PM PDT 24 Jun 09 12:44:15 PM PDT 24 31718194 ps
T1034 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.183765241 Jun 09 12:43:45 PM PDT 24 Jun 09 12:43:47 PM PDT 24 159303377 ps
T1035 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3591501859 Jun 09 12:44:01 PM PDT 24 Jun 09 12:44:05 PM PDT 24 127302398 ps
T1036 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1825999032 Jun 09 12:43:48 PM PDT 24 Jun 09 12:43:50 PM PDT 24 146081971 ps
T1037 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3886967688 Jun 09 12:44:09 PM PDT 24 Jun 09 12:44:10 PM PDT 24 29244148 ps
T1038 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3659706231 Jun 09 12:44:09 PM PDT 24 Jun 09 12:44:14 PM PDT 24 530615957 ps
T1039 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2259585002 Jun 09 12:44:19 PM PDT 24 Jun 09 12:44:20 PM PDT 24 63752099 ps
T1040 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3863696411 Jun 09 12:44:04 PM PDT 24 Jun 09 12:44:13 PM PDT 24 593538436 ps
T1041 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1348761393 Jun 09 12:43:55 PM PDT 24 Jun 09 12:44:18 PM PDT 24 610265875 ps
T1042 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1051250853 Jun 09 12:43:48 PM PDT 24 Jun 09 12:43:50 PM PDT 24 205557659 ps
T1043 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3371455931 Jun 09 12:44:15 PM PDT 24 Jun 09 12:44:16 PM PDT 24 13025399 ps
T1044 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4049042011 Jun 09 12:44:16 PM PDT 24 Jun 09 12:44:18 PM PDT 24 307905470 ps
T1045 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1055438593 Jun 09 12:43:54 PM PDT 24 Jun 09 12:43:58 PM PDT 24 63830389 ps
T70 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3530692621 Jun 09 12:43:46 PM PDT 24 Jun 09 12:43:48 PM PDT 24 462706134 ps
T1046 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1179966971 Jun 09 12:43:55 PM PDT 24 Jun 09 12:43:57 PM PDT 24 97414562 ps
T1047 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2189484890 Jun 09 12:44:15 PM PDT 24 Jun 09 12:44:16 PM PDT 24 30019404 ps
T1048 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.284754614 Jun 09 12:43:49 PM PDT 24 Jun 09 12:43:50 PM PDT 24 27003898 ps
T1049 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2157282321 Jun 09 12:44:14 PM PDT 24 Jun 09 12:44:16 PM PDT 24 25747536 ps
T1050 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.476997656 Jun 09 12:43:53 PM PDT 24 Jun 09 12:44:08 PM PDT 24 420559176 ps
T1051 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3878217972 Jun 09 12:43:49 PM PDT 24 Jun 09 12:43:51 PM PDT 24 24234785 ps
T242 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1247338960 Jun 09 12:44:15 PM PDT 24 Jun 09 12:44:29 PM PDT 24 1055492231 ps
T1052 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2842426114 Jun 09 12:44:08 PM PDT 24 Jun 09 12:44:13 PM PDT 24 170597988 ps
T1053 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2696127783 Jun 09 12:44:04 PM PDT 24 Jun 09 12:44:05 PM PDT 24 157940097 ps
T1054 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.820921519 Jun 09 12:44:13 PM PDT 24 Jun 09 12:44:15 PM PDT 24 58410794 ps
T238 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2378116212 Jun 09 12:44:06 PM PDT 24 Jun 09 12:44:19 PM PDT 24 4005095013 ps
T1055 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2868172943 Jun 09 12:44:15 PM PDT 24 Jun 09 12:44:16 PM PDT 24 19369493 ps
T1056 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1625745999 Jun 09 12:44:15 PM PDT 24 Jun 09 12:44:18 PM PDT 24 133509820 ps
T1057 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4091056838 Jun 09 12:43:53 PM PDT 24 Jun 09 12:44:32 PM PDT 24 2438091004 ps
T1058 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1899985583 Jun 09 12:43:50 PM PDT 24 Jun 09 12:43:59 PM PDT 24 2020283173 ps
T1059 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1643757369 Jun 09 12:43:51 PM PDT 24 Jun 09 12:43:52 PM PDT 24 32498077 ps
T1060 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2176660522 Jun 09 12:44:15 PM PDT 24 Jun 09 12:44:16 PM PDT 24 37799488 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2115506285 Jun 09 12:43:48 PM PDT 24 Jun 09 12:43:50 PM PDT 24 227470819 ps
T1062 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3270956990 Jun 09 12:44:10 PM PDT 24 Jun 09 12:44:11 PM PDT 24 49959782 ps
T1063 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1847511835 Jun 09 12:43:54 PM PDT 24 Jun 09 12:43:56 PM PDT 24 175886109 ps
T1064 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1809911302 Jun 09 12:43:52 PM PDT 24 Jun 09 12:43:54 PM PDT 24 54267387 ps
T1065 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2717265807 Jun 09 12:43:46 PM PDT 24 Jun 09 12:43:47 PM PDT 24 11359904 ps
T1066 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.526986547 Jun 09 12:44:03 PM PDT 24 Jun 09 12:44:05 PM PDT 24 28422530 ps
T1067 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.126295348 Jun 09 12:44:13 PM PDT 24 Jun 09 12:44:15 PM PDT 24 16280473 ps
T1068 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1630754234 Jun 09 12:44:02 PM PDT 24 Jun 09 12:44:03 PM PDT 24 64340331 ps
T239 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2586102335 Jun 09 12:43:46 PM PDT 24 Jun 09 12:44:09 PM PDT 24 1679907138 ps
T1069 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3190990496 Jun 09 12:44:03 PM PDT 24 Jun 09 12:44:05 PM PDT 24 29014121 ps
T1070 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2133971580 Jun 09 12:44:10 PM PDT 24 Jun 09 12:44:33 PM PDT 24 2361014907 ps
T1071 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.856253160 Jun 09 12:44:16 PM PDT 24 Jun 09 12:44:18 PM PDT 24 155671860 ps
T1072 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2295246945 Jun 09 12:44:18 PM PDT 24 Jun 09 12:44:19 PM PDT 24 30738219 ps
T1073 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.437057102 Jun 09 12:44:10 PM PDT 24 Jun 09 12:44:18 PM PDT 24 228357660 ps
T1074 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1621062012 Jun 09 12:44:08 PM PDT 24 Jun 09 12:44:10 PM PDT 24 50779991 ps
T1075 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2697992860 Jun 09 12:43:54 PM PDT 24 Jun 09 12:43:55 PM PDT 24 37687322 ps
T1076 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4265901580 Jun 09 12:44:06 PM PDT 24 Jun 09 12:44:07 PM PDT 24 22250577 ps
T1077 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.942241945 Jun 09 12:44:09 PM PDT 24 Jun 09 12:44:13 PM PDT 24 89908278 ps
T1078 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.832036968 Jun 09 12:44:03 PM PDT 24 Jun 09 12:44:04 PM PDT 24 21483266 ps
T1079 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2891017169 Jun 09 12:43:58 PM PDT 24 Jun 09 12:44:02 PM PDT 24 53691128 ps
T1080 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2041380706 Jun 09 12:44:13 PM PDT 24 Jun 09 12:44:15 PM PDT 24 14364629 ps
T1081 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3284380634 Jun 09 12:43:54 PM PDT 24 Jun 09 12:44:28 PM PDT 24 2167399146 ps
T1082 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.414505769 Jun 09 12:44:09 PM PDT 24 Jun 09 12:44:12 PM PDT 24 83797956 ps
T1083 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2049098810 Jun 09 12:44:13 PM PDT 24 Jun 09 12:44:15 PM PDT 24 17029161 ps
T1084 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4238880390 Jun 09 12:44:19 PM PDT 24 Jun 09 12:44:20 PM PDT 24 50467753 ps
T1085 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2596765258 Jun 09 12:44:17 PM PDT 24 Jun 09 12:44:19 PM PDT 24 147376544 ps
T1086 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3550569387 Jun 09 12:43:43 PM PDT 24 Jun 09 12:43:46 PM PDT 24 80046106 ps
T244 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1491558606 Jun 09 12:44:07 PM PDT 24 Jun 09 12:44:28 PM PDT 24 2074642847 ps
T1087 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.527637601 Jun 09 12:44:08 PM PDT 24 Jun 09 12:44:17 PM PDT 24 402444851 ps
T245 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2507986751 Jun 09 12:44:12 PM PDT 24 Jun 09 12:44:30 PM PDT 24 280092330 ps
T1088 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.509975833 Jun 09 12:43:42 PM PDT 24 Jun 09 12:43:47 PM PDT 24 57255104 ps
T1089 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1797422338 Jun 09 12:43:58 PM PDT 24 Jun 09 12:44:00 PM PDT 24 40422173 ps
T1090 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2119418045 Jun 09 12:44:09 PM PDT 24 Jun 09 12:44:12 PM PDT 24 223995197 ps
T1091 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.234039406 Jun 09 12:43:55 PM PDT 24 Jun 09 12:43:56 PM PDT 24 18179377 ps
T1092 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3146252890 Jun 09 12:43:58 PM PDT 24 Jun 09 12:44:00 PM PDT 24 336525589 ps
T1093 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.392633480 Jun 09 12:43:52 PM PDT 24 Jun 09 12:44:27 PM PDT 24 559570951 ps
T1094 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.536622334 Jun 09 12:43:56 PM PDT 24 Jun 09 12:43:58 PM PDT 24 95058854 ps
T1095 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3286653504 Jun 09 12:43:54 PM PDT 24 Jun 09 12:43:56 PM PDT 24 163481156 ps
T1096 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2002469116 Jun 09 12:44:13 PM PDT 24 Jun 09 12:44:14 PM PDT 24 19251577 ps
T1097 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3571134090 Jun 09 12:44:17 PM PDT 24 Jun 09 12:44:19 PM PDT 24 14938970 ps
T1098 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.272534782 Jun 09 12:44:16 PM PDT 24 Jun 09 12:44:17 PM PDT 24 25371737 ps
T1099 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4035210040 Jun 09 12:43:55 PM PDT 24 Jun 09 12:43:57 PM PDT 24 68331260 ps
T1100 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3836022937 Jun 09 12:44:07 PM PDT 24 Jun 09 12:44:10 PM PDT 24 203606246 ps

Test location /workspace/coverage/default/15.spi_device_stress_all.1661883697
Short name T1
Test name
Test status
Simulation time 151075751377 ps
CPU time 776.36 seconds
Started Jun 09 02:29:48 PM PDT 24
Finished Jun 09 02:42:45 PM PDT 24
Peak memory 272416 kb
Host smart-b2b6696c-5732-45ce-9ddb-d580c42cab3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661883697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1661883697
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3079723251
Short name T11
Test name
Test status
Simulation time 63887047627 ps
CPU time 597.2 seconds
Started Jun 09 02:31:08 PM PDT 24
Finished Jun 09 02:41:06 PM PDT 24
Peak memory 273256 kb
Host smart-d75a1d45-e9f7-4e9e-b419-16b6befcb2ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079723251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3079723251
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3747882862
Short name T100
Test name
Test status
Simulation time 664954704 ps
CPU time 3.75 seconds
Started Jun 09 12:43:45 PM PDT 24
Finished Jun 09 12:43:49 PM PDT 24
Peak memory 217508 kb
Host smart-1a0e46bd-c690-44fa-a86a-cf55b30a41ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747882862 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3747882862
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3448276720
Short name T34
Test name
Test status
Simulation time 111267824356 ps
CPU time 884.08 seconds
Started Jun 09 02:29:49 PM PDT 24
Finished Jun 09 02:44:34 PM PDT 24
Peak memory 289652 kb
Host smart-7bd368b0-f388-4955-9d78-74064dd21041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448276720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3448276720
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.4090059653
Short name T57
Test name
Test status
Simulation time 17191155 ps
CPU time 0.76 seconds
Started Jun 09 02:28:50 PM PDT 24
Finished Jun 09 02:28:51 PM PDT 24
Peak memory 215940 kb
Host smart-a2760824-220a-40c7-a455-c22db16f7592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090059653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.4090059653
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1819782233
Short name T33
Test name
Test status
Simulation time 11713094465 ps
CPU time 177.91 seconds
Started Jun 09 02:30:04 PM PDT 24
Finished Jun 09 02:33:02 PM PDT 24
Peak memory 256768 kb
Host smart-1db9880f-5e31-4e91-8ac7-42aae2bce98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819782233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1819782233
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1590275686
Short name T35
Test name
Test status
Simulation time 117783935006 ps
CPU time 292.77 seconds
Started Jun 09 02:30:07 PM PDT 24
Finished Jun 09 02:35:00 PM PDT 24
Peak memory 251396 kb
Host smart-46173873-d30c-47c2-a62b-f15b23ca7e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590275686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1590275686
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3825963809
Short name T58
Test name
Test status
Simulation time 32990548 ps
CPU time 0.98 seconds
Started Jun 09 02:28:49 PM PDT 24
Finished Jun 09 02:28:50 PM PDT 24
Peak memory 235392 kb
Host smart-a89452b3-de04-4d80-874f-e80ab0a5d476
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825963809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3825963809
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2083897624
Short name T149
Test name
Test status
Simulation time 11031175000 ps
CPU time 181.9 seconds
Started Jun 09 02:30:41 PM PDT 24
Finished Jun 09 02:33:44 PM PDT 24
Peak memory 273400 kb
Host smart-d431d682-6daf-42a6-86c9-63d02ed344ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083897624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2083897624
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1291526346
Short name T180
Test name
Test status
Simulation time 9025511167 ps
CPU time 123.58 seconds
Started Jun 09 02:30:45 PM PDT 24
Finished Jun 09 02:32:49 PM PDT 24
Peak memory 265424 kb
Host smart-3d708b5e-cc7a-4bca-ab72-16f920d0154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291526346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1291526346
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1113035096
Short name T39
Test name
Test status
Simulation time 470393495 ps
CPU time 6.34 seconds
Started Jun 09 02:30:48 PM PDT 24
Finished Jun 09 02:30:55 PM PDT 24
Peak memory 224332 kb
Host smart-b1d39a43-df06-4e70-ae1c-a34acdb3f8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113035096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1113035096
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2712657037
Short name T143
Test name
Test status
Simulation time 198874675488 ps
CPU time 503.13 seconds
Started Jun 09 02:30:45 PM PDT 24
Finished Jun 09 02:39:09 PM PDT 24
Peak memory 272672 kb
Host smart-7d494b22-2aee-415d-b946-364e048d11be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712657037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2712657037
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1981113172
Short name T240
Test name
Test status
Simulation time 291677237 ps
CPU time 18.61 seconds
Started Jun 09 12:44:15 PM PDT 24
Finished Jun 09 12:44:34 PM PDT 24
Peak memory 216020 kb
Host smart-e14e0909-e2d0-4d36-9591-3c8b00e4d21b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981113172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1981113172
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1320673327
Short name T104
Test name
Test status
Simulation time 67228674 ps
CPU time 1.87 seconds
Started Jun 09 12:44:11 PM PDT 24
Finished Jun 09 12:44:13 PM PDT 24
Peak memory 207556 kb
Host smart-88b583de-9abf-484e-8401-cb345a68b777
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320673327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1320673327
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1161236329
Short name T153
Test name
Test status
Simulation time 48986005257 ps
CPU time 351.4 seconds
Started Jun 09 02:30:24 PM PDT 24
Finished Jun 09 02:36:16 PM PDT 24
Peak memory 254928 kb
Host smart-ec64fb5e-0dff-4a40-9252-b917efc72d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161236329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1161236329
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2107258541
Short name T161
Test name
Test status
Simulation time 113043125237 ps
CPU time 424.23 seconds
Started Jun 09 02:30:56 PM PDT 24
Finished Jun 09 02:38:01 PM PDT 24
Peak memory 255136 kb
Host smart-9b5e78a7-6908-411e-8001-ffc7e353322f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107258541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2107258541
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2443960712
Short name T92
Test name
Test status
Simulation time 142101340 ps
CPU time 5.1 seconds
Started Jun 09 12:44:15 PM PDT 24
Finished Jun 09 12:44:21 PM PDT 24
Peak memory 215820 kb
Host smart-43994d55-71c9-405b-b1e9-7869d6d5a825
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443960712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2443960712
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2085285396
Short name T49
Test name
Test status
Simulation time 15100754 ps
CPU time 1.01 seconds
Started Jun 09 02:29:24 PM PDT 24
Finished Jun 09 02:29:25 PM PDT 24
Peak memory 217604 kb
Host smart-5e4ad78c-27e3-47fb-bbc6-99691a294681
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085285396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2085285396
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2898735694
Short name T216
Test name
Test status
Simulation time 8357979452 ps
CPU time 52.43 seconds
Started Jun 09 02:30:47 PM PDT 24
Finished Jun 09 02:31:40 PM PDT 24
Peak memory 248948 kb
Host smart-db26d135-7d29-448c-8e7b-80190408a334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898735694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2898735694
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1078376080
Short name T188
Test name
Test status
Simulation time 62881108841 ps
CPU time 648.14 seconds
Started Jun 09 02:29:59 PM PDT 24
Finished Jun 09 02:40:48 PM PDT 24
Peak memory 273616 kb
Host smart-02a8b9a4-d615-4a55-980a-9fca66cc2c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078376080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1078376080
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2035487636
Short name T201
Test name
Test status
Simulation time 21304258011 ps
CPU time 136.83 seconds
Started Jun 09 02:30:52 PM PDT 24
Finished Jun 09 02:33:09 PM PDT 24
Peak memory 267516 kb
Host smart-02bbc1fa-31f6-4117-bcfd-42da0c397fad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035487636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2035487636
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2888518601
Short name T208
Test name
Test status
Simulation time 111047287206 ps
CPU time 304.76 seconds
Started Jun 09 02:29:53 PM PDT 24
Finished Jun 09 02:34:58 PM PDT 24
Peak memory 257216 kb
Host smart-600741ac-cf22-45bc-9c51-737705e22567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888518601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2888518601
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2855972232
Short name T207
Test name
Test status
Simulation time 270212115690 ps
CPU time 611.6 seconds
Started Jun 09 02:29:17 PM PDT 24
Finished Jun 09 02:39:29 PM PDT 24
Peak memory 252480 kb
Host smart-c0ce9f20-a759-493e-9d34-979df7ed9966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855972232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2855972232
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2563511525
Short name T151
Test name
Test status
Simulation time 55432913413 ps
CPU time 121.3 seconds
Started Jun 09 02:30:15 PM PDT 24
Finished Jun 09 02:32:16 PM PDT 24
Peak memory 271276 kb
Host smart-1bb4789a-169a-4037-909b-c29a2e6430ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563511525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2563511525
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.784098923
Short name T145
Test name
Test status
Simulation time 115938076749 ps
CPU time 575.24 seconds
Started Jun 09 02:30:20 PM PDT 24
Finished Jun 09 02:39:55 PM PDT 24
Peak memory 249484 kb
Host smart-5c9af42c-24b7-4b7f-b2c9-78e9b55f36ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784098923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.784098923
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3019930370
Short name T55
Test name
Test status
Simulation time 16770223 ps
CPU time 0.73 seconds
Started Jun 09 02:29:31 PM PDT 24
Finished Jun 09 02:29:32 PM PDT 24
Peak memory 204512 kb
Host smart-e9e592f0-6c2c-4f61-8d8d-df94bc329b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019930370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3019930370
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2586102335
Short name T239
Test name
Test status
Simulation time 1679907138 ps
CPU time 23.18 seconds
Started Jun 09 12:43:46 PM PDT 24
Finished Jun 09 12:44:09 PM PDT 24
Peak memory 215800 kb
Host smart-1e671ea1-8896-4106-b122-6c954d384227
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586102335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2586102335
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2477505389
Short name T205
Test name
Test status
Simulation time 35141942972 ps
CPU time 126.15 seconds
Started Jun 09 02:29:39 PM PDT 24
Finished Jun 09 02:31:45 PM PDT 24
Peak memory 269624 kb
Host smart-3f1d2779-22e0-47ff-90ef-882933eec90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477505389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2477505389
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.601296853
Short name T219
Test name
Test status
Simulation time 61213615367 ps
CPU time 297.48 seconds
Started Jun 09 02:30:34 PM PDT 24
Finished Jun 09 02:35:32 PM PDT 24
Peak memory 249040 kb
Host smart-7a223af6-bfc1-42eb-a8e3-a7e54853e900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601296853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.601296853
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1753441605
Short name T85
Test name
Test status
Simulation time 147673149 ps
CPU time 4.55 seconds
Started Jun 09 12:43:43 PM PDT 24
Finished Jun 09 12:43:48 PM PDT 24
Peak memory 216096 kb
Host smart-af517136-0547-450c-9e58-8d0d2a37e65c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753441605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
753441605
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.222092447
Short name T181
Test name
Test status
Simulation time 4582067736 ps
CPU time 97.2 seconds
Started Jun 09 02:29:03 PM PDT 24
Finished Jun 09 02:30:40 PM PDT 24
Peak memory 267028 kb
Host smart-74a439df-12df-4d47-a0e2-34cddc1e8fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222092447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.222092447
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2244182735
Short name T893
Test name
Test status
Simulation time 32869956831 ps
CPU time 193.24 seconds
Started Jun 09 02:29:53 PM PDT 24
Finished Jun 09 02:33:07 PM PDT 24
Peak memory 264740 kb
Host smart-b16ea9d6-6d4d-40fc-b0c2-116803a8dd5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244182735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2244182735
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1240258547
Short name T66
Test name
Test status
Simulation time 50984144325 ps
CPU time 470.8 seconds
Started Jun 09 02:29:55 PM PDT 24
Finished Jun 09 02:37:46 PM PDT 24
Peak memory 289844 kb
Host smart-c919e8de-a39d-4fcf-a91a-7edda5037537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240258547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1240258547
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1701537498
Short name T142
Test name
Test status
Simulation time 54285498731 ps
CPU time 121.78 seconds
Started Jun 09 02:30:23 PM PDT 24
Finished Jun 09 02:32:25 PM PDT 24
Peak memory 254476 kb
Host smart-bb1fd69c-4036-4f91-b7be-357fe5cdfba1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701537498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1701537498
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2033271899
Short name T42
Test name
Test status
Simulation time 15786625414 ps
CPU time 106.21 seconds
Started Jun 09 02:29:00 PM PDT 24
Finished Jun 09 02:30:47 PM PDT 24
Peak memory 236676 kb
Host smart-6b1b0de3-1113-46bd-a36b-16facf5697f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033271899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2033271899
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.938638166
Short name T62
Test name
Test status
Simulation time 73959776123 ps
CPU time 19.44 seconds
Started Jun 09 02:29:31 PM PDT 24
Finished Jun 09 02:29:51 PM PDT 24
Peak memory 240728 kb
Host smart-4b2ffea8-28c4-429e-8596-5348abc7129f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938638166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.938638166
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.312202559
Short name T236
Test name
Test status
Simulation time 192536366 ps
CPU time 4.68 seconds
Started Jun 09 12:44:09 PM PDT 24
Finished Jun 09 12:44:14 PM PDT 24
Peak memory 215876 kb
Host smart-31021ef0-72cb-44b6-87dd-11eabb4ef3ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312202559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.312202559
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2133971580
Short name T1070
Test name
Test status
Simulation time 2361014907 ps
CPU time 22.86 seconds
Started Jun 09 12:44:10 PM PDT 24
Finished Jun 09 12:44:33 PM PDT 24
Peak memory 215928 kb
Host smart-f4872ce3-4e1e-405e-9d1f-a74576d0757f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133971580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2133971580
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1085000465
Short name T171
Test name
Test status
Simulation time 10568083309 ps
CPU time 159.95 seconds
Started Jun 09 02:29:51 PM PDT 24
Finished Jun 09 02:32:31 PM PDT 24
Peak memory 260300 kb
Host smart-c13aa1e1-c6f1-46b8-83f0-e7fd130a65f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085000465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1085000465
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.195344699
Short name T286
Test name
Test status
Simulation time 3310332270 ps
CPU time 16.34 seconds
Started Jun 09 02:29:58 PM PDT 24
Finished Jun 09 02:30:15 PM PDT 24
Peak memory 224408 kb
Host smart-85f18a50-5baf-4d47-9c83-4795b4ca530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195344699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.195344699
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.645928867
Short name T209
Test name
Test status
Simulation time 178546028819 ps
CPU time 400.28 seconds
Started Jun 09 02:30:33 PM PDT 24
Finished Jun 09 02:37:14 PM PDT 24
Peak memory 263836 kb
Host smart-8164aa61-f35e-4798-b69e-d027f3207d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645928867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.645928867
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3834504167
Short name T77
Test name
Test status
Simulation time 7406718082 ps
CPU time 44.17 seconds
Started Jun 09 02:30:05 PM PDT 24
Finished Jun 09 02:30:49 PM PDT 24
Peak memory 224364 kb
Host smart-bb78f155-1a0a-4881-a912-10f11db7b471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834504167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3834504167
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.29305216
Short name T19
Test name
Test status
Simulation time 41417038283 ps
CPU time 278 seconds
Started Jun 09 02:29:30 PM PDT 24
Finished Jun 09 02:34:08 PM PDT 24
Peak memory 256004 kb
Host smart-704585b9-9c62-4219-b713-58c323ccff25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29305216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.29305216
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4207518622
Short name T251
Test name
Test status
Simulation time 5304533786 ps
CPU time 51.61 seconds
Started Jun 09 02:29:03 PM PDT 24
Finished Jun 09 02:29:55 PM PDT 24
Peak memory 236384 kb
Host smart-973451d8-26e2-4a72-9365-3b2ac7311cf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207518622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4207518622
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2412168238
Short name T285
Test name
Test status
Simulation time 680626979 ps
CPU time 6.43 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:36 PM PDT 24
Peak memory 233576 kb
Host smart-5fb28e5f-8984-472e-bdd2-e4b9f2036cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412168238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2412168238
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3504293732
Short name T281
Test name
Test status
Simulation time 1707580141 ps
CPU time 17.17 seconds
Started Jun 09 02:29:32 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 221888 kb
Host smart-d8647d02-cf5f-462c-86b9-3f1472cf9d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504293732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3504293732
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3061178465
Short name T210
Test name
Test status
Simulation time 142195932402 ps
CPU time 335.71 seconds
Started Jun 09 02:29:06 PM PDT 24
Finished Jun 09 02:34:42 PM PDT 24
Peak memory 252388 kb
Host smart-ecf33b46-5075-4e04-be75-40326ce42442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061178465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3061178465
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2388512519
Short name T234
Test name
Test status
Simulation time 12582617595 ps
CPU time 27.5 seconds
Started Jun 09 02:30:02 PM PDT 24
Finished Jun 09 02:30:29 PM PDT 24
Peak memory 256704 kb
Host smart-32b46060-633b-4639-b3e2-3879978a89d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388512519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2388512519
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2492020832
Short name T204
Test name
Test status
Simulation time 76952967239 ps
CPU time 213.02 seconds
Started Jun 09 02:30:53 PM PDT 24
Finished Jun 09 02:34:27 PM PDT 24
Peak memory 250036 kb
Host smart-4b9cf501-671a-449e-8291-68f110b4c05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492020832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2492020832
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3530692621
Short name T70
Test name
Test status
Simulation time 462706134 ps
CPU time 1.49 seconds
Started Jun 09 12:43:46 PM PDT 24
Finished Jun 09 12:43:48 PM PDT 24
Peak memory 207524 kb
Host smart-543bbeec-bce2-413a-a1aa-2a3572b6867e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530692621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3530692621
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2302382540
Short name T88
Test name
Test status
Simulation time 219916658 ps
CPU time 4.93 seconds
Started Jun 09 12:44:06 PM PDT 24
Finished Jun 09 12:44:11 PM PDT 24
Peak memory 215944 kb
Host smart-d7dd8a53-b0b2-49ab-8b17-0d91c994988f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302382540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2302382540
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2807411134
Short name T302
Test name
Test status
Simulation time 298740776 ps
CPU time 0.84 seconds
Started Jun 09 02:29:20 PM PDT 24
Finished Jun 09 02:29:22 PM PDT 24
Peak memory 206220 kb
Host smart-dfc81bfc-4b8b-4355-81eb-bc85478a7e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807411134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2807411134
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.815535549
Short name T80
Test name
Test status
Simulation time 493482228 ps
CPU time 8.78 seconds
Started Jun 09 02:29:48 PM PDT 24
Finished Jun 09 02:29:57 PM PDT 24
Peak memory 232496 kb
Host smart-16961dd0-409b-4a43-9bc7-126a2d61335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815535549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.815535549
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.332081540
Short name T113
Test name
Test status
Simulation time 316103899 ps
CPU time 21.71 seconds
Started Jun 09 12:43:44 PM PDT 24
Finished Jun 09 12:44:06 PM PDT 24
Peak memory 207592 kb
Host smart-49a4d89a-6864-487e-927d-b0a1f495ebfd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332081540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.332081540
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3738711059
Short name T114
Test name
Test status
Simulation time 1851355662 ps
CPU time 26.6 seconds
Started Jun 09 12:43:46 PM PDT 24
Finished Jun 09 12:44:13 PM PDT 24
Peak memory 207616 kb
Host smart-8db34e12-63df-4d3c-bacd-a6c3cee8613d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738711059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3738711059
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.182266676
Short name T109
Test name
Test status
Simulation time 103283061 ps
CPU time 1.87 seconds
Started Jun 09 12:43:42 PM PDT 24
Finished Jun 09 12:43:44 PM PDT 24
Peak memory 207600 kb
Host smart-3c24124a-7004-4e44-ae81-78a04d63e3d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182266676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.182266676
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3746948047
Short name T1015
Test name
Test status
Simulation time 71551418 ps
CPU time 0.76 seconds
Started Jun 09 12:43:44 PM PDT 24
Finished Jun 09 12:43:45 PM PDT 24
Peak memory 204080 kb
Host smart-24e98d40-00ab-46f2-b0be-51a350078c9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746948047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
746948047
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3550569387
Short name T1086
Test name
Test status
Simulation time 80046106 ps
CPU time 1.96 seconds
Started Jun 09 12:43:43 PM PDT 24
Finished Jun 09 12:43:46 PM PDT 24
Peak memory 215792 kb
Host smart-591519f5-2844-4c9b-94da-55448b80f361
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550569387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3550569387
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4074350281
Short name T1018
Test name
Test status
Simulation time 13951379 ps
CPU time 0.69 seconds
Started Jun 09 12:43:45 PM PDT 24
Finished Jun 09 12:43:45 PM PDT 24
Peak memory 204332 kb
Host smart-730290b6-0ecf-49d2-bd30-cd7402c1b248
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074350281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.4074350281
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.201488053
Short name T982
Test name
Test status
Simulation time 44734375 ps
CPU time 2.84 seconds
Started Jun 09 12:43:45 PM PDT 24
Finished Jun 09 12:43:49 PM PDT 24
Peak memory 215752 kb
Host smart-2aec3710-4427-4b09-91f3-24afa91ddba3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201488053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.201488053
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1899985583
Short name T1058
Test name
Test status
Simulation time 2020283173 ps
CPU time 8.43 seconds
Started Jun 09 12:43:50 PM PDT 24
Finished Jun 09 12:43:59 PM PDT 24
Peak memory 207592 kb
Host smart-8b0975d3-eb78-46ae-8d19-2332f8528b62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899985583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1899985583
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3284380634
Short name T1081
Test name
Test status
Simulation time 2167399146 ps
CPU time 33.55 seconds
Started Jun 09 12:43:54 PM PDT 24
Finished Jun 09 12:44:28 PM PDT 24
Peak memory 207500 kb
Host smart-6b989d2e-1f08-4b9f-bcd7-5aff3e3e0395
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284380634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3284380634
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3052042765
Short name T68
Test name
Test status
Simulation time 216241355 ps
CPU time 1.21 seconds
Started Jun 09 12:43:44 PM PDT 24
Finished Jun 09 12:43:46 PM PDT 24
Peak memory 207592 kb
Host smart-c1ff2480-5db5-4b6f-b38c-909801750125
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052042765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3052042765
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2100646224
Short name T1001
Test name
Test status
Simulation time 205356660 ps
CPU time 1.79 seconds
Started Jun 09 12:43:48 PM PDT 24
Finished Jun 09 12:43:51 PM PDT 24
Peak memory 215904 kb
Host smart-4d787b2f-a5a9-4005-a897-04442cfb68ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100646224 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2100646224
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2800521860
Short name T110
Test name
Test status
Simulation time 28955225 ps
CPU time 1.93 seconds
Started Jun 09 12:43:47 PM PDT 24
Finished Jun 09 12:43:49 PM PDT 24
Peak memory 207556 kb
Host smart-800f3075-c423-4a74-a86f-abffdc38a720
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800521860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
800521860
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.247675207
Short name T1007
Test name
Test status
Simulation time 21860989 ps
CPU time 0.76 seconds
Started Jun 09 12:43:44 PM PDT 24
Finished Jun 09 12:43:45 PM PDT 24
Peak memory 204104 kb
Host smart-7d1184ec-8d3c-4a93-b207-f82f60c8118a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247675207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.247675207
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.183765241
Short name T1034
Test name
Test status
Simulation time 159303377 ps
CPU time 1.96 seconds
Started Jun 09 12:43:45 PM PDT 24
Finished Jun 09 12:43:47 PM PDT 24
Peak memory 215856 kb
Host smart-4c217907-7d5a-4aa4-906d-01c24228000c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183765241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.183765241
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2717265807
Short name T1065
Test name
Test status
Simulation time 11359904 ps
CPU time 0.68 seconds
Started Jun 09 12:43:46 PM PDT 24
Finished Jun 09 12:43:47 PM PDT 24
Peak memory 204052 kb
Host smart-ed470d7d-4748-4f14-b386-66828a8230c4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717265807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2717265807
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2115506285
Short name T1061
Test name
Test status
Simulation time 227470819 ps
CPU time 1.98 seconds
Started Jun 09 12:43:48 PM PDT 24
Finished Jun 09 12:43:50 PM PDT 24
Peak memory 215832 kb
Host smart-41ce5a62-bbd0-4d1a-9b05-3bbd7a6ee4ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115506285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2115506285
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.509975833
Short name T1088
Test name
Test status
Simulation time 57255104 ps
CPU time 3.73 seconds
Started Jun 09 12:43:42 PM PDT 24
Finished Jun 09 12:43:47 PM PDT 24
Peak memory 215848 kb
Host smart-6eae247c-0408-46cc-ac89-88943b2c7079
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509975833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.509975833
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.620425670
Short name T87
Test name
Test status
Simulation time 421007712 ps
CPU time 7.74 seconds
Started Jun 09 12:43:46 PM PDT 24
Finished Jun 09 12:43:55 PM PDT 24
Peak memory 215820 kb
Host smart-08805e90-d486-485c-bdb4-460cb8e74e0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620425670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.620425670
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1683574446
Short name T1031
Test name
Test status
Simulation time 192281465 ps
CPU time 2.44 seconds
Started Jun 09 12:44:09 PM PDT 24
Finished Jun 09 12:44:12 PM PDT 24
Peak memory 216944 kb
Host smart-daef258c-a6f9-4d2a-b0d7-6df2cda317a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683574446 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1683574446
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3836022937
Short name T1100
Test name
Test status
Simulation time 203606246 ps
CPU time 2.75 seconds
Started Jun 09 12:44:07 PM PDT 24
Finished Jun 09 12:44:10 PM PDT 24
Peak memory 215704 kb
Host smart-fb563330-9552-4507-b839-9858b1c1dfbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836022937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3836022937
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2696127783
Short name T1053
Test name
Test status
Simulation time 157940097 ps
CPU time 0.69 seconds
Started Jun 09 12:44:04 PM PDT 24
Finished Jun 09 12:44:05 PM PDT 24
Peak memory 204048 kb
Host smart-41d03d15-8ef8-4645-913c-2fb0c060607a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696127783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2696127783
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.877684574
Short name T128
Test name
Test status
Simulation time 53782668 ps
CPU time 1.95 seconds
Started Jun 09 12:44:10 PM PDT 24
Finished Jun 09 12:44:12 PM PDT 24
Peak memory 207628 kb
Host smart-c6f54408-c153-4a67-9e21-061d99ba3210
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877684574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.877684574
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1247338960
Short name T242
Test name
Test status
Simulation time 1055492231 ps
CPU time 13.84 seconds
Started Jun 09 12:44:15 PM PDT 24
Finished Jun 09 12:44:29 PM PDT 24
Peak memory 215840 kb
Host smart-f6476d20-ba85-4704-b8b0-b04b34f2f426
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247338960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1247338960
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3489176374
Short name T93
Test name
Test status
Simulation time 106845165 ps
CPU time 4.76 seconds
Started Jun 09 12:44:04 PM PDT 24
Finished Jun 09 12:44:09 PM PDT 24
Peak memory 218740 kb
Host smart-79f898f4-735f-466f-ab4a-b632dce40c52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489176374 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3489176374
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1630754234
Short name T1068
Test name
Test status
Simulation time 64340331 ps
CPU time 1.3 seconds
Started Jun 09 12:44:02 PM PDT 24
Finished Jun 09 12:44:03 PM PDT 24
Peak memory 207496 kb
Host smart-d921328f-7742-414b-b6a8-33d3b03cfa12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630754234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1630754234
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.526986547
Short name T1066
Test name
Test status
Simulation time 28422530 ps
CPU time 0.71 seconds
Started Jun 09 12:44:03 PM PDT 24
Finished Jun 09 12:44:05 PM PDT 24
Peak memory 204008 kb
Host smart-7e0123d2-19a8-48e0-a117-3f1a99779166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526986547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.526986547
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3180728131
Short name T1009
Test name
Test status
Simulation time 223991057 ps
CPU time 2.57 seconds
Started Jun 09 12:44:03 PM PDT 24
Finished Jun 09 12:44:06 PM PDT 24
Peak memory 215772 kb
Host smart-a5de8ad1-59ee-4b76-8ab7-f746cb1ee938
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180728131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3180728131
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3524726925
Short name T1026
Test name
Test status
Simulation time 60322599 ps
CPU time 1.8 seconds
Started Jun 09 12:44:04 PM PDT 24
Finished Jun 09 12:44:06 PM PDT 24
Peak memory 215844 kb
Host smart-d65e580b-077a-4f59-bb48-49a1b3450c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524726925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3524726925
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3863696411
Short name T1040
Test name
Test status
Simulation time 593538436 ps
CPU time 8.52 seconds
Started Jun 09 12:44:04 PM PDT 24
Finished Jun 09 12:44:13 PM PDT 24
Peak memory 215756 kb
Host smart-db48a4d0-751e-4edd-a784-41a47c6dad5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863696411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3863696411
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2997210212
Short name T83
Test name
Test status
Simulation time 943809630 ps
CPU time 1.73 seconds
Started Jun 09 12:44:08 PM PDT 24
Finished Jun 09 12:44:10 PM PDT 24
Peak memory 215888 kb
Host smart-9b41853e-a5a8-4947-9724-125f79baf86b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997210212 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2997210212
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2119418045
Short name T1090
Test name
Test status
Simulation time 223995197 ps
CPU time 2.41 seconds
Started Jun 09 12:44:09 PM PDT 24
Finished Jun 09 12:44:12 PM PDT 24
Peak memory 215752 kb
Host smart-9978ffd5-563d-440f-b3a4-2c9786ddea29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119418045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2119418045
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3608531072
Short name T978
Test name
Test status
Simulation time 39818495 ps
CPU time 0.71 seconds
Started Jun 09 12:44:04 PM PDT 24
Finished Jun 09 12:44:05 PM PDT 24
Peak memory 204024 kb
Host smart-1c89e6bb-3dca-44d7-b1a6-d68c8a0f149d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608531072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3608531072
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1445398294
Short name T1027
Test name
Test status
Simulation time 432961044 ps
CPU time 3.03 seconds
Started Jun 09 12:44:07 PM PDT 24
Finished Jun 09 12:44:11 PM PDT 24
Peak memory 215748 kb
Host smart-e3bcfe78-5b95-4dd4-b315-c774582e438a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445398294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1445398294
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2509520484
Short name T1004
Test name
Test status
Simulation time 230022272 ps
CPU time 6.99 seconds
Started Jun 09 12:44:04 PM PDT 24
Finished Jun 09 12:44:12 PM PDT 24
Peak memory 216440 kb
Host smart-10c7f31c-ede8-4673-bde7-fc7743718a19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509520484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2509520484
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.414505769
Short name T1082
Test name
Test status
Simulation time 83797956 ps
CPU time 2.84 seconds
Started Jun 09 12:44:09 PM PDT 24
Finished Jun 09 12:44:12 PM PDT 24
Peak memory 217460 kb
Host smart-34a9d72f-1f96-4a12-b767-a3a2523f8969
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414505769 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.414505769
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1621062012
Short name T1074
Test name
Test status
Simulation time 50779991 ps
CPU time 1.54 seconds
Started Jun 09 12:44:08 PM PDT 24
Finished Jun 09 12:44:10 PM PDT 24
Peak memory 207604 kb
Host smart-5341739d-8543-43ce-accc-9269c3da36fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621062012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1621062012
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2291103556
Short name T991
Test name
Test status
Simulation time 18278588 ps
CPU time 0.74 seconds
Started Jun 09 12:44:14 PM PDT 24
Finished Jun 09 12:44:16 PM PDT 24
Peak memory 204120 kb
Host smart-c1a00d11-6361-4491-94a3-12d9bff2baaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291103556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2291103556
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2026985288
Short name T993
Test name
Test status
Simulation time 146033225 ps
CPU time 3.06 seconds
Started Jun 09 12:44:13 PM PDT 24
Finished Jun 09 12:44:17 PM PDT 24
Peak memory 215628 kb
Host smart-961afce4-22bb-47ca-a793-57942cd84c84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026985288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2026985288
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2301867269
Short name T1011
Test name
Test status
Simulation time 500374078 ps
CPU time 5.95 seconds
Started Jun 09 12:44:14 PM PDT 24
Finished Jun 09 12:44:20 PM PDT 24
Peak memory 215820 kb
Host smart-fa94bb08-4b86-406d-8ae3-e0d67a829a00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301867269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2301867269
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.437057102
Short name T1073
Test name
Test status
Simulation time 228357660 ps
CPU time 7.58 seconds
Started Jun 09 12:44:10 PM PDT 24
Finished Jun 09 12:44:18 PM PDT 24
Peak memory 215716 kb
Host smart-829a6877-55fb-4862-a5ef-bf0fbf87a148
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437057102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.437057102
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4198561952
Short name T998
Test name
Test status
Simulation time 157342353 ps
CPU time 3.07 seconds
Started Jun 09 12:44:14 PM PDT 24
Finished Jun 09 12:44:18 PM PDT 24
Peak memory 217300 kb
Host smart-0dca4be0-8b94-4527-affb-2e0d6da4473c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198561952 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4198561952
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3361626945
Short name T992
Test name
Test status
Simulation time 17137242 ps
CPU time 0.76 seconds
Started Jun 09 12:44:16 PM PDT 24
Finished Jun 09 12:44:17 PM PDT 24
Peak memory 204120 kb
Host smart-47c21273-21f7-40d6-be79-26123bb285ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361626945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3361626945
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1498541820
Short name T1024
Test name
Test status
Simulation time 115141582 ps
CPU time 3.05 seconds
Started Jun 09 12:44:08 PM PDT 24
Finished Jun 09 12:44:11 PM PDT 24
Peak memory 215828 kb
Host smart-97d8e95b-ab0c-46e9-845e-31bfdef62588
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498541820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1498541820
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3432615284
Short name T99
Test name
Test status
Simulation time 360224526 ps
CPU time 1.86 seconds
Started Jun 09 12:44:08 PM PDT 24
Finished Jun 09 12:44:10 PM PDT 24
Peak memory 216096 kb
Host smart-bc242501-00a0-4d89-b2b5-f2fc74e09150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432615284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3432615284
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.229108658
Short name T89
Test name
Test status
Simulation time 2236804021 ps
CPU time 14.55 seconds
Started Jun 09 12:44:10 PM PDT 24
Finished Jun 09 12:44:25 PM PDT 24
Peak memory 216192 kb
Host smart-d5baffc1-0389-44bd-807a-9f611a96b3bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229108658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.229108658
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2842426114
Short name T1052
Test name
Test status
Simulation time 170597988 ps
CPU time 3.99 seconds
Started Jun 09 12:44:08 PM PDT 24
Finished Jun 09 12:44:13 PM PDT 24
Peak memory 217704 kb
Host smart-37fd237f-1770-45fa-95c8-4aa5934fdbb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842426114 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2842426114
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3309892419
Short name T107
Test name
Test status
Simulation time 340596143 ps
CPU time 1.99 seconds
Started Jun 09 12:44:15 PM PDT 24
Finished Jun 09 12:44:18 PM PDT 24
Peak memory 215800 kb
Host smart-a6693990-473c-487a-ad0f-c5726cb9cc8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309892419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3309892419
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4091125982
Short name T999
Test name
Test status
Simulation time 91908523 ps
CPU time 0.73 seconds
Started Jun 09 12:44:09 PM PDT 24
Finished Jun 09 12:44:11 PM PDT 24
Peak memory 204044 kb
Host smart-24a19d32-db27-4085-b033-8d2eb6294718
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091125982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
4091125982
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3659706231
Short name T1038
Test name
Test status
Simulation time 530615957 ps
CPU time 3.75 seconds
Started Jun 09 12:44:09 PM PDT 24
Finished Jun 09 12:44:14 PM PDT 24
Peak memory 215800 kb
Host smart-e740fc08-78fb-4f51-8625-300a9b7aa805
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659706231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3659706231
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.942241945
Short name T1077
Test name
Test status
Simulation time 89908278 ps
CPU time 3.24 seconds
Started Jun 09 12:44:09 PM PDT 24
Finished Jun 09 12:44:13 PM PDT 24
Peak memory 215944 kb
Host smart-24c35bb9-fc93-4e80-b4f1-e1c702ac8d47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942241945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.942241945
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3899748162
Short name T237
Test name
Test status
Simulation time 193884946 ps
CPU time 11.51 seconds
Started Jun 09 12:44:15 PM PDT 24
Finished Jun 09 12:44:27 PM PDT 24
Peak memory 215780 kb
Host smart-086b191a-6609-4186-bbac-4ba11e4149d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899748162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3899748162
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2157282321
Short name T1049
Test name
Test status
Simulation time 25747536 ps
CPU time 1.67 seconds
Started Jun 09 12:44:14 PM PDT 24
Finished Jun 09 12:44:16 PM PDT 24
Peak memory 215948 kb
Host smart-4de5fb62-23d0-48fc-8495-8005f586ecc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157282321 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2157282321
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3496467839
Short name T105
Test name
Test status
Simulation time 39024534 ps
CPU time 2.48 seconds
Started Jun 09 12:44:14 PM PDT 24
Finished Jun 09 12:44:17 PM PDT 24
Peak memory 207604 kb
Host smart-8d1ea57a-8ae4-4006-96bd-ad71ac932593
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496467839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3496467839
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3403833412
Short name T979
Test name
Test status
Simulation time 44384631 ps
CPU time 0.71 seconds
Started Jun 09 12:44:09 PM PDT 24
Finished Jun 09 12:44:11 PM PDT 24
Peak memory 203960 kb
Host smart-7436b3a0-0851-4491-8c5f-b2863be23ac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403833412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3403833412
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4049042011
Short name T1044
Test name
Test status
Simulation time 307905470 ps
CPU time 1.86 seconds
Started Jun 09 12:44:16 PM PDT 24
Finished Jun 09 12:44:18 PM PDT 24
Peak memory 215824 kb
Host smart-4b27105b-3fdd-4c85-b1df-9fb102f47642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049042011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4049042011
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.527637601
Short name T1087
Test name
Test status
Simulation time 402444851 ps
CPU time 8.59 seconds
Started Jun 09 12:44:08 PM PDT 24
Finished Jun 09 12:44:17 PM PDT 24
Peak memory 215828 kb
Host smart-a4cd7846-3ac5-48e4-826f-cf39b6dfd750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527637601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.527637601
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2053146694
Short name T98
Test name
Test status
Simulation time 241328498 ps
CPU time 3.43 seconds
Started Jun 09 12:44:09 PM PDT 24
Finished Jun 09 12:44:13 PM PDT 24
Peak memory 218360 kb
Host smart-588fcf5e-90c9-40a4-84c5-0d1a95afb300
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053146694 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2053146694
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3123708596
Short name T106
Test name
Test status
Simulation time 436335516 ps
CPU time 2.55 seconds
Started Jun 09 12:44:13 PM PDT 24
Finished Jun 09 12:44:15 PM PDT 24
Peak memory 215672 kb
Host smart-d5c22220-e141-4975-8d9f-3e9c3c8eccdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123708596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3123708596
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3886967688
Short name T1037
Test name
Test status
Simulation time 29244148 ps
CPU time 0.71 seconds
Started Jun 09 12:44:09 PM PDT 24
Finished Jun 09 12:44:10 PM PDT 24
Peak memory 204376 kb
Host smart-824fa972-d69a-47a6-8464-ffcf7cb70261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886967688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3886967688
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3982155902
Short name T1006
Test name
Test status
Simulation time 113252438 ps
CPU time 3.05 seconds
Started Jun 09 12:44:14 PM PDT 24
Finished Jun 09 12:44:18 PM PDT 24
Peak memory 207596 kb
Host smart-69c17f14-22ea-4d64-94c9-8eb3ec9a06a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982155902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3982155902
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.856253160
Short name T1071
Test name
Test status
Simulation time 155671860 ps
CPU time 2.14 seconds
Started Jun 09 12:44:16 PM PDT 24
Finished Jun 09 12:44:18 PM PDT 24
Peak memory 216008 kb
Host smart-565e3f56-5b80-4520-a515-ae80fbbbf7b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856253160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.856253160
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.575898339
Short name T1016
Test name
Test status
Simulation time 131664797 ps
CPU time 3.68 seconds
Started Jun 09 12:44:13 PM PDT 24
Finished Jun 09 12:44:17 PM PDT 24
Peak memory 217776 kb
Host smart-23f7a5b7-aec2-413d-a7b7-30eb990a4f27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575898339 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.575898339
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3266803849
Short name T1033
Test name
Test status
Simulation time 31718194 ps
CPU time 1.28 seconds
Started Jun 09 12:44:13 PM PDT 24
Finished Jun 09 12:44:15 PM PDT 24
Peak memory 215796 kb
Host smart-b24b0545-d365-4c2a-aa75-e8c112305d22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266803849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3266803849
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2964780170
Short name T977
Test name
Test status
Simulation time 14546202 ps
CPU time 0.75 seconds
Started Jun 09 12:44:09 PM PDT 24
Finished Jun 09 12:44:10 PM PDT 24
Peak memory 204372 kb
Host smart-c40d07fc-27df-44d3-9c10-0241248333d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964780170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2964780170
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1625745999
Short name T1056
Test name
Test status
Simulation time 133509820 ps
CPU time 1.92 seconds
Started Jun 09 12:44:15 PM PDT 24
Finished Jun 09 12:44:18 PM PDT 24
Peak memory 215728 kb
Host smart-7cc4e599-0d0e-474e-a318-eecc59bddb56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625745999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1625745999
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2596765258
Short name T1085
Test name
Test status
Simulation time 147376544 ps
CPU time 1.99 seconds
Started Jun 09 12:44:17 PM PDT 24
Finished Jun 09 12:44:19 PM PDT 24
Peak memory 215952 kb
Host smart-0f1b7744-aba7-46c7-b7ef-5c54559b8ee3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596765258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2596765258
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3137978740
Short name T1008
Test name
Test status
Simulation time 140341959 ps
CPU time 1.76 seconds
Started Jun 09 12:44:18 PM PDT 24
Finished Jun 09 12:44:20 PM PDT 24
Peak memory 215820 kb
Host smart-16a97e95-9e4d-4e0c-9a75-b5d00eb385f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137978740 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3137978740
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2264746989
Short name T112
Test name
Test status
Simulation time 114908174 ps
CPU time 2.03 seconds
Started Jun 09 12:44:11 PM PDT 24
Finished Jun 09 12:44:13 PM PDT 24
Peak memory 215716 kb
Host smart-fe26b39c-3a33-44df-856a-2e8a66d54aeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264746989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2264746989
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.126295348
Short name T1067
Test name
Test status
Simulation time 16280473 ps
CPU time 0.77 seconds
Started Jun 09 12:44:13 PM PDT 24
Finished Jun 09 12:44:15 PM PDT 24
Peak memory 204368 kb
Host smart-7fec0005-c2d7-40c1-a773-08f6fd16876f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126295348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.126295348
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3392824550
Short name T1030
Test name
Test status
Simulation time 68296544 ps
CPU time 2.08 seconds
Started Jun 09 12:44:12 PM PDT 24
Finished Jun 09 12:44:14 PM PDT 24
Peak memory 207612 kb
Host smart-590bf8d5-432d-4a41-8ef1-6de09e598a0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392824550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3392824550
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.439937749
Short name T94
Test name
Test status
Simulation time 476520798 ps
CPU time 3.37 seconds
Started Jun 09 12:44:12 PM PDT 24
Finished Jun 09 12:44:15 PM PDT 24
Peak memory 216896 kb
Host smart-d5f13404-0777-443f-ad54-656d1e6404ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439937749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.439937749
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2507986751
Short name T245
Test name
Test status
Simulation time 280092330 ps
CPU time 18.11 seconds
Started Jun 09 12:44:12 PM PDT 24
Finished Jun 09 12:44:30 PM PDT 24
Peak memory 215788 kb
Host smart-f31b78c9-1e03-4e3f-a9e5-d42aa71bc0f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507986751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2507986751
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3467460260
Short name T986
Test name
Test status
Simulation time 436023748 ps
CPU time 7.43 seconds
Started Jun 09 12:43:51 PM PDT 24
Finished Jun 09 12:43:58 PM PDT 24
Peak memory 215656 kb
Host smart-dcb76fa2-92f0-45cd-99df-a5a3176b5d4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467460260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3467460260
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1220916434
Short name T1003
Test name
Test status
Simulation time 616852311 ps
CPU time 13.11 seconds
Started Jun 09 12:43:48 PM PDT 24
Finished Jun 09 12:44:02 PM PDT 24
Peak memory 207528 kb
Host smart-e6e76191-4d0c-453b-b75a-c2d4b077029e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220916434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1220916434
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.976365347
Short name T69
Test name
Test status
Simulation time 47745022 ps
CPU time 1.43 seconds
Started Jun 09 12:43:51 PM PDT 24
Finished Jun 09 12:43:53 PM PDT 24
Peak memory 207604 kb
Host smart-c8413db1-8793-4b40-91b9-c1293d46672e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976365347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.976365347
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3878217972
Short name T1051
Test name
Test status
Simulation time 24234785 ps
CPU time 1.67 seconds
Started Jun 09 12:43:49 PM PDT 24
Finished Jun 09 12:43:51 PM PDT 24
Peak memory 215792 kb
Host smart-3e1d4bb9-d10f-4265-968c-b49f74a2b3e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878217972 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3878217972
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4294005892
Short name T108
Test name
Test status
Simulation time 39924702 ps
CPU time 1.39 seconds
Started Jun 09 12:43:52 PM PDT 24
Finished Jun 09 12:43:54 PM PDT 24
Peak memory 215712 kb
Host smart-ef786efc-3959-433b-bf2b-8e73dd4ea2ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294005892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
294005892
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.284754614
Short name T1048
Test name
Test status
Simulation time 27003898 ps
CPU time 0.77 seconds
Started Jun 09 12:43:49 PM PDT 24
Finished Jun 09 12:43:50 PM PDT 24
Peak memory 204040 kb
Host smart-dbea1273-bb28-453f-ad9c-d7e6e80bc21d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284754614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.284754614
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1825999032
Short name T1036
Test name
Test status
Simulation time 146081971 ps
CPU time 1.48 seconds
Started Jun 09 12:43:48 PM PDT 24
Finished Jun 09 12:43:50 PM PDT 24
Peak memory 215872 kb
Host smart-e7609234-31c7-47a1-a651-c0a3ffa36559
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825999032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1825999032
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.372060108
Short name T1013
Test name
Test status
Simulation time 10558484 ps
CPU time 0.67 seconds
Started Jun 09 12:43:50 PM PDT 24
Finished Jun 09 12:43:51 PM PDT 24
Peak memory 204028 kb
Host smart-1fdc326a-373b-4fc1-9a93-866f421b867b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372060108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.372060108
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1051250853
Short name T1042
Test name
Test status
Simulation time 205557659 ps
CPU time 1.85 seconds
Started Jun 09 12:43:48 PM PDT 24
Finished Jun 09 12:43:50 PM PDT 24
Peak memory 207588 kb
Host smart-bb404860-edca-4df9-9ae7-a0c1cc7d5282
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051250853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1051250853
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.322924259
Short name T84
Test name
Test status
Simulation time 26215592 ps
CPU time 1.78 seconds
Started Jun 09 12:43:50 PM PDT 24
Finished Jun 09 12:43:52 PM PDT 24
Peak memory 215928 kb
Host smart-fa45d09c-7974-4830-82b0-48965634c32d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322924259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.322924259
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1121327213
Short name T246
Test name
Test status
Simulation time 1148628065 ps
CPU time 7.03 seconds
Started Jun 09 12:43:48 PM PDT 24
Finished Jun 09 12:43:56 PM PDT 24
Peak memory 216456 kb
Host smart-68e4202d-865f-4160-8758-a19ec1c7d39f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121327213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1121327213
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1922302330
Short name T976
Test name
Test status
Simulation time 34966610 ps
CPU time 0.72 seconds
Started Jun 09 12:44:12 PM PDT 24
Finished Jun 09 12:44:13 PM PDT 24
Peak memory 204008 kb
Host smart-8202f5d0-a276-4d42-888a-c30bd821649c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922302330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1922302330
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2176660522
Short name T1060
Test name
Test status
Simulation time 37799488 ps
CPU time 0.7 seconds
Started Jun 09 12:44:15 PM PDT 24
Finished Jun 09 12:44:16 PM PDT 24
Peak memory 204052 kb
Host smart-9764f284-1bf7-4839-8634-93efaf13358d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176660522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2176660522
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3270956990
Short name T1062
Test name
Test status
Simulation time 49959782 ps
CPU time 0.74 seconds
Started Jun 09 12:44:10 PM PDT 24
Finished Jun 09 12:44:11 PM PDT 24
Peak memory 204376 kb
Host smart-18aad5e3-86eb-4426-886c-e75d36e59edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270956990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3270956990
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2328054316
Short name T987
Test name
Test status
Simulation time 40772981 ps
CPU time 0.69 seconds
Started Jun 09 12:44:12 PM PDT 24
Finished Jun 09 12:44:14 PM PDT 24
Peak memory 204384 kb
Host smart-cc95c549-bf31-4a89-96af-ae0866f0369d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328054316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2328054316
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2868172943
Short name T1055
Test name
Test status
Simulation time 19369493 ps
CPU time 0.69 seconds
Started Jun 09 12:44:15 PM PDT 24
Finished Jun 09 12:44:16 PM PDT 24
Peak memory 203996 kb
Host smart-bd50e76d-f7ca-4316-9101-4e3dc34968dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868172943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2868172943
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2959873265
Short name T1002
Test name
Test status
Simulation time 32502883 ps
CPU time 0.71 seconds
Started Jun 09 12:44:12 PM PDT 24
Finished Jun 09 12:44:13 PM PDT 24
Peak memory 204036 kb
Host smart-b1afb292-3c12-4662-a59c-7848e4d5aad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959873265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2959873265
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.820921519
Short name T1054
Test name
Test status
Simulation time 58410794 ps
CPU time 0.77 seconds
Started Jun 09 12:44:13 PM PDT 24
Finished Jun 09 12:44:15 PM PDT 24
Peak memory 204040 kb
Host smart-a241aef0-d3f4-4712-973b-3b84ef64309b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820921519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.820921519
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3176304453
Short name T988
Test name
Test status
Simulation time 15635597 ps
CPU time 0.75 seconds
Started Jun 09 12:44:15 PM PDT 24
Finished Jun 09 12:44:17 PM PDT 24
Peak memory 204380 kb
Host smart-4b1ab3d3-f1d0-4e59-9c38-8eda51849918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176304453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3176304453
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2476722800
Short name T1012
Test name
Test status
Simulation time 26213905 ps
CPU time 0.73 seconds
Started Jun 09 12:44:14 PM PDT 24
Finished Jun 09 12:44:15 PM PDT 24
Peak memory 204380 kb
Host smart-467087bb-a06a-4538-9e16-161647733ca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476722800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2476722800
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2259585002
Short name T1039
Test name
Test status
Simulation time 63752099 ps
CPU time 0.75 seconds
Started Jun 09 12:44:19 PM PDT 24
Finished Jun 09 12:44:20 PM PDT 24
Peak memory 204276 kb
Host smart-cd170af8-71b0-4f6b-83ae-6eadb2ca87c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259585002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2259585002
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.476997656
Short name T1050
Test name
Test status
Simulation time 420559176 ps
CPU time 15.12 seconds
Started Jun 09 12:43:53 PM PDT 24
Finished Jun 09 12:44:08 PM PDT 24
Peak memory 207468 kb
Host smart-093f9eb2-5dc5-4abb-9664-214665ab3bce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476997656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.476997656
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4091056838
Short name T1057
Test name
Test status
Simulation time 2438091004 ps
CPU time 38.01 seconds
Started Jun 09 12:43:53 PM PDT 24
Finished Jun 09 12:44:32 PM PDT 24
Peak memory 207576 kb
Host smart-ef6cb987-e785-41fa-8904-02fbbe5ba8fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091056838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.4091056838
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2697992860
Short name T1075
Test name
Test status
Simulation time 37687322 ps
CPU time 1.11 seconds
Started Jun 09 12:43:54 PM PDT 24
Finished Jun 09 12:43:55 PM PDT 24
Peak memory 207380 kb
Host smart-e30c4e48-920f-4acc-bb82-92ee7c26615b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697992860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2697992860
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1308996238
Short name T141
Test name
Test status
Simulation time 199610925 ps
CPU time 2.94 seconds
Started Jun 09 12:43:55 PM PDT 24
Finished Jun 09 12:43:59 PM PDT 24
Peak memory 218340 kb
Host smart-08e76a50-e15d-4c08-90da-23aa26df5872
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308996238 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1308996238
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4035210040
Short name T1099
Test name
Test status
Simulation time 68331260 ps
CPU time 1.9 seconds
Started Jun 09 12:43:55 PM PDT 24
Finished Jun 09 12:43:57 PM PDT 24
Peak memory 207600 kb
Host smart-3e88aec9-f739-4151-8387-0189b54ebb44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035210040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
035210040
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.975412960
Short name T1021
Test name
Test status
Simulation time 13050384 ps
CPU time 0.73 seconds
Started Jun 09 12:43:49 PM PDT 24
Finished Jun 09 12:43:50 PM PDT 24
Peak memory 204040 kb
Host smart-48bb759e-24c1-4eae-b3ba-2b64e30ad4f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975412960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.975412960
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3478408378
Short name T1023
Test name
Test status
Simulation time 36272616 ps
CPU time 1.28 seconds
Started Jun 09 12:43:51 PM PDT 24
Finished Jun 09 12:43:52 PM PDT 24
Peak memory 215704 kb
Host smart-d64f7e78-1840-42fb-8277-11b6eea541f7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478408378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3478408378
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1643757369
Short name T1059
Test name
Test status
Simulation time 32498077 ps
CPU time 0.67 seconds
Started Jun 09 12:43:51 PM PDT 24
Finished Jun 09 12:43:52 PM PDT 24
Peak memory 204012 kb
Host smart-c8ce56c1-d058-400d-96d4-b06807c78089
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643757369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1643757369
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1027821741
Short name T1014
Test name
Test status
Simulation time 228313267 ps
CPU time 3.7 seconds
Started Jun 09 12:43:51 PM PDT 24
Finished Jun 09 12:43:55 PM PDT 24
Peak memory 215664 kb
Host smart-10f2c445-baa1-4cf8-a2a8-165e675c382a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027821741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1027821741
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4144344089
Short name T95
Test name
Test status
Simulation time 2791111077 ps
CPU time 4.07 seconds
Started Jun 09 12:43:48 PM PDT 24
Finished Jun 09 12:43:52 PM PDT 24
Peak memory 216056 kb
Host smart-d54f9e43-01eb-4fe0-8e8d-1625b08a1b12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144344089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.4
144344089
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.970571664
Short name T243
Test name
Test status
Simulation time 2487718205 ps
CPU time 14.31 seconds
Started Jun 09 12:43:50 PM PDT 24
Finished Jun 09 12:44:05 PM PDT 24
Peak memory 215808 kb
Host smart-8fd387cf-26c0-41ac-816c-73bd55bd878e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970571664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.970571664
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1523830233
Short name T983
Test name
Test status
Simulation time 15992733 ps
CPU time 0.73 seconds
Started Jun 09 12:44:16 PM PDT 24
Finished Jun 09 12:44:17 PM PDT 24
Peak memory 204384 kb
Host smart-e4dcad86-313d-4557-a333-79c1b5dff199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523830233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1523830233
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2295246945
Short name T1072
Test name
Test status
Simulation time 30738219 ps
CPU time 0.75 seconds
Started Jun 09 12:44:18 PM PDT 24
Finished Jun 09 12:44:19 PM PDT 24
Peak memory 204116 kb
Host smart-9f41538c-d22d-42fb-830f-b6cf424c562a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295246945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2295246945
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2041380706
Short name T1080
Test name
Test status
Simulation time 14364629 ps
CPU time 0.79 seconds
Started Jun 09 12:44:13 PM PDT 24
Finished Jun 09 12:44:15 PM PDT 24
Peak memory 204064 kb
Host smart-21a154b6-a607-4fb0-be04-253236109ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041380706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2041380706
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.325390370
Short name T990
Test name
Test status
Simulation time 12801016 ps
CPU time 0.72 seconds
Started Jun 09 12:44:14 PM PDT 24
Finished Jun 09 12:44:15 PM PDT 24
Peak memory 204112 kb
Host smart-88f4560a-28e6-437f-bdc5-87992942b43b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325390370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.325390370
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3641343074
Short name T1029
Test name
Test status
Simulation time 51003332 ps
CPU time 0.78 seconds
Started Jun 09 12:44:14 PM PDT 24
Finished Jun 09 12:44:16 PM PDT 24
Peak memory 204124 kb
Host smart-65035884-79b0-44a8-b454-722b6bb6ec84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641343074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3641343074
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2008568827
Short name T981
Test name
Test status
Simulation time 14736912 ps
CPU time 0.72 seconds
Started Jun 09 12:44:13 PM PDT 24
Finished Jun 09 12:44:15 PM PDT 24
Peak memory 204376 kb
Host smart-9eb7ea9f-a206-4817-a6c0-7c42413128b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008568827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2008568827
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3692180829
Short name T985
Test name
Test status
Simulation time 17924476 ps
CPU time 0.76 seconds
Started Jun 09 12:44:13 PM PDT 24
Finished Jun 09 12:44:14 PM PDT 24
Peak memory 204292 kb
Host smart-8ef0a434-e7ce-4b43-bac1-dfaa3fed3fcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692180829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3692180829
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2026908823
Short name T994
Test name
Test status
Simulation time 12671785 ps
CPU time 0.73 seconds
Started Jun 09 12:44:15 PM PDT 24
Finished Jun 09 12:44:16 PM PDT 24
Peak memory 204084 kb
Host smart-a397fc99-e924-4842-b961-766e923b13eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026908823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2026908823
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.272534782
Short name T1098
Test name
Test status
Simulation time 25371737 ps
CPU time 0.76 seconds
Started Jun 09 12:44:16 PM PDT 24
Finished Jun 09 12:44:17 PM PDT 24
Peak memory 204364 kb
Host smart-175ceb6f-f89e-48ec-952d-006293bde01f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272534782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.272534782
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2002469116
Short name T1096
Test name
Test status
Simulation time 19251577 ps
CPU time 0.73 seconds
Started Jun 09 12:44:13 PM PDT 24
Finished Jun 09 12:44:14 PM PDT 24
Peak memory 204372 kb
Host smart-ae5946c3-a9f2-427d-b2b8-f1fd41ea48f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002469116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2002469116
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1348761393
Short name T1041
Test name
Test status
Simulation time 610265875 ps
CPU time 22.22 seconds
Started Jun 09 12:43:55 PM PDT 24
Finished Jun 09 12:44:18 PM PDT 24
Peak memory 215820 kb
Host smart-0e71a936-908a-4b20-8ddd-5fc882ba53f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348761393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1348761393
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.392633480
Short name T1093
Test name
Test status
Simulation time 559570951 ps
CPU time 34.91 seconds
Started Jun 09 12:43:52 PM PDT 24
Finished Jun 09 12:44:27 PM PDT 24
Peak memory 207712 kb
Host smart-ed53778d-5ecc-4b68-924e-abba4cca6ccd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392633480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.392633480
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1809911302
Short name T1064
Test name
Test status
Simulation time 54267387 ps
CPU time 0.98 seconds
Started Jun 09 12:43:52 PM PDT 24
Finished Jun 09 12:43:54 PM PDT 24
Peak memory 207356 kb
Host smart-a3efe09a-1e89-46ff-bcc0-f7cc5704f64b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809911302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1809911302
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1230820837
Short name T148
Test name
Test status
Simulation time 419460310 ps
CPU time 2.78 seconds
Started Jun 09 12:43:55 PM PDT 24
Finished Jun 09 12:43:58 PM PDT 24
Peak memory 217376 kb
Host smart-6550e494-c1b2-4c4c-851b-9c2ed232f5e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230820837 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1230820837
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2931200577
Short name T111
Test name
Test status
Simulation time 420201786 ps
CPU time 2.48 seconds
Started Jun 09 12:43:52 PM PDT 24
Finished Jun 09 12:43:55 PM PDT 24
Peak memory 215772 kb
Host smart-9bdb60b0-48e8-4a60-8d59-a111e0179126
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931200577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
931200577
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.418846355
Short name T984
Test name
Test status
Simulation time 53591250 ps
CPU time 0.77 seconds
Started Jun 09 12:43:55 PM PDT 24
Finished Jun 09 12:43:56 PM PDT 24
Peak memory 204052 kb
Host smart-d4118603-d087-4cd0-a006-533597841a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418846355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.418846355
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1179966971
Short name T1046
Test name
Test status
Simulation time 97414562 ps
CPU time 2.01 seconds
Started Jun 09 12:43:55 PM PDT 24
Finished Jun 09 12:43:57 PM PDT 24
Peak memory 215736 kb
Host smart-fcd8bc26-d6db-47bb-9f45-098f90cb8cd5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179966971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1179966971
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.234039406
Short name T1091
Test name
Test status
Simulation time 18179377 ps
CPU time 0.7 seconds
Started Jun 09 12:43:55 PM PDT 24
Finished Jun 09 12:43:56 PM PDT 24
Peak memory 204016 kb
Host smart-0e548c70-d668-4f5a-af45-54605eda3c57
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234039406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.234039406
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1055438593
Short name T1045
Test name
Test status
Simulation time 63830389 ps
CPU time 2.8 seconds
Started Jun 09 12:43:54 PM PDT 24
Finished Jun 09 12:43:58 PM PDT 24
Peak memory 215752 kb
Host smart-d192f646-2187-4881-97d8-6649b967665e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055438593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1055438593
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.536622334
Short name T1094
Test name
Test status
Simulation time 95058854 ps
CPU time 1.55 seconds
Started Jun 09 12:43:56 PM PDT 24
Finished Jun 09 12:43:58 PM PDT 24
Peak memory 215860 kb
Host smart-785c7073-e046-4791-8b4d-e1ce477db860
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536622334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.536622334
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3750578597
Short name T90
Test name
Test status
Simulation time 2247021028 ps
CPU time 14.46 seconds
Started Jun 09 12:43:54 PM PDT 24
Finished Jun 09 12:44:09 PM PDT 24
Peak memory 215816 kb
Host smart-63392045-7cfc-4b3c-86ff-2f465928238d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750578597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3750578597
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2940682987
Short name T989
Test name
Test status
Simulation time 19937162 ps
CPU time 0.76 seconds
Started Jun 09 12:44:13 PM PDT 24
Finished Jun 09 12:44:14 PM PDT 24
Peak memory 204120 kb
Host smart-6d87cf5b-6026-41cd-b8fd-24800144d78f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940682987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2940682987
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3371455931
Short name T1043
Test name
Test status
Simulation time 13025399 ps
CPU time 0.73 seconds
Started Jun 09 12:44:15 PM PDT 24
Finished Jun 09 12:44:16 PM PDT 24
Peak memory 204332 kb
Host smart-54929fbc-0b54-4842-bc04-c03e2575c5de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371455931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3371455931
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3776588345
Short name T997
Test name
Test status
Simulation time 17262333 ps
CPU time 0.75 seconds
Started Jun 09 12:44:14 PM PDT 24
Finished Jun 09 12:44:15 PM PDT 24
Peak memory 204052 kb
Host smart-e08de12a-3081-4dc6-a8d1-e58103437bc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776588345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3776588345
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1863684142
Short name T1020
Test name
Test status
Simulation time 40887311 ps
CPU time 0.72 seconds
Started Jun 09 12:44:13 PM PDT 24
Finished Jun 09 12:44:14 PM PDT 24
Peak memory 204044 kb
Host smart-76b7d9be-ba9e-4383-b2f2-b9b6041b4aa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863684142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1863684142
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3100367331
Short name T1032
Test name
Test status
Simulation time 42573357 ps
CPU time 0.72 seconds
Started Jun 09 12:44:14 PM PDT 24
Finished Jun 09 12:44:15 PM PDT 24
Peak memory 204112 kb
Host smart-c015a9ac-7189-45d5-ab8d-9455166fff88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100367331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3100367331
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2049098810
Short name T1083
Test name
Test status
Simulation time 17029161 ps
CPU time 0.8 seconds
Started Jun 09 12:44:13 PM PDT 24
Finished Jun 09 12:44:15 PM PDT 24
Peak memory 204072 kb
Host smart-f8890c10-43a0-4326-8666-e889a8e1010e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049098810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2049098810
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4238880390
Short name T1084
Test name
Test status
Simulation time 50467753 ps
CPU time 0.77 seconds
Started Jun 09 12:44:19 PM PDT 24
Finished Jun 09 12:44:20 PM PDT 24
Peak memory 204256 kb
Host smart-2116a5cd-54db-4338-8981-8c01c8784985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238880390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4238880390
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2189484890
Short name T1047
Test name
Test status
Simulation time 30019404 ps
CPU time 0.78 seconds
Started Jun 09 12:44:15 PM PDT 24
Finished Jun 09 12:44:16 PM PDT 24
Peak memory 204124 kb
Host smart-c0d45204-95ab-4b32-99c0-6b8e6fd4253d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189484890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2189484890
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1410265750
Short name T1005
Test name
Test status
Simulation time 56813461 ps
CPU time 0.76 seconds
Started Jun 09 12:44:17 PM PDT 24
Finished Jun 09 12:44:18 PM PDT 24
Peak memory 204064 kb
Host smart-7fc419a3-9b23-4fb5-a231-9393d8385867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410265750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1410265750
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3571134090
Short name T1097
Test name
Test status
Simulation time 14938970 ps
CPU time 0.76 seconds
Started Jun 09 12:44:17 PM PDT 24
Finished Jun 09 12:44:19 PM PDT 24
Peak memory 204384 kb
Host smart-2c810442-0ce2-43df-aeac-6905a3936369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571134090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3571134090
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1847511835
Short name T1063
Test name
Test status
Simulation time 175886109 ps
CPU time 1.62 seconds
Started Jun 09 12:43:54 PM PDT 24
Finished Jun 09 12:43:56 PM PDT 24
Peak memory 215916 kb
Host smart-6eb314fe-6c1b-449e-b3e7-4611e999f150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847511835 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1847511835
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3286653504
Short name T1095
Test name
Test status
Simulation time 163481156 ps
CPU time 1.45 seconds
Started Jun 09 12:43:54 PM PDT 24
Finished Jun 09 12:43:56 PM PDT 24
Peak memory 207592 kb
Host smart-88354a89-6b56-4c58-8ddb-a7f1ca9f5972
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286653504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
286653504
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2434556908
Short name T1017
Test name
Test status
Simulation time 25692766 ps
CPU time 0.72 seconds
Started Jun 09 12:43:53 PM PDT 24
Finished Jun 09 12:43:54 PM PDT 24
Peak memory 204052 kb
Host smart-2a4768ce-2d96-464e-b21b-c024342644b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434556908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
434556908
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.943088131
Short name T996
Test name
Test status
Simulation time 144083198 ps
CPU time 3.24 seconds
Started Jun 09 12:43:55 PM PDT 24
Finished Jun 09 12:43:58 PM PDT 24
Peak memory 215748 kb
Host smart-457ea670-51d3-478f-bfda-29569faae83b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943088131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.943088131
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2750679903
Short name T91
Test name
Test status
Simulation time 229758913 ps
CPU time 4.89 seconds
Started Jun 09 12:43:53 PM PDT 24
Finished Jun 09 12:43:58 PM PDT 24
Peak memory 215856 kb
Host smart-52dda712-6c7e-48ee-9f2d-0a7d2929ff9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750679903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
750679903
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1853899430
Short name T138
Test name
Test status
Simulation time 640876209 ps
CPU time 8.45 seconds
Started Jun 09 12:43:51 PM PDT 24
Finished Jun 09 12:44:00 PM PDT 24
Peak memory 217364 kb
Host smart-382e1b58-86de-43f1-a3d7-7f775cf7a84d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853899430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1853899430
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3591501859
Short name T1035
Test name
Test status
Simulation time 127302398 ps
CPU time 3.65 seconds
Started Jun 09 12:44:01 PM PDT 24
Finished Jun 09 12:44:05 PM PDT 24
Peak memory 217776 kb
Host smart-f674ea21-d23e-4e06-99db-86c8f360bd65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591501859 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3591501859
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1797422338
Short name T1089
Test name
Test status
Simulation time 40422173 ps
CPU time 1.37 seconds
Started Jun 09 12:43:58 PM PDT 24
Finished Jun 09 12:44:00 PM PDT 24
Peak memory 207524 kb
Host smart-da182db2-cdb6-4fc5-a474-638893c33ae2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797422338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
797422338
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.902400374
Short name T980
Test name
Test status
Simulation time 39665567 ps
CPU time 0.74 seconds
Started Jun 09 12:43:59 PM PDT 24
Finished Jun 09 12:44:00 PM PDT 24
Peak memory 204340 kb
Host smart-2c100925-22b5-49c4-b2ea-0890f156331d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902400374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.902400374
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.501016929
Short name T1028
Test name
Test status
Simulation time 59587103 ps
CPU time 4.14 seconds
Started Jun 09 12:43:57 PM PDT 24
Finished Jun 09 12:44:02 PM PDT 24
Peak memory 215728 kb
Host smart-ba24b78f-8581-4565-b795-3bbf3c8c8bda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501016929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.501016929
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3927702251
Short name T1010
Test name
Test status
Simulation time 279801152 ps
CPU time 2.37 seconds
Started Jun 09 12:43:59 PM PDT 24
Finished Jun 09 12:44:02 PM PDT 24
Peak memory 215948 kb
Host smart-54086fb2-301d-44b5-911d-5fdcbda899c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927702251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
927702251
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1491558606
Short name T244
Test name
Test status
Simulation time 2074642847 ps
CPU time 21.32 seconds
Started Jun 09 12:44:07 PM PDT 24
Finished Jun 09 12:44:28 PM PDT 24
Peak memory 216216 kb
Host smart-cba6fb43-8bab-47cc-afef-e3ed4a6a5345
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491558606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1491558606
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2891017169
Short name T1079
Test name
Test status
Simulation time 53691128 ps
CPU time 3.83 seconds
Started Jun 09 12:43:58 PM PDT 24
Finished Jun 09 12:44:02 PM PDT 24
Peak memory 218940 kb
Host smart-997e7591-6ef2-431f-ae8d-99cebe76d8a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891017169 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2891017169
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3146252890
Short name T1092
Test name
Test status
Simulation time 336525589 ps
CPU time 1.46 seconds
Started Jun 09 12:43:58 PM PDT 24
Finished Jun 09 12:44:00 PM PDT 24
Peak memory 207616 kb
Host smart-93df34ac-38d0-412e-86b3-a738a4ff63a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146252890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
146252890
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4265901580
Short name T1076
Test name
Test status
Simulation time 22250577 ps
CPU time 0.74 seconds
Started Jun 09 12:44:06 PM PDT 24
Finished Jun 09 12:44:07 PM PDT 24
Peak memory 204104 kb
Host smart-a1c653d4-d127-41af-83ca-ce8356ed475a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265901580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4
265901580
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.532069023
Short name T995
Test name
Test status
Simulation time 626953198 ps
CPU time 4.07 seconds
Started Jun 09 12:44:01 PM PDT 24
Finished Jun 09 12:44:05 PM PDT 24
Peak memory 215760 kb
Host smart-e921b8b2-707c-465b-bc44-57048c2674b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532069023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.532069023
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2964016259
Short name T96
Test name
Test status
Simulation time 117714468 ps
CPU time 2.17 seconds
Started Jun 09 12:43:58 PM PDT 24
Finished Jun 09 12:44:01 PM PDT 24
Peak memory 215948 kb
Host smart-ed2f7b23-d922-475f-a17c-2a0a67e8d777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964016259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
964016259
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2378116212
Short name T238
Test name
Test status
Simulation time 4005095013 ps
CPU time 12.7 seconds
Started Jun 09 12:44:06 PM PDT 24
Finished Jun 09 12:44:19 PM PDT 24
Peak memory 215772 kb
Host smart-c2aedb7f-7145-4a60-880b-154a39af30aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378116212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2378116212
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3895489188
Short name T82
Test name
Test status
Simulation time 483821922 ps
CPU time 3.13 seconds
Started Jun 09 12:44:07 PM PDT 24
Finished Jun 09 12:44:10 PM PDT 24
Peak memory 218336 kb
Host smart-ad2c68ca-6b07-46c2-83d4-a5646b6f3918
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895489188 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3895489188
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3427049976
Short name T1000
Test name
Test status
Simulation time 284113888 ps
CPU time 1.87 seconds
Started Jun 09 12:43:58 PM PDT 24
Finished Jun 09 12:44:00 PM PDT 24
Peak memory 207600 kb
Host smart-57d3cf06-0be7-40d0-af26-342dda30c599
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427049976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
427049976
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2527531100
Short name T1019
Test name
Test status
Simulation time 53331405 ps
CPU time 0.76 seconds
Started Jun 09 12:44:06 PM PDT 24
Finished Jun 09 12:44:07 PM PDT 24
Peak memory 204112 kb
Host smart-8810ba8c-db0d-4892-85f6-8da81d70fd9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527531100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
527531100
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2311414195
Short name T139
Test name
Test status
Simulation time 149944157 ps
CPU time 3.31 seconds
Started Jun 09 12:44:01 PM PDT 24
Finished Jun 09 12:44:04 PM PDT 24
Peak memory 215804 kb
Host smart-a743e935-fa04-4300-91fc-6c87be80e265
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311414195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2311414195
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2410223577
Short name T97
Test name
Test status
Simulation time 514918158 ps
CPU time 3.25 seconds
Started Jun 09 12:43:59 PM PDT 24
Finished Jun 09 12:44:02 PM PDT 24
Peak memory 215940 kb
Host smart-0063453c-8840-4f52-9162-6398680c5afa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410223577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
410223577
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1744451646
Short name T241
Test name
Test status
Simulation time 3264141974 ps
CPU time 22.02 seconds
Started Jun 09 12:44:01 PM PDT 24
Finished Jun 09 12:44:23 PM PDT 24
Peak memory 224012 kb
Host smart-0ae6bbd3-9f51-4b2a-8d1f-0308f1ff7d43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744451646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1744451646
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3190990496
Short name T1069
Test name
Test status
Simulation time 29014121 ps
CPU time 2.22 seconds
Started Jun 09 12:44:03 PM PDT 24
Finished Jun 09 12:44:05 PM PDT 24
Peak memory 216816 kb
Host smart-cec8b492-f617-4925-9a5b-a8ea114a83d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190990496 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3190990496
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2970549961
Short name T1025
Test name
Test status
Simulation time 196152940 ps
CPU time 2.75 seconds
Started Jun 09 12:44:09 PM PDT 24
Finished Jun 09 12:44:12 PM PDT 24
Peak memory 215788 kb
Host smart-c9d4b436-d5b2-4d81-875b-606ac301bac3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970549961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
970549961
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.832036968
Short name T1078
Test name
Test status
Simulation time 21483266 ps
CPU time 0.73 seconds
Started Jun 09 12:44:03 PM PDT 24
Finished Jun 09 12:44:04 PM PDT 24
Peak memory 204000 kb
Host smart-9f9928b7-f031-4c45-9c5d-618fc3eaebf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832036968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.832036968
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4066108809
Short name T1022
Test name
Test status
Simulation time 721120487 ps
CPU time 4.15 seconds
Started Jun 09 12:44:03 PM PDT 24
Finished Jun 09 12:44:07 PM PDT 24
Peak memory 215752 kb
Host smart-283c569a-4ab6-4e3b-b96f-7c9ece1cdf0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066108809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4066108809
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1519195652
Short name T86
Test name
Test status
Simulation time 85368157 ps
CPU time 1.73 seconds
Started Jun 09 12:44:06 PM PDT 24
Finished Jun 09 12:44:09 PM PDT 24
Peak memory 216056 kb
Host smart-fafc8798-8eaa-4858-a185-0577649e556f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519195652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
519195652
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.801341772
Short name T140
Test name
Test status
Simulation time 361931414 ps
CPU time 8.07 seconds
Started Jun 09 12:44:07 PM PDT 24
Finished Jun 09 12:44:16 PM PDT 24
Peak memory 215892 kb
Host smart-817bdde7-2f9f-40a3-aaa2-408670cd53b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801341772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.801341772
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.239938012
Short name T498
Test name
Test status
Simulation time 29381980 ps
CPU time 0.69 seconds
Started Jun 09 02:28:43 PM PDT 24
Finished Jun 09 02:28:44 PM PDT 24
Peak memory 204532 kb
Host smart-0544e068-ca85-41af-a113-c9f99a561bff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239938012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.239938012
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2331244488
Short name T74
Test name
Test status
Simulation time 90979310 ps
CPU time 2.79 seconds
Started Jun 09 02:28:48 PM PDT 24
Finished Jun 09 02:28:51 PM PDT 24
Peak memory 232492 kb
Host smart-6273dcf0-4ecc-4c53-956c-0d544417af73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331244488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2331244488
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2737499999
Short name T943
Test name
Test status
Simulation time 40417781 ps
CPU time 0.77 seconds
Started Jun 09 02:28:55 PM PDT 24
Finished Jun 09 02:28:56 PM PDT 24
Peak memory 206212 kb
Host smart-fe62e0e2-e74c-4a10-9684-bb78d3d1ff67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737499999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2737499999
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.860999555
Short name T175
Test name
Test status
Simulation time 70973057156 ps
CPU time 543.46 seconds
Started Jun 09 02:28:50 PM PDT 24
Finished Jun 09 02:37:54 PM PDT 24
Peak memory 253724 kb
Host smart-3346744c-e564-4108-9ce8-54a06764222c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860999555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.860999555
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.593410564
Short name T296
Test name
Test status
Simulation time 3607363631 ps
CPU time 38.88 seconds
Started Jun 09 02:29:01 PM PDT 24
Finished Jun 09 02:29:40 PM PDT 24
Peak memory 248524 kb
Host smart-c579184b-2b01-46ef-a19c-19ea42ac1803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593410564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
593410564
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1345586993
Short name T626
Test name
Test status
Simulation time 107693110 ps
CPU time 4.9 seconds
Started Jun 09 02:28:57 PM PDT 24
Finished Jun 09 02:29:02 PM PDT 24
Peak memory 224356 kb
Host smart-6b8fa153-87d7-488c-83ba-97d44fdfdfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345586993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1345586993
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2548701499
Short name T885
Test name
Test status
Simulation time 623642469 ps
CPU time 6.39 seconds
Started Jun 09 02:28:59 PM PDT 24
Finished Jun 09 02:29:06 PM PDT 24
Peak memory 232492 kb
Host smart-295f52d5-0225-40f4-935a-23e9131a01d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548701499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2548701499
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3370582244
Short name T954
Test name
Test status
Simulation time 8068905920 ps
CPU time 55.99 seconds
Started Jun 09 02:29:00 PM PDT 24
Finished Jun 09 02:29:56 PM PDT 24
Peak memory 251152 kb
Host smart-c4a44e18-5f06-4d6a-b2e7-1a8d0c98e273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370582244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3370582244
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1502065668
Short name T711
Test name
Test status
Simulation time 75589705 ps
CPU time 1.07 seconds
Started Jun 09 02:28:44 PM PDT 24
Finished Jun 09 02:28:46 PM PDT 24
Peak memory 216380 kb
Host smart-3dd59ff7-c6d3-4f2d-89b5-43ee442cf048
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502065668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1502065668
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2534958243
Short name T189
Test name
Test status
Simulation time 1997890129 ps
CPU time 4.46 seconds
Started Jun 09 02:28:55 PM PDT 24
Finished Jun 09 02:29:00 PM PDT 24
Peak memory 224272 kb
Host smart-43c5d942-c13b-4359-923f-39deca44b0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534958243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2534958243
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1949728484
Short name T467
Test name
Test status
Simulation time 12202623222 ps
CPU time 20.97 seconds
Started Jun 09 02:28:48 PM PDT 24
Finished Jun 09 02:29:10 PM PDT 24
Peak memory 224352 kb
Host smart-577a9c81-e21c-4c04-97b3-bb6a1dce070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949728484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1949728484
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3593355246
Short name T924
Test name
Test status
Simulation time 473181289 ps
CPU time 6.37 seconds
Started Jun 09 02:29:00 PM PDT 24
Finished Jun 09 02:29:07 PM PDT 24
Peak memory 218576 kb
Host smart-1f5aa835-b5dd-48b1-a860-8decf25685e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3593355246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3593355246
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2012699875
Short name T289
Test name
Test status
Simulation time 16265246676 ps
CPU time 21.75 seconds
Started Jun 09 02:29:00 PM PDT 24
Finished Jun 09 02:29:22 PM PDT 24
Peak memory 219592 kb
Host smart-661b18b8-a1c3-45aa-8e78-34054aedb954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012699875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2012699875
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1198451386
Short name T704
Test name
Test status
Simulation time 3220347356 ps
CPU time 9.14 seconds
Started Jun 09 02:28:53 PM PDT 24
Finished Jun 09 02:29:03 PM PDT 24
Peak memory 216096 kb
Host smart-c5ca0d3e-7f5d-4746-95a7-2c441951e8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198451386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1198451386
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4273885588
Short name T792
Test name
Test status
Simulation time 96434159 ps
CPU time 1.36 seconds
Started Jun 09 02:28:46 PM PDT 24
Finished Jun 09 02:28:48 PM PDT 24
Peak memory 207852 kb
Host smart-ca690b51-49e8-4d23-980a-fb6b67759340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273885588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4273885588
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3107932625
Short name T863
Test name
Test status
Simulation time 62144143 ps
CPU time 0.84 seconds
Started Jun 09 02:28:52 PM PDT 24
Finished Jun 09 02:28:54 PM PDT 24
Peak memory 205600 kb
Host smart-4cbc85ed-ae93-4cec-9162-0ba54a34c907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107932625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3107932625
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.609143653
Short name T500
Test name
Test status
Simulation time 1089707257 ps
CPU time 5.44 seconds
Started Jun 09 02:29:02 PM PDT 24
Finished Jun 09 02:29:07 PM PDT 24
Peak memory 240260 kb
Host smart-cf1c9c02-52be-4ecc-96a7-49b2bc853c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609143653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.609143653
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3119883365
Short name T861
Test name
Test status
Simulation time 108151363 ps
CPU time 0.67 seconds
Started Jun 09 02:28:54 PM PDT 24
Finished Jun 09 02:28:55 PM PDT 24
Peak memory 205156 kb
Host smart-1eda467e-9629-4c7e-bb42-eb335bd1eaee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119883365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
119883365
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2662691719
Short name T653
Test name
Test status
Simulation time 2165449154 ps
CPU time 12.66 seconds
Started Jun 09 02:28:59 PM PDT 24
Finished Jun 09 02:29:12 PM PDT 24
Peak memory 232556 kb
Host smart-a346771a-10f0-41c0-ab95-a3718fff0602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662691719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2662691719
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3055405088
Short name T855
Test name
Test status
Simulation time 14206699 ps
CPU time 0.77 seconds
Started Jun 09 02:28:49 PM PDT 24
Finished Jun 09 02:28:50 PM PDT 24
Peak memory 206524 kb
Host smart-03cb2e89-41a0-465b-9b7c-59e3b6a9c9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055405088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3055405088
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2080815923
Short name T211
Test name
Test status
Simulation time 183890039886 ps
CPU time 237.57 seconds
Started Jun 09 02:28:58 PM PDT 24
Finished Jun 09 02:32:56 PM PDT 24
Peak memory 253984 kb
Host smart-801908ea-a68a-469d-9b50-d738e45413b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080815923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2080815923
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.237397247
Short name T192
Test name
Test status
Simulation time 153517766290 ps
CPU time 168.42 seconds
Started Jun 09 02:29:00 PM PDT 24
Finished Jun 09 02:31:49 PM PDT 24
Peak memory 252308 kb
Host smart-38be6c62-d14a-4f3e-a0b8-ea8b66d78cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237397247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.237397247
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3830384022
Short name T20
Test name
Test status
Simulation time 15932473581 ps
CPU time 127.96 seconds
Started Jun 09 02:28:58 PM PDT 24
Finished Jun 09 02:31:06 PM PDT 24
Peak memory 249136 kb
Host smart-00c13783-fced-41a4-be61-16ecbca09a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830384022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3830384022
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1107790968
Short name T283
Test name
Test status
Simulation time 2278618367 ps
CPU time 9.74 seconds
Started Jun 09 02:28:57 PM PDT 24
Finished Jun 09 02:29:07 PM PDT 24
Peak memory 240788 kb
Host smart-882efe37-ed35-4f2e-8b89-3542cf9fd851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107790968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1107790968
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.876341864
Short name T975
Test name
Test status
Simulation time 2261468614 ps
CPU time 30.8 seconds
Started Jun 09 02:29:00 PM PDT 24
Finished Jun 09 02:29:31 PM PDT 24
Peak memory 224356 kb
Host smart-1f17cb07-9fe5-4441-abe9-40f6e4b302b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876341864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.876341864
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3680168826
Short name T173
Test name
Test status
Simulation time 17786018321 ps
CPU time 36.87 seconds
Started Jun 09 02:28:59 PM PDT 24
Finished Jun 09 02:29:36 PM PDT 24
Peak memory 248984 kb
Host smart-6b867fba-6738-40a2-aa63-0196a710de94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680168826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3680168826
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3266890766
Short name T905
Test name
Test status
Simulation time 114131365 ps
CPU time 1.07 seconds
Started Jun 09 02:28:59 PM PDT 24
Finished Jun 09 02:29:00 PM PDT 24
Peak memory 216368 kb
Host smart-4f188a00-2b29-4edd-b53f-4b3f9c98cb29
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266890766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3266890766
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2538668162
Short name T168
Test name
Test status
Simulation time 3352199348 ps
CPU time 13.37 seconds
Started Jun 09 02:29:06 PM PDT 24
Finished Jun 09 02:29:20 PM PDT 24
Peak memory 232548 kb
Host smart-f067916b-8e07-45d5-9205-fc1f61d3beb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538668162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2538668162
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1690995031
Short name T27
Test name
Test status
Simulation time 1086461281 ps
CPU time 5.64 seconds
Started Jun 09 02:29:03 PM PDT 24
Finished Jun 09 02:29:09 PM PDT 24
Peak memory 232512 kb
Host smart-d1703b32-fc2f-4ae9-b936-489e6e4a2abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690995031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1690995031
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4257456085
Short name T628
Test name
Test status
Simulation time 1099071636 ps
CPU time 6.5 seconds
Started Jun 09 02:28:55 PM PDT 24
Finished Jun 09 02:29:02 PM PDT 24
Peak memory 222852 kb
Host smart-833ef255-bfa6-4731-8c83-6b0cd34fe5d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4257456085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4257456085
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3472603397
Short name T61
Test name
Test status
Simulation time 319629554 ps
CPU time 1.2 seconds
Started Jun 09 02:29:13 PM PDT 24
Finished Jun 09 02:29:15 PM PDT 24
Peak memory 236532 kb
Host smart-7df5dfab-fb39-4970-af6c-23aef07f8a0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472603397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3472603397
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.4005986291
Short name T425
Test name
Test status
Simulation time 19527577332 ps
CPU time 39.18 seconds
Started Jun 09 02:28:54 PM PDT 24
Finished Jun 09 02:29:34 PM PDT 24
Peak memory 219304 kb
Host smart-cd1e5480-02d6-4f2e-a90c-442187db9ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005986291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.4005986291
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.467840776
Short name T787
Test name
Test status
Simulation time 5368302849 ps
CPU time 28.91 seconds
Started Jun 09 02:29:01 PM PDT 24
Finished Jun 09 02:29:30 PM PDT 24
Peak memory 216176 kb
Host smart-ecf87f26-1e36-4ad8-9ddb-f20c2dad2bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467840776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.467840776
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3381310040
Short name T595
Test name
Test status
Simulation time 2486596148 ps
CPU time 7.34 seconds
Started Jun 09 02:28:59 PM PDT 24
Finished Jun 09 02:29:07 PM PDT 24
Peak memory 216040 kb
Host smart-61ddf37a-d0f1-4773-8fd9-4f174ee850f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381310040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3381310040
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2941993275
Short name T812
Test name
Test status
Simulation time 602495327 ps
CPU time 3.2 seconds
Started Jun 09 02:28:55 PM PDT 24
Finished Jun 09 02:28:58 PM PDT 24
Peak memory 216184 kb
Host smart-02ef6495-714b-489d-9190-49fcbdffcb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941993275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2941993275
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1674332284
Short name T320
Test name
Test status
Simulation time 393483831 ps
CPU time 1.06 seconds
Started Jun 09 02:29:01 PM PDT 24
Finished Jun 09 02:29:03 PM PDT 24
Peak memory 206080 kb
Host smart-f8af66bd-7545-41a1-a935-f213e40537e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674332284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1674332284
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.922657682
Short name T877
Test name
Test status
Simulation time 22564962830 ps
CPU time 18.82 seconds
Started Jun 09 02:29:03 PM PDT 24
Finished Jun 09 02:29:23 PM PDT 24
Peak memory 232564 kb
Host smart-0bd405cd-763b-48de-b2c4-ba33691c20bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922657682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.922657682
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3790047478
Short name T632
Test name
Test status
Simulation time 659160028 ps
CPU time 3.45 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:33 PM PDT 24
Peak memory 224340 kb
Host smart-3c9de115-25b5-41b2-b8d3-efd7b4786fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790047478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3790047478
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3911809560
Short name T343
Test name
Test status
Simulation time 7395623301 ps
CPU time 73.7 seconds
Started Jun 09 02:29:32 PM PDT 24
Finished Jun 09 02:30:46 PM PDT 24
Peak memory 249984 kb
Host smart-74d885f4-128f-4ac4-9205-24bb27a7b62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911809560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3911809560
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2865937595
Short name T10
Test name
Test status
Simulation time 21856928877 ps
CPU time 119.13 seconds
Started Jun 09 02:29:28 PM PDT 24
Finished Jun 09 02:31:27 PM PDT 24
Peak memory 249048 kb
Host smart-994ae939-5937-456d-be0e-87b1bc7cba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865937595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2865937595
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.4207291814
Short name T293
Test name
Test status
Simulation time 23172186503 ps
CPU time 229.23 seconds
Started Jun 09 02:29:19 PM PDT 24
Finished Jun 09 02:33:09 PM PDT 24
Peak memory 252452 kb
Host smart-cd368605-2720-497e-96ee-ac426ce39bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207291814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.4207291814
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2872940772
Short name T476
Test name
Test status
Simulation time 1290364872 ps
CPU time 13 seconds
Started Jun 09 02:29:23 PM PDT 24
Finished Jun 09 02:29:37 PM PDT 24
Peak memory 224276 kb
Host smart-a6f96446-037d-4eaf-b0bd-85068fd448d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872940772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2872940772
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2326651234
Short name T549
Test name
Test status
Simulation time 205224632 ps
CPU time 5.38 seconds
Started Jun 09 02:29:26 PM PDT 24
Finished Jun 09 02:29:32 PM PDT 24
Peak memory 226888 kb
Host smart-3311805b-2f44-4259-8553-7f45f7179b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326651234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2326651234
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2707232269
Short name T215
Test name
Test status
Simulation time 786019918 ps
CPU time 4.28 seconds
Started Jun 09 02:29:21 PM PDT 24
Finished Jun 09 02:29:25 PM PDT 24
Peak memory 224356 kb
Host smart-5ccdf292-e123-4d21-bbb4-5f5fa6b485e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707232269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2707232269
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3876768535
Short name T837
Test name
Test status
Simulation time 3219561582 ps
CPU time 11.09 seconds
Started Jun 09 02:29:27 PM PDT 24
Finished Jun 09 02:29:38 PM PDT 24
Peak memory 232624 kb
Host smart-673dcdb2-77d6-461b-8afa-c57c8cfc3141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876768535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3876768535
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3420559566
Short name T759
Test name
Test status
Simulation time 3588544815 ps
CPU time 9.88 seconds
Started Jun 09 02:29:14 PM PDT 24
Finished Jun 09 02:29:24 PM PDT 24
Peak memory 218480 kb
Host smart-6889f3ad-2287-4c4d-ac69-237d5d2fb771
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3420559566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3420559566
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.169604299
Short name T222
Test name
Test status
Simulation time 11406206278 ps
CPU time 183.32 seconds
Started Jun 09 02:29:19 PM PDT 24
Finished Jun 09 02:32:23 PM PDT 24
Peak memory 249040 kb
Host smart-ca80fe92-065b-4da5-a63d-893f9504417a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169604299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.169604299
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2986033525
Short name T580
Test name
Test status
Simulation time 4247834187 ps
CPU time 6.5 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:36 PM PDT 24
Peak memory 216320 kb
Host smart-46be9c3e-3dcf-44b9-a7e7-1fb0c5b91f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986033525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2986033525
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.489280432
Short name T334
Test name
Test status
Simulation time 9378208784 ps
CPU time 8.73 seconds
Started Jun 09 02:29:12 PM PDT 24
Finished Jun 09 02:29:21 PM PDT 24
Peak memory 216112 kb
Host smart-90ed96ca-6e09-4bc8-8804-95a92fada643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489280432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.489280432
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.668990776
Short name T417
Test name
Test status
Simulation time 70222426 ps
CPU time 1.37 seconds
Started Jun 09 02:29:21 PM PDT 24
Finished Jun 09 02:29:22 PM PDT 24
Peak memory 207812 kb
Host smart-c55da4fc-3e14-4cba-b02c-6ded9c8216a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668990776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.668990776
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3328931101
Short name T326
Test name
Test status
Simulation time 47951788 ps
CPU time 0.68 seconds
Started Jun 09 02:29:12 PM PDT 24
Finished Jun 09 02:29:13 PM PDT 24
Peak memory 205608 kb
Host smart-89a78e18-38c6-4543-8838-f05691342d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328931101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3328931101
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1239923379
Short name T655
Test name
Test status
Simulation time 896172185 ps
CPU time 4.57 seconds
Started Jun 09 02:29:12 PM PDT 24
Finished Jun 09 02:29:17 PM PDT 24
Peak memory 224336 kb
Host smart-685c5701-a2ca-4827-a006-fde025a285ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239923379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1239923379
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3136848663
Short name T693
Test name
Test status
Simulation time 28229095 ps
CPU time 0.73 seconds
Started Jun 09 02:29:30 PM PDT 24
Finished Jun 09 02:29:31 PM PDT 24
Peak memory 204544 kb
Host smart-500d53ee-c3ee-4485-ac74-ddfd8070f258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136848663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3136848663
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3068315347
Short name T637
Test name
Test status
Simulation time 1843972314 ps
CPU time 11.48 seconds
Started Jun 09 02:29:32 PM PDT 24
Finished Jun 09 02:29:44 PM PDT 24
Peak memory 232536 kb
Host smart-8ff61827-edde-4bf8-925d-93f7ca2d2d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068315347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3068315347
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2761564566
Short name T116
Test name
Test status
Simulation time 156686973 ps
CPU time 0.77 seconds
Started Jun 09 02:29:22 PM PDT 24
Finished Jun 09 02:29:23 PM PDT 24
Peak memory 206244 kb
Host smart-cfb1684e-da63-4192-a6c8-1753713df8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761564566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2761564566
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1031368880
Short name T25
Test name
Test status
Simulation time 234200184750 ps
CPU time 165.63 seconds
Started Jun 09 02:29:30 PM PDT 24
Finished Jun 09 02:32:16 PM PDT 24
Peak memory 251844 kb
Host smart-14fe43bf-1f23-4f48-bdcb-1669c84d759f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031368880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1031368880
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3145123930
Short name T46
Test name
Test status
Simulation time 49855215 ps
CPU time 0.82 seconds
Started Jun 09 02:29:37 PM PDT 24
Finished Jun 09 02:29:38 PM PDT 24
Peak memory 216756 kb
Host smart-fbfab9a2-56d5-4109-b25c-279eaf059682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145123930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3145123930
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1579406410
Short name T778
Test name
Test status
Simulation time 27483907142 ps
CPU time 240.93 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:33:30 PM PDT 24
Peak memory 265428 kb
Host smart-69c2a47c-266b-4840-95a0-9170da58c7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579406410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1579406410
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3707347568
Short name T841
Test name
Test status
Simulation time 258454467 ps
CPU time 2.58 seconds
Started Jun 09 02:29:31 PM PDT 24
Finished Jun 09 02:29:34 PM PDT 24
Peak memory 224312 kb
Host smart-cc272922-3011-44e6-85f1-bf8f43a71d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707347568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3707347568
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2516996185
Short name T839
Test name
Test status
Simulation time 51561394 ps
CPU time 2.22 seconds
Started Jun 09 02:29:39 PM PDT 24
Finished Jun 09 02:29:42 PM PDT 24
Peak memory 224276 kb
Host smart-8d89eb2a-116d-4010-92d1-c17a3e95e47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516996185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2516996185
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3272922477
Short name T574
Test name
Test status
Simulation time 262380314 ps
CPU time 3.29 seconds
Started Jun 09 02:29:30 PM PDT 24
Finished Jun 09 02:29:34 PM PDT 24
Peak memory 232560 kb
Host smart-b612a544-3d7b-48ae-b662-479bbc26ddf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272922477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3272922477
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2696595256
Short name T859
Test name
Test status
Simulation time 25506815 ps
CPU time 1.09 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:30 PM PDT 24
Peak memory 216344 kb
Host smart-36a425fb-69d3-4a6a-a2c2-1e0f6159f533
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696595256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2696595256
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2604561502
Short name T567
Test name
Test status
Simulation time 869107415 ps
CPU time 3.25 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:38 PM PDT 24
Peak memory 232516 kb
Host smart-2d011321-4ab4-43ac-beca-794b90176c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604561502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2604561502
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3850350334
Short name T150
Test name
Test status
Simulation time 1561743072 ps
CPU time 10.78 seconds
Started Jun 09 02:29:13 PM PDT 24
Finished Jun 09 02:29:24 PM PDT 24
Peak memory 240640 kb
Host smart-32c7a2ea-c3ac-49b5-8904-9a375fdab801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850350334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3850350334
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.183584552
Short name T485
Test name
Test status
Simulation time 292382085 ps
CPU time 3.61 seconds
Started Jun 09 02:29:32 PM PDT 24
Finished Jun 09 02:29:36 PM PDT 24
Peak memory 222676 kb
Host smart-b6566165-d279-4d4d-a0b8-efaa917509eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=183584552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.183584552
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1984030008
Short name T127
Test name
Test status
Simulation time 55136373597 ps
CPU time 431.44 seconds
Started Jun 09 02:29:18 PM PDT 24
Finished Jun 09 02:36:30 PM PDT 24
Peak memory 265000 kb
Host smart-05d4c3df-1613-4739-bf90-e51e108117e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984030008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1984030008
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3568835801
Short name T456
Test name
Test status
Simulation time 6071872541 ps
CPU time 21.95 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:52 PM PDT 24
Peak memory 216156 kb
Host smart-ec492964-4faf-4846-bbbb-9dc801723af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568835801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3568835801
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.876375344
Short name T526
Test name
Test status
Simulation time 1338787332 ps
CPU time 5.15 seconds
Started Jun 09 02:29:12 PM PDT 24
Finished Jun 09 02:29:17 PM PDT 24
Peak memory 216060 kb
Host smart-a0d67bb8-d096-481e-8081-a9f4264999e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876375344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.876375344
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1288021422
Short name T688
Test name
Test status
Simulation time 21924632 ps
CPU time 1.27 seconds
Started Jun 09 02:29:26 PM PDT 24
Finished Jun 09 02:29:27 PM PDT 24
Peak memory 216072 kb
Host smart-3ed997fa-e3cd-40f5-b1ec-3817ea592012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288021422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1288021422
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3458100168
Short name T699
Test name
Test status
Simulation time 69835128 ps
CPU time 0.8 seconds
Started Jun 09 02:29:23 PM PDT 24
Finished Jun 09 02:29:24 PM PDT 24
Peak memory 205596 kb
Host smart-ceadefd7-504e-4d65-bd26-79fa5abfdc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458100168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3458100168
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3100230282
Short name T473
Test name
Test status
Simulation time 3541345494 ps
CPU time 15.97 seconds
Started Jun 09 02:29:33 PM PDT 24
Finished Jun 09 02:29:50 PM PDT 24
Peak memory 224420 kb
Host smart-c211bad8-3250-4ed4-8478-75f157790422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100230282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3100230282
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1423635235
Short name T571
Test name
Test status
Simulation time 18796567 ps
CPU time 0.7 seconds
Started Jun 09 02:29:39 PM PDT 24
Finished Jun 09 02:29:40 PM PDT 24
Peak memory 205132 kb
Host smart-f69cfc19-eb2a-4450-b02a-36c11fabd419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423635235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1423635235
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1247675430
Short name T185
Test name
Test status
Simulation time 46045735 ps
CPU time 2.48 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:32 PM PDT 24
Peak memory 232720 kb
Host smart-19561afa-6acf-4b9a-af7b-819a3b011dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247675430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1247675430
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.696319483
Short name T504
Test name
Test status
Simulation time 257310635 ps
CPU time 0.79 seconds
Started Jun 09 02:29:30 PM PDT 24
Finished Jun 09 02:29:31 PM PDT 24
Peak memory 206228 kb
Host smart-d9fcd1e2-1da3-4fca-a0bb-126e88a806f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696319483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.696319483
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1521159223
Short name T492
Test name
Test status
Simulation time 26628696588 ps
CPU time 186.32 seconds
Started Jun 09 02:29:18 PM PDT 24
Finished Jun 09 02:32:25 PM PDT 24
Peak memory 240796 kb
Host smart-0efdda26-b7f9-4c68-872f-cec580791ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521159223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1521159223
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1803692095
Short name T206
Test name
Test status
Simulation time 125228044002 ps
CPU time 590.15 seconds
Started Jun 09 02:29:38 PM PDT 24
Finished Jun 09 02:39:28 PM PDT 24
Peak memory 256936 kb
Host smart-7fb07161-47ee-4bb1-9272-9fa3a6c7cc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803692095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1803692095
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1516605247
Short name T917
Test name
Test status
Simulation time 13965272077 ps
CPU time 92.86 seconds
Started Jun 09 02:29:32 PM PDT 24
Finished Jun 09 02:31:05 PM PDT 24
Peak memory 254116 kb
Host smart-2ee42d2d-56ba-47e8-8a19-ad9e1d19dd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516605247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1516605247
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.4199634123
Short name T329
Test name
Test status
Simulation time 2314600771 ps
CPU time 10.61 seconds
Started Jun 09 02:29:31 PM PDT 24
Finished Jun 09 02:29:42 PM PDT 24
Peak memory 236600 kb
Host smart-11e4b92d-33f2-46de-89e8-d8af5544e4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199634123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.4199634123
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2516770922
Short name T619
Test name
Test status
Simulation time 1399224657 ps
CPU time 6.63 seconds
Started Jun 09 02:29:33 PM PDT 24
Finished Jun 09 02:29:40 PM PDT 24
Peak memory 232492 kb
Host smart-90b77cf7-3ce4-492a-82b3-8ac98001cee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516770922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2516770922
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.429149816
Short name T751
Test name
Test status
Simulation time 7304504638 ps
CPU time 65.18 seconds
Started Jun 09 02:29:27 PM PDT 24
Finished Jun 09 02:30:33 PM PDT 24
Peak memory 240608 kb
Host smart-2342e3ec-cafc-4dc2-a9a3-5a72ce0f505e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429149816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.429149816
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1010274987
Short name T376
Test name
Test status
Simulation time 45750106 ps
CPU time 0.98 seconds
Started Jun 09 02:29:38 PM PDT 24
Finished Jun 09 02:29:40 PM PDT 24
Peak memory 217624 kb
Host smart-49ddba92-8bee-4c65-a484-8932aeb19896
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010274987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1010274987
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3589613771
Short name T636
Test name
Test status
Simulation time 21704468644 ps
CPU time 17.41 seconds
Started Jun 09 02:29:49 PM PDT 24
Finished Jun 09 02:30:07 PM PDT 24
Peak memory 232620 kb
Host smart-ad5616da-474b-4d12-abe0-1a616b954930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589613771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3589613771
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.350123548
Short name T686
Test name
Test status
Simulation time 2815761950 ps
CPU time 8.02 seconds
Started Jun 09 02:29:27 PM PDT 24
Finished Jun 09 02:29:35 PM PDT 24
Peak memory 232612 kb
Host smart-a5503aee-8a65-4396-95eb-ae6edf5e1592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350123548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.350123548
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2055113665
Short name T410
Test name
Test status
Simulation time 2141602648 ps
CPU time 8.77 seconds
Started Jun 09 02:29:15 PM PDT 24
Finished Jun 09 02:29:29 PM PDT 24
Peak memory 218580 kb
Host smart-dbf47b58-b80e-4631-af6e-65b780076a9e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2055113665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2055113665
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1304875652
Short name T958
Test name
Test status
Simulation time 517872180 ps
CPU time 0.95 seconds
Started Jun 09 02:29:26 PM PDT 24
Finished Jun 09 02:29:28 PM PDT 24
Peak memory 206768 kb
Host smart-19c44243-8038-464c-a88d-df9dcef1c8f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304875652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1304875652
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.206338920
Short name T547
Test name
Test status
Simulation time 793150537 ps
CPU time 4.53 seconds
Started Jun 09 02:29:30 PM PDT 24
Finished Jun 09 02:29:35 PM PDT 24
Peak memory 216052 kb
Host smart-66b30aaf-15b8-4572-a387-6d206a5ae06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206338920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.206338920
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3251867607
Short name T386
Test name
Test status
Simulation time 5528188392 ps
CPU time 19.99 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 216044 kb
Host smart-2c9fde9f-5742-4220-9d6d-11bec6d81b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251867607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3251867607
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3412974386
Short name T811
Test name
Test status
Simulation time 163153462 ps
CPU time 1.02 seconds
Started Jun 09 02:29:17 PM PDT 24
Finished Jun 09 02:29:18 PM PDT 24
Peak memory 207428 kb
Host smart-271f3c05-1df1-4198-8591-fc14fbc854f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412974386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3412974386
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.511465513
Short name T379
Test name
Test status
Simulation time 18725129 ps
CPU time 0.78 seconds
Started Jun 09 02:29:45 PM PDT 24
Finished Jun 09 02:29:47 PM PDT 24
Peak memory 205584 kb
Host smart-497ebb76-7d8d-40cf-963f-eb74d1be296e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511465513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.511465513
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1747772796
Short name T935
Test name
Test status
Simulation time 332690966 ps
CPU time 2.99 seconds
Started Jun 09 02:29:35 PM PDT 24
Finished Jun 09 02:29:39 PM PDT 24
Peak memory 232516 kb
Host smart-bb454e8c-8932-4174-8dc5-aa03d68b0572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747772796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1747772796
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1062440444
Short name T352
Test name
Test status
Simulation time 19161992 ps
CPU time 0.73 seconds
Started Jun 09 02:29:39 PM PDT 24
Finished Jun 09 02:29:40 PM PDT 24
Peak memory 205432 kb
Host smart-c1175a6c-35a6-4656-b237-a254bbfcab33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062440444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1062440444
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1184412704
Short name T664
Test name
Test status
Simulation time 939507464 ps
CPU time 5.67 seconds
Started Jun 09 02:29:50 PM PDT 24
Finished Jun 09 02:29:56 PM PDT 24
Peak memory 232480 kb
Host smart-1d573f1e-eafa-4d13-b988-a9b22a996171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184412704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1184412704
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1409003730
Short name T813
Test name
Test status
Simulation time 44149187 ps
CPU time 0.78 seconds
Started Jun 09 02:29:33 PM PDT 24
Finished Jun 09 02:29:34 PM PDT 24
Peak memory 206232 kb
Host smart-e46136e7-d7c2-4c8b-9196-0caf30d0401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409003730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1409003730
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4083823938
Short name T255
Test name
Test status
Simulation time 37670290873 ps
CPU time 151.04 seconds
Started Jun 09 02:29:45 PM PDT 24
Finished Jun 09 02:32:16 PM PDT 24
Peak memory 248976 kb
Host smart-420ee1e9-ddd7-44dc-82f0-6629d1cf94f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083823938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4083823938
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2829799795
Short name T297
Test name
Test status
Simulation time 3808246531 ps
CPU time 75.54 seconds
Started Jun 09 02:29:39 PM PDT 24
Finished Jun 09 02:30:55 PM PDT 24
Peak memory 249056 kb
Host smart-ec08414b-64c7-4266-b75a-96447103c7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829799795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2829799795
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2784887225
Short name T509
Test name
Test status
Simulation time 27684753503 ps
CPU time 237.76 seconds
Started Jun 09 02:29:39 PM PDT 24
Finished Jun 09 02:33:37 PM PDT 24
Peak memory 249860 kb
Host smart-3cdb82f2-29d9-488d-85bb-5d7191f18d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784887225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2784887225
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.864577815
Short name T287
Test name
Test status
Simulation time 470222514 ps
CPU time 8.45 seconds
Started Jun 09 02:29:40 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 232520 kb
Host smart-8e8f49e0-92a9-4010-bb03-b7da12a97504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864577815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.864577815
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.216819436
Short name T541
Test name
Test status
Simulation time 609083718 ps
CPU time 2.77 seconds
Started Jun 09 02:29:35 PM PDT 24
Finished Jun 09 02:29:38 PM PDT 24
Peak memory 224276 kb
Host smart-b4585904-7c96-4487-a030-7d2652e237b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216819436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.216819436
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3905771817
Short name T746
Test name
Test status
Simulation time 11334429115 ps
CPU time 118.24 seconds
Started Jun 09 02:29:31 PM PDT 24
Finished Jun 09 02:31:30 PM PDT 24
Peak memory 240696 kb
Host smart-d4f9e554-c6b9-4005-b8e8-053581d36e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905771817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3905771817
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.127027112
Short name T827
Test name
Test status
Simulation time 49105365 ps
CPU time 1.08 seconds
Started Jun 09 02:29:28 PM PDT 24
Finished Jun 09 02:29:29 PM PDT 24
Peak memory 216376 kb
Host smart-f38d73d1-eecc-4367-a00d-3bfe1f53ba2c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127027112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.127027112
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2479690479
Short name T708
Test name
Test status
Simulation time 34034461813 ps
CPU time 24.54 seconds
Started Jun 09 02:29:35 PM PDT 24
Finished Jun 09 02:30:00 PM PDT 24
Peak memory 240152 kb
Host smart-45f1502e-1719-449c-89c6-4f88a775f9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479690479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2479690479
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3103511812
Short name T434
Test name
Test status
Simulation time 481475185 ps
CPU time 8.18 seconds
Started Jun 09 02:29:41 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 232536 kb
Host smart-177e60a9-b8c9-4bf8-8eb3-7d98e3e5fa86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103511812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3103511812
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.291730415
Short name T496
Test name
Test status
Simulation time 2673111290 ps
CPU time 5.98 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:35 PM PDT 24
Peak memory 220124 kb
Host smart-01ab5c65-a1d1-4041-92e4-de7adfa6ca17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=291730415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.291730415
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.4130260649
Short name T914
Test name
Test status
Simulation time 220850641 ps
CPU time 1.04 seconds
Started Jun 09 02:29:38 PM PDT 24
Finished Jun 09 02:29:40 PM PDT 24
Peak memory 206588 kb
Host smart-c39e1260-3e4d-4961-b6d5-97d1b5e237e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130260649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.4130260649
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1251617487
Short name T484
Test name
Test status
Simulation time 1054760197 ps
CPU time 6.19 seconds
Started Jun 09 02:29:32 PM PDT 24
Finished Jun 09 02:29:38 PM PDT 24
Peak memory 216088 kb
Host smart-cbfb4f67-d791-4fcb-ba03-35e275bc7cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251617487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1251617487
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.697926994
Short name T408
Test name
Test status
Simulation time 29817432923 ps
CPU time 23.57 seconds
Started Jun 09 02:29:35 PM PDT 24
Finished Jun 09 02:29:59 PM PDT 24
Peak memory 216084 kb
Host smart-897c935f-065b-4499-a763-198cccc1fc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697926994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.697926994
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3029226015
Short name T556
Test name
Test status
Simulation time 104618292 ps
CPU time 2.22 seconds
Started Jun 09 02:29:37 PM PDT 24
Finished Jun 09 02:29:40 PM PDT 24
Peak memory 215976 kb
Host smart-240085e4-1560-48d9-89d2-30b612e7c972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029226015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3029226015
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1482986691
Short name T312
Test name
Test status
Simulation time 463629259 ps
CPU time 0.86 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:30 PM PDT 24
Peak memory 205600 kb
Host smart-6a944f94-eb93-48d0-a00a-92d143adace3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482986691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1482986691
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1303661013
Short name T459
Test name
Test status
Simulation time 6786986030 ps
CPU time 9.34 seconds
Started Jun 09 02:29:33 PM PDT 24
Finished Jun 09 02:29:43 PM PDT 24
Peak memory 232580 kb
Host smart-6e31f34f-2ee3-4dc8-b56e-26ed870117db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303661013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1303661013
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1342134163
Short name T342
Test name
Test status
Simulation time 108787658 ps
CPU time 0.75 seconds
Started Jun 09 02:29:34 PM PDT 24
Finished Jun 09 02:29:35 PM PDT 24
Peak memory 205152 kb
Host smart-0231f844-6145-40aa-9fa0-c113c03966f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342134163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1342134163
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1974778143
Short name T548
Test name
Test status
Simulation time 585750825 ps
CPU time 2.58 seconds
Started Jun 09 02:29:37 PM PDT 24
Finished Jun 09 02:29:40 PM PDT 24
Peak memory 224344 kb
Host smart-42ff7d1c-df57-48d6-9cb1-74f9efcca426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974778143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1974778143
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.4240436771
Short name T445
Test name
Test status
Simulation time 20855692 ps
CPU time 0.82 seconds
Started Jun 09 02:29:27 PM PDT 24
Finished Jun 09 02:29:28 PM PDT 24
Peak memory 206556 kb
Host smart-5c798251-60c1-4049-be18-94d49ba3811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240436771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4240436771
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2893111737
Short name T598
Test name
Test status
Simulation time 3433945934 ps
CPU time 16.34 seconds
Started Jun 09 02:29:37 PM PDT 24
Finished Jun 09 02:29:54 PM PDT 24
Peak memory 240776 kb
Host smart-96ed1a4b-8181-4cf8-977c-409e2de016b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893111737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2893111737
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.558377737
Short name T522
Test name
Test status
Simulation time 4900795910 ps
CPU time 35 seconds
Started Jun 09 02:29:30 PM PDT 24
Finished Jun 09 02:30:05 PM PDT 24
Peak memory 257184 kb
Host smart-e5eed1a2-7587-4fd3-894d-c6d26c6c5d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558377737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.558377737
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.694026414
Short name T617
Test name
Test status
Simulation time 22367729523 ps
CPU time 24.3 seconds
Started Jun 09 02:29:31 PM PDT 24
Finished Jun 09 02:29:56 PM PDT 24
Peak memory 224452 kb
Host smart-c0b3d33a-dc73-4ebf-a36c-23728812817e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694026414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.694026414
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.489295091
Short name T945
Test name
Test status
Simulation time 558115232 ps
CPU time 6.86 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:37 PM PDT 24
Peak memory 232492 kb
Host smart-51731a0f-3ff4-48ba-b7d5-b8ff5b3cdad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489295091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.489295091
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1300818408
Short name T802
Test name
Test status
Simulation time 3267415088 ps
CPU time 33.01 seconds
Started Jun 09 02:29:41 PM PDT 24
Finished Jun 09 02:30:15 PM PDT 24
Peak memory 240776 kb
Host smart-6f9a45d9-fff0-4984-a67d-aa91b14f5b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300818408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1300818408
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3834431731
Short name T972
Test name
Test status
Simulation time 74813240 ps
CPU time 1.08 seconds
Started Jun 09 02:29:42 PM PDT 24
Finished Jun 09 02:29:43 PM PDT 24
Peak memory 216344 kb
Host smart-974e9e1a-ecb1-4f07-bebc-805d498a5627
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834431731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3834431731
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2931380310
Short name T835
Test name
Test status
Simulation time 273835729 ps
CPU time 5.26 seconds
Started Jun 09 02:29:35 PM PDT 24
Finished Jun 09 02:29:40 PM PDT 24
Peak memory 224236 kb
Host smart-851520e1-337a-4040-999d-ce78d6b4e2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931380310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2931380310
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2254809410
Short name T703
Test name
Test status
Simulation time 2310332855 ps
CPU time 6.19 seconds
Started Jun 09 02:29:27 PM PDT 24
Finished Jun 09 02:29:33 PM PDT 24
Peak memory 232808 kb
Host smart-c9be2b41-d2ef-40ea-9c84-339ec3426a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254809410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2254809410
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2787081157
Short name T6
Test name
Test status
Simulation time 1611354323 ps
CPU time 16.53 seconds
Started Jun 09 02:29:32 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 222856 kb
Host smart-02437bd1-94a5-414c-ab1e-9839c74b3b89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2787081157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2787081157
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1098179553
Short name T220
Test name
Test status
Simulation time 27236857402 ps
CPU time 245.13 seconds
Started Jun 09 02:29:32 PM PDT 24
Finished Jun 09 02:33:37 PM PDT 24
Peak memory 248068 kb
Host smart-2f4aa5eb-85a4-4fd0-872e-d5a2d9f2b7d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098179553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1098179553
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3105271113
Short name T16
Test name
Test status
Simulation time 4537517860 ps
CPU time 10.65 seconds
Started Jun 09 02:29:38 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 216128 kb
Host smart-2f7a55a1-2acc-4ff9-939b-4455c5d45cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105271113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3105271113
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.704432191
Short name T449
Test name
Test status
Simulation time 2376701095 ps
CPU time 9.12 seconds
Started Jun 09 02:29:30 PM PDT 24
Finished Jun 09 02:29:39 PM PDT 24
Peak memory 216092 kb
Host smart-5d9479c0-a270-47f1-a821-0f7c3754e04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704432191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.704432191
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2516314564
Short name T583
Test name
Test status
Simulation time 226757989 ps
CPU time 1.07 seconds
Started Jun 09 02:29:43 PM PDT 24
Finished Jun 09 02:29:44 PM PDT 24
Peak memory 206788 kb
Host smart-71d0aae8-c976-459e-a909-368640fbad56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516314564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2516314564
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.332696985
Short name T321
Test name
Test status
Simulation time 205264659 ps
CPU time 0.86 seconds
Started Jun 09 02:29:30 PM PDT 24
Finished Jun 09 02:29:31 PM PDT 24
Peak memory 205752 kb
Host smart-6fa82fc3-fd5d-459b-bfc2-6ba46b777730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332696985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.332696985
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1521491889
Short name T897
Test name
Test status
Simulation time 26317573968 ps
CPU time 20 seconds
Started Jun 09 02:29:38 PM PDT 24
Finished Jun 09 02:29:58 PM PDT 24
Peak memory 232584 kb
Host smart-59dd4203-b9f3-4b20-b629-c3ac82aa8bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521491889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1521491889
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3510522546
Short name T878
Test name
Test status
Simulation time 34005403 ps
CPU time 0.69 seconds
Started Jun 09 02:29:33 PM PDT 24
Finished Jun 09 02:29:34 PM PDT 24
Peak memory 205176 kb
Host smart-d9ae06f4-32d5-42a1-b23c-2c9365f72090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510522546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3510522546
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1037866354
Short name T968
Test name
Test status
Simulation time 298143771 ps
CPU time 3.33 seconds
Started Jun 09 02:29:46 PM PDT 24
Finished Jun 09 02:29:50 PM PDT 24
Peak memory 232480 kb
Host smart-2af81905-0772-4a6a-8529-1e34ff5bb351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037866354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1037866354
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1837862001
Short name T674
Test name
Test status
Simulation time 52398165 ps
CPU time 0.9 seconds
Started Jun 09 02:29:33 PM PDT 24
Finished Jun 09 02:29:35 PM PDT 24
Peak memory 206204 kb
Host smart-7e85b0f9-e644-46cb-8071-a4a36068f72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837862001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1837862001
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3817259019
Short name T795
Test name
Test status
Simulation time 3206562920 ps
CPU time 78.05 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:30:48 PM PDT 24
Peak memory 249004 kb
Host smart-02acad14-6d3a-4c83-a8de-a1c1ad09ccd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817259019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3817259019
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1209638128
Short name T230
Test name
Test status
Simulation time 40768538632 ps
CPU time 360.12 seconds
Started Jun 09 02:29:33 PM PDT 24
Finished Jun 09 02:35:34 PM PDT 24
Peak memory 254636 kb
Host smart-ff13618e-38cb-4d08-8947-01e76fe4466f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209638128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1209638128
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1526569027
Short name T514
Test name
Test status
Simulation time 1099605642 ps
CPU time 8.57 seconds
Started Jun 09 02:29:40 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 232548 kb
Host smart-ddfc8ce8-2798-4e8a-8b4f-ee1b5a0a5836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526569027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1526569027
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3697251722
Short name T337
Test name
Test status
Simulation time 266113236 ps
CPU time 4.83 seconds
Started Jun 09 02:29:41 PM PDT 24
Finished Jun 09 02:29:46 PM PDT 24
Peak memory 227696 kb
Host smart-fa48eea0-cf3a-4f58-9788-539c2031f4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697251722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3697251722
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.967456440
Short name T724
Test name
Test status
Simulation time 2730869274 ps
CPU time 7.82 seconds
Started Jun 09 02:29:47 PM PDT 24
Finished Jun 09 02:29:55 PM PDT 24
Peak memory 232628 kb
Host smart-4c3b1393-9025-429a-b08d-565ee640023e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967456440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.967456440
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1601243992
Short name T22
Test name
Test status
Simulation time 64961754 ps
CPU time 1.08 seconds
Started Jun 09 02:29:38 PM PDT 24
Finished Jun 09 02:29:39 PM PDT 24
Peak memory 216388 kb
Host smart-cc86d116-c600-4d17-a514-2324e705dede
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601243992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1601243992
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.293598034
Short name T760
Test name
Test status
Simulation time 1404308410 ps
CPU time 6.39 seconds
Started Jun 09 02:29:46 PM PDT 24
Finished Jun 09 02:29:53 PM PDT 24
Peak memory 232524 kb
Host smart-d7d7bd12-d10c-4084-81eb-ffc1687f538e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293598034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.293598034
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3976572000
Short name T101
Test name
Test status
Simulation time 254678863 ps
CPU time 4.01 seconds
Started Jun 09 02:29:33 PM PDT 24
Finished Jun 09 02:29:38 PM PDT 24
Peak memory 232536 kb
Host smart-70afac3e-f138-41d1-9687-e3c13f31fbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976572000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3976572000
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2855478502
Short name T129
Test name
Test status
Simulation time 4473125934 ps
CPU time 17.53 seconds
Started Jun 09 02:29:43 PM PDT 24
Finished Jun 09 02:30:00 PM PDT 24
Peak memory 218800 kb
Host smart-b6f9e6e8-3292-4b66-b0ab-63898ee0516f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2855478502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2855478502
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2657472041
Short name T909
Test name
Test status
Simulation time 84540059926 ps
CPU time 24.47 seconds
Started Jun 09 02:29:35 PM PDT 24
Finished Jun 09 02:30:00 PM PDT 24
Peak memory 216548 kb
Host smart-3b959168-b1a7-4b5b-96bc-044fbf395751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657472041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2657472041
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1164074511
Short name T607
Test name
Test status
Simulation time 54750156 ps
CPU time 0.7 seconds
Started Jun 09 02:29:32 PM PDT 24
Finished Jun 09 02:29:33 PM PDT 24
Peak memory 205328 kb
Host smart-05aae935-6d78-4854-9e1d-2a7b50123671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164074511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1164074511
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2378461637
Short name T325
Test name
Test status
Simulation time 25012146 ps
CPU time 0.97 seconds
Started Jun 09 02:29:42 PM PDT 24
Finished Jun 09 02:29:44 PM PDT 24
Peak memory 206944 kb
Host smart-cf1f78f4-9843-4f6e-8c5b-3c0bde2bd51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378461637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2378461637
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2545656043
Short name T886
Test name
Test status
Simulation time 11307091 ps
CPU time 0.69 seconds
Started Jun 09 02:29:47 PM PDT 24
Finished Jun 09 02:29:48 PM PDT 24
Peak memory 205252 kb
Host smart-27f06db3-7a21-4eb8-ab1f-d529670d6a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545656043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2545656043
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2465836044
Short name T272
Test name
Test status
Simulation time 2242424865 ps
CPU time 5.56 seconds
Started Jun 09 02:29:50 PM PDT 24
Finished Jun 09 02:29:56 PM PDT 24
Peak memory 224340 kb
Host smart-ddea2c0b-932d-4ecf-8f9c-a2666d786e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465836044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2465836044
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.430729668
Short name T851
Test name
Test status
Simulation time 13780758 ps
CPU time 0.72 seconds
Started Jun 09 02:29:32 PM PDT 24
Finished Jun 09 02:29:33 PM PDT 24
Peak memory 204544 kb
Host smart-1393b65b-aeaa-438d-a061-4aa30289576a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430729668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.430729668
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2325557103
Short name T775
Test name
Test status
Simulation time 108581977 ps
CPU time 2.62 seconds
Started Jun 09 02:29:37 PM PDT 24
Finished Jun 09 02:29:40 PM PDT 24
Peak memory 224320 kb
Host smart-47dc05b0-851f-4c6b-bf65-bf859c8d5c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325557103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2325557103
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1631492497
Short name T15
Test name
Test status
Simulation time 14883977 ps
CPU time 0.76 seconds
Started Jun 09 02:29:36 PM PDT 24
Finished Jun 09 02:29:37 PM PDT 24
Peak memory 205536 kb
Host smart-63cc01d6-0b12-4846-bccf-dd70439a422b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631492497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1631492497
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.456042619
Short name T427
Test name
Test status
Simulation time 14780377 ps
CPU time 0.77 seconds
Started Jun 09 02:29:56 PM PDT 24
Finished Jun 09 02:29:57 PM PDT 24
Peak memory 215708 kb
Host smart-d6f3e1cb-53de-42ff-869b-fa6ce81914da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456042619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.456042619
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3234923108
Short name T47
Test name
Test status
Simulation time 77415709585 ps
CPU time 181.09 seconds
Started Jun 09 02:29:39 PM PDT 24
Finished Jun 09 02:32:40 PM PDT 24
Peak memory 239672 kb
Host smart-036a4671-8233-4ef7-8fe9-7548bf645a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234923108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3234923108
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2468693480
Short name T115
Test name
Test status
Simulation time 5793943855 ps
CPU time 34.89 seconds
Started Jun 09 02:29:45 PM PDT 24
Finished Jun 09 02:30:20 PM PDT 24
Peak memory 249684 kb
Host smart-1298cdf8-4950-4bcf-856e-451d290fcb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468693480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2468693480
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.308433459
Short name T755
Test name
Test status
Simulation time 1647399540 ps
CPU time 21.08 seconds
Started Jun 09 02:29:48 PM PDT 24
Finished Jun 09 02:30:09 PM PDT 24
Peak memory 224316 kb
Host smart-daa78771-a0b2-4fc3-99b2-6bb965a7c834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308433459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.308433459
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.903483070
Short name T689
Test name
Test status
Simulation time 1244722148 ps
CPU time 5.48 seconds
Started Jun 09 02:29:51 PM PDT 24
Finished Jun 09 02:30:02 PM PDT 24
Peak memory 224276 kb
Host smart-6131bdf7-414b-4f14-9697-3fd72ab88ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903483070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.903483070
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1701216884
Short name T614
Test name
Test status
Simulation time 62487704780 ps
CPU time 50.02 seconds
Started Jun 09 02:29:44 PM PDT 24
Finished Jun 09 02:30:34 PM PDT 24
Peak memory 239912 kb
Host smart-223cf547-b0cc-4f39-97e8-404628b8eb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701216884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1701216884
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2381229581
Short name T918
Test name
Test status
Simulation time 17199455 ps
CPU time 1.08 seconds
Started Jun 09 02:29:39 PM PDT 24
Finished Jun 09 02:29:40 PM PDT 24
Peak memory 216368 kb
Host smart-b557e777-5441-4913-9221-e76f50cf8f35
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381229581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2381229581
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3369691203
Short name T823
Test name
Test status
Simulation time 7231756796 ps
CPU time 18.04 seconds
Started Jun 09 02:29:34 PM PDT 24
Finished Jun 09 02:29:53 PM PDT 24
Peak memory 232592 kb
Host smart-5d64a390-c2be-43bf-aeb3-80b46a493edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369691203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3369691203
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3533039012
Short name T152
Test name
Test status
Simulation time 2147641090 ps
CPU time 4.94 seconds
Started Jun 09 02:29:31 PM PDT 24
Finished Jun 09 02:29:36 PM PDT 24
Peak memory 220156 kb
Host smart-34884954-329c-4b5a-a75a-70f7c235f95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533039012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3533039012
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.419947768
Short name T659
Test name
Test status
Simulation time 533449649 ps
CPU time 4.85 seconds
Started Jun 09 02:29:48 PM PDT 24
Finished Jun 09 02:29:54 PM PDT 24
Peak memory 222300 kb
Host smart-5b2ffa42-0be7-4791-a9a4-d0b4fea68b64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=419947768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.419947768
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2195839831
Short name T232
Test name
Test status
Simulation time 53407065544 ps
CPU time 273.11 seconds
Started Jun 09 02:29:38 PM PDT 24
Finished Jun 09 02:34:12 PM PDT 24
Peak memory 250056 kb
Host smart-ed105b1b-129f-4320-9d6a-3c3e9526bd83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195839831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2195839831
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3031736468
Short name T341
Test name
Test status
Simulation time 23150583462 ps
CPU time 34.74 seconds
Started Jun 09 02:29:39 PM PDT 24
Finished Jun 09 02:30:14 PM PDT 24
Peak memory 216176 kb
Host smart-e9286929-3e42-4d9a-9306-6406b128917c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031736468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3031736468
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.792638298
Short name T656
Test name
Test status
Simulation time 585748306 ps
CPU time 3.19 seconds
Started Jun 09 02:29:39 PM PDT 24
Finished Jun 09 02:29:43 PM PDT 24
Peak memory 216092 kb
Host smart-7218b4dd-2ff2-4847-8ef1-d7a34283c111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792638298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.792638298
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2994152659
Short name T805
Test name
Test status
Simulation time 49508080 ps
CPU time 0.75 seconds
Started Jun 09 02:29:47 PM PDT 24
Finished Jun 09 02:29:48 PM PDT 24
Peak memory 205620 kb
Host smart-056cfd40-3065-4d12-b542-e20f765b4df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994152659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2994152659
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.7592063
Short name T48
Test name
Test status
Simulation time 57953085 ps
CPU time 0.7 seconds
Started Jun 09 02:29:36 PM PDT 24
Finished Jun 09 02:29:36 PM PDT 24
Peak memory 205592 kb
Host smart-f3241675-0490-426c-a67a-475057c3c65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7592063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.7592063
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3854653155
Short name T102
Test name
Test status
Simulation time 2982572770 ps
CPU time 4.99 seconds
Started Jun 09 02:29:46 PM PDT 24
Finished Jun 09 02:29:51 PM PDT 24
Peak memory 232792 kb
Host smart-282a9a44-1fd3-46d4-95d2-a6e31317ebcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854653155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3854653155
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2454040025
Short name T854
Test name
Test status
Simulation time 37327252 ps
CPU time 0.72 seconds
Started Jun 09 02:29:33 PM PDT 24
Finished Jun 09 02:29:34 PM PDT 24
Peak memory 205148 kb
Host smart-361481cd-f3ca-4247-b492-edd8a3a7b842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454040025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2454040025
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3207916721
Short name T250
Test name
Test status
Simulation time 65213190 ps
CPU time 2.62 seconds
Started Jun 09 02:29:44 PM PDT 24
Finished Jun 09 02:29:47 PM PDT 24
Peak memory 232508 kb
Host smart-f1038ef0-6c23-472b-96ae-a04738cb6df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207916721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3207916721
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.4057473415
Short name T327
Test name
Test status
Simulation time 70189078 ps
CPU time 0.79 seconds
Started Jun 09 02:29:33 PM PDT 24
Finished Jun 09 02:29:34 PM PDT 24
Peak memory 206216 kb
Host smart-4f62f75a-6984-4f34-a1f3-21a724b7ccb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057473415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4057473415
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1767021555
Short name T650
Test name
Test status
Simulation time 18527640468 ps
CPU time 111.25 seconds
Started Jun 09 02:29:36 PM PDT 24
Finished Jun 09 02:31:27 PM PDT 24
Peak memory 272348 kb
Host smart-fb88d32f-82f6-4728-a4f6-b1f17aae0c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767021555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1767021555
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2668047545
Short name T213
Test name
Test status
Simulation time 67070207376 ps
CPU time 76.29 seconds
Started Jun 09 02:29:48 PM PDT 24
Finished Jun 09 02:31:04 PM PDT 24
Peak memory 250036 kb
Host smart-0af22bab-9dc1-45ab-81f7-0b5e7dac4ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668047545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2668047545
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2385911111
Short name T942
Test name
Test status
Simulation time 5259011823 ps
CPU time 104.92 seconds
Started Jun 09 02:29:49 PM PDT 24
Finished Jun 09 02:31:34 PM PDT 24
Peak memory 255088 kb
Host smart-94ddfcae-ad2f-42a8-84c3-8695e7257eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385911111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2385911111
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2658206920
Short name T79
Test name
Test status
Simulation time 1193019175 ps
CPU time 7.98 seconds
Started Jun 09 02:29:41 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 232524 kb
Host smart-78e4fd1f-b260-40b1-af86-e7c7171a5b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658206920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2658206920
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3518104489
Short name T5
Test name
Test status
Simulation time 1730751074 ps
CPU time 3.98 seconds
Started Jun 09 02:29:43 PM PDT 24
Finished Jun 09 02:29:48 PM PDT 24
Peak memory 232500 kb
Host smart-6974f968-7c9a-49e7-a12b-51d3a029da15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518104489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3518104489
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1516960348
Short name T727
Test name
Test status
Simulation time 9273602935 ps
CPU time 24.73 seconds
Started Jun 09 02:29:49 PM PDT 24
Finished Jun 09 02:30:14 PM PDT 24
Peak memory 232628 kb
Host smart-17d8ad27-dafb-488b-97d0-63f292f87da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516960348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1516960348
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1926542955
Short name T23
Test name
Test status
Simulation time 31779641 ps
CPU time 1.14 seconds
Started Jun 09 02:29:51 PM PDT 24
Finished Jun 09 02:29:53 PM PDT 24
Peak memory 217612 kb
Host smart-d394e732-8f66-43bf-a2d7-e89954208157
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926542955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1926542955
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2513582666
Short name T654
Test name
Test status
Simulation time 928635306 ps
CPU time 7.42 seconds
Started Jun 09 02:29:33 PM PDT 24
Finished Jun 09 02:29:40 PM PDT 24
Peak memory 232532 kb
Host smart-bf4c7451-fbad-4ed8-9d4f-cc8e6fe5c2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513582666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2513582666
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1171628498
Short name T882
Test name
Test status
Simulation time 14079130592 ps
CPU time 13.25 seconds
Started Jun 09 02:29:47 PM PDT 24
Finished Jun 09 02:30:01 PM PDT 24
Peak memory 224408 kb
Host smart-aa3d08d3-b9d3-4dd5-a7d0-a97a4bbe3214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171628498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1171628498
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1661064870
Short name T133
Test name
Test status
Simulation time 447526146 ps
CPU time 3.66 seconds
Started Jun 09 02:29:46 PM PDT 24
Finished Jun 09 02:29:50 PM PDT 24
Peak memory 220364 kb
Host smart-dd317e2a-ad0d-44a6-8191-fadcd4f64656
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1661064870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1661064870
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2391509406
Short name T125
Test name
Test status
Simulation time 12642534425 ps
CPU time 84.4 seconds
Started Jun 09 02:29:33 PM PDT 24
Finished Jun 09 02:30:58 PM PDT 24
Peak memory 265448 kb
Host smart-d5a7f18f-b330-4d95-9511-3c34fa1f5bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391509406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2391509406
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.175536921
Short name T801
Test name
Test status
Simulation time 2018775259 ps
CPU time 12.5 seconds
Started Jun 09 02:29:44 PM PDT 24
Finished Jun 09 02:29:56 PM PDT 24
Peak memory 216092 kb
Host smart-66b2d960-c04c-41a6-b07a-793c124ee37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175536921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.175536921
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.117966577
Short name T960
Test name
Test status
Simulation time 3627641239 ps
CPU time 11.18 seconds
Started Jun 09 02:29:48 PM PDT 24
Finished Jun 09 02:29:59 PM PDT 24
Peak memory 216068 kb
Host smart-accf240e-7adc-4f97-9032-7d2add132763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117966577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.117966577
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.203059339
Short name T814
Test name
Test status
Simulation time 94034641 ps
CPU time 1.97 seconds
Started Jun 09 02:29:38 PM PDT 24
Finished Jun 09 02:29:41 PM PDT 24
Peak memory 216048 kb
Host smart-64175cfd-42d8-423b-9a40-894ecab6fa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203059339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.203059339
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3773236056
Short name T678
Test name
Test status
Simulation time 142139924 ps
CPU time 0.73 seconds
Started Jun 09 02:29:33 PM PDT 24
Finished Jun 09 02:29:34 PM PDT 24
Peak memory 205620 kb
Host smart-3d4d82b9-bc94-4aa6-9cdc-378065cf21f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773236056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3773236056
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1013473310
Short name T788
Test name
Test status
Simulation time 9589116552 ps
CPU time 12.67 seconds
Started Jun 09 02:29:46 PM PDT 24
Finished Jun 09 02:29:59 PM PDT 24
Peak memory 232636 kb
Host smart-49b9e893-a1b3-455b-aa56-5baf921c9e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013473310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1013473310
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3947875376
Short name T560
Test name
Test status
Simulation time 18093855 ps
CPU time 0.69 seconds
Started Jun 09 02:29:48 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 205524 kb
Host smart-a0531621-88fa-4499-be90-e1297ea36fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947875376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3947875376
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3241609371
Short name T103
Test name
Test status
Simulation time 4145557054 ps
CPU time 8.22 seconds
Started Jun 09 02:29:52 PM PDT 24
Finished Jun 09 02:30:00 PM PDT 24
Peak memory 232560 kb
Host smart-a30fd644-d12d-48eb-aea4-9ba86d83b40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241609371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3241609371
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1603103786
Short name T707
Test name
Test status
Simulation time 41735777 ps
CPU time 0.77 seconds
Started Jun 09 02:30:02 PM PDT 24
Finished Jun 09 02:30:03 PM PDT 24
Peak memory 205536 kb
Host smart-1a08078a-7105-434c-a7a5-736405de458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603103786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1603103786
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3842587807
Short name T409
Test name
Test status
Simulation time 4528825106 ps
CPU time 21.7 seconds
Started Jun 09 02:29:45 PM PDT 24
Finished Jun 09 02:30:07 PM PDT 24
Peak memory 240780 kb
Host smart-e83fa54e-ad0f-41a5-a3fa-f560bbb0bbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842587807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3842587807
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3317916733
Short name T224
Test name
Test status
Simulation time 47282911414 ps
CPU time 447.53 seconds
Started Jun 09 02:29:51 PM PDT 24
Finished Jun 09 02:37:19 PM PDT 24
Peak memory 249072 kb
Host smart-323c98df-a078-4f67-a7c2-455f0e655c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317916733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3317916733
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3162527983
Short name T229
Test name
Test status
Simulation time 41669529735 ps
CPU time 96.97 seconds
Started Jun 09 02:29:34 PM PDT 24
Finished Jun 09 02:31:12 PM PDT 24
Peak memory 249044 kb
Host smart-6e0ff1d4-0bb0-42db-8bc7-dc9d775d4b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162527983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3162527983
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1015926897
Short name T740
Test name
Test status
Simulation time 22888733440 ps
CPU time 41.86 seconds
Started Jun 09 02:29:33 PM PDT 24
Finished Jun 09 02:30:15 PM PDT 24
Peak memory 232552 kb
Host smart-fd0a308d-7f61-47c2-bf62-5e215e627d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015926897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1015926897
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2895538721
Short name T600
Test name
Test status
Simulation time 5988082272 ps
CPU time 15.79 seconds
Started Jun 09 02:29:51 PM PDT 24
Finished Jun 09 02:30:07 PM PDT 24
Peak memory 232576 kb
Host smart-3f0d1753-d35d-4bb1-9f03-332e24803d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895538721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2895538721
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1539699981
Short name T881
Test name
Test status
Simulation time 308242658 ps
CPU time 5.12 seconds
Started Jun 09 02:29:40 PM PDT 24
Finished Jun 09 02:29:46 PM PDT 24
Peak memory 232568 kb
Host smart-cbf3dc40-b67d-4303-b357-86cca947d238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539699981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1539699981
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1062550478
Short name T858
Test name
Test status
Simulation time 50570264 ps
CPU time 1.12 seconds
Started Jun 09 02:30:04 PM PDT 24
Finished Jun 09 02:30:05 PM PDT 24
Peak memory 216376 kb
Host smart-660731c0-833e-4efb-8140-fc50e8261470
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062550478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1062550478
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4161262769
Short name T395
Test name
Test status
Simulation time 5042212593 ps
CPU time 17.01 seconds
Started Jun 09 02:29:46 PM PDT 24
Finished Jun 09 02:30:03 PM PDT 24
Peak memory 232580 kb
Host smart-756efe6a-ab77-4414-87c9-b699c27e8b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161262769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4161262769
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1449443954
Short name T807
Test name
Test status
Simulation time 2862980354 ps
CPU time 10.44 seconds
Started Jun 09 02:29:58 PM PDT 24
Finished Jun 09 02:30:09 PM PDT 24
Peak memory 232604 kb
Host smart-44139de8-f67d-4ed9-8954-70eeace4b1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449443954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1449443954
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1479213142
Short name T806
Test name
Test status
Simulation time 282529440 ps
CPU time 3.81 seconds
Started Jun 09 02:29:32 PM PDT 24
Finished Jun 09 02:29:36 PM PDT 24
Peak memory 222304 kb
Host smart-31dc6e34-4a56-4bae-9a0d-80fcee327ffd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1479213142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1479213142
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.175240273
Short name T922
Test name
Test status
Simulation time 5175342743 ps
CPU time 15.01 seconds
Started Jun 09 02:29:49 PM PDT 24
Finished Jun 09 02:30:04 PM PDT 24
Peak memory 216188 kb
Host smart-24335c3a-246b-4fd0-9372-2c531ebe9ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175240273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.175240273
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1032966610
Short name T421
Test name
Test status
Simulation time 753631413 ps
CPU time 5.83 seconds
Started Jun 09 02:29:56 PM PDT 24
Finished Jun 09 02:30:02 PM PDT 24
Peak memory 216024 kb
Host smart-07a6d826-fb91-49e9-8a55-aea18d88fc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032966610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1032966610
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.4234313029
Short name T355
Test name
Test status
Simulation time 18652684 ps
CPU time 0.97 seconds
Started Jun 09 02:29:45 PM PDT 24
Finished Jun 09 02:29:47 PM PDT 24
Peak memory 206652 kb
Host smart-ac679c4b-57b2-4e63-8e4d-9b214fd0444d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234313029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4234313029
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.620402962
Short name T515
Test name
Test status
Simulation time 159291939 ps
CPU time 0.8 seconds
Started Jun 09 02:29:48 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 205596 kb
Host smart-aa4ec6b4-4ea4-4e89-bd09-c80311e54fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620402962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.620402962
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3937103606
Short name T491
Test name
Test status
Simulation time 25996791 ps
CPU time 0.72 seconds
Started Jun 09 02:29:51 PM PDT 24
Finished Jun 09 02:29:52 PM PDT 24
Peak memory 205152 kb
Host smart-d10102b4-9737-4f47-962c-ebd016fd2d40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937103606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3937103606
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2147184727
Short name T333
Test name
Test status
Simulation time 312551185 ps
CPU time 4.26 seconds
Started Jun 09 02:29:51 PM PDT 24
Finished Jun 09 02:29:56 PM PDT 24
Peak memory 224332 kb
Host smart-e2e2440d-9b77-482d-beff-9e6c6a719956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147184727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2147184727
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.117291252
Short name T869
Test name
Test status
Simulation time 92227440 ps
CPU time 0.84 seconds
Started Jun 09 02:29:47 PM PDT 24
Finished Jun 09 02:29:48 PM PDT 24
Peak memory 206560 kb
Host smart-4bba1513-4c35-474c-8847-b21779c49f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117291252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.117291252
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3209586750
Short name T155
Test name
Test status
Simulation time 54631737866 ps
CPU time 127.67 seconds
Started Jun 09 02:29:59 PM PDT 24
Finished Jun 09 02:32:07 PM PDT 24
Peak memory 252740 kb
Host smart-ecd0109f-8540-4ad3-9ae9-acd59f5bccff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209586750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3209586750
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3670202767
Short name T439
Test name
Test status
Simulation time 92789690379 ps
CPU time 175.04 seconds
Started Jun 09 02:29:55 PM PDT 24
Finished Jun 09 02:32:51 PM PDT 24
Peak memory 250876 kb
Host smart-88c32edc-ed30-445d-9e6f-c5292fdec50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670202767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3670202767
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2583571456
Short name T779
Test name
Test status
Simulation time 241294215 ps
CPU time 5.21 seconds
Started Jun 09 02:29:48 PM PDT 24
Finished Jun 09 02:29:53 PM PDT 24
Peak memory 224340 kb
Host smart-1df1ce42-cad2-48f0-b99c-58f7643034f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583571456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2583571456
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4183088601
Short name T633
Test name
Test status
Simulation time 2085517098 ps
CPU time 6.27 seconds
Started Jun 09 02:29:51 PM PDT 24
Finished Jun 09 02:29:58 PM PDT 24
Peak memory 224316 kb
Host smart-12ca60bc-cbd1-439a-a86e-cd9d485e46e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183088601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4183088601
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.118806093
Short name T426
Test name
Test status
Simulation time 2319263791 ps
CPU time 26.46 seconds
Started Jun 09 02:29:52 PM PDT 24
Finished Jun 09 02:30:19 PM PDT 24
Peak memory 240256 kb
Host smart-0f0192ad-bc88-4797-b4a9-2be4bdb2b5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118806093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.118806093
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3428214498
Short name T572
Test name
Test status
Simulation time 26763818 ps
CPU time 1.1 seconds
Started Jun 09 02:29:48 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 216380 kb
Host smart-8587c000-68d6-49d4-a7f0-12d3daf7ad7e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428214498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3428214498
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2151829938
Short name T137
Test name
Test status
Simulation time 598312879 ps
CPU time 3.34 seconds
Started Jun 09 02:29:48 PM PDT 24
Finished Jun 09 02:29:52 PM PDT 24
Peak memory 224284 kb
Host smart-7c1f05ff-e7f4-46d8-b082-6f2d1122e281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151829938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2151829938
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2444603521
Short name T743
Test name
Test status
Simulation time 3135332007 ps
CPU time 3.2 seconds
Started Jun 09 02:29:46 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 232600 kb
Host smart-70343bed-18c3-49ed-9ff4-3dd5bf60166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444603521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2444603521
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1583538538
Short name T118
Test name
Test status
Simulation time 863780620 ps
CPU time 10.91 seconds
Started Jun 09 02:29:49 PM PDT 24
Finished Jun 09 02:30:01 PM PDT 24
Peak memory 222680 kb
Host smart-b0548a15-6655-4d43-bad9-931afad28b25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1583538538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1583538538
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1954071537
Short name T761
Test name
Test status
Simulation time 45795949156 ps
CPU time 86.75 seconds
Started Jun 09 02:29:46 PM PDT 24
Finished Jun 09 02:31:14 PM PDT 24
Peak memory 253764 kb
Host smart-6e5dad56-1e50-4284-9279-8695581c4430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954071537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1954071537
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2321536479
Short name T916
Test name
Test status
Simulation time 2420554537 ps
CPU time 30.71 seconds
Started Jun 09 02:29:50 PM PDT 24
Finished Jun 09 02:30:21 PM PDT 24
Peak memory 216180 kb
Host smart-b19426ed-f8ad-4225-898a-e7467f13ad33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321536479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2321536479
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.504198183
Short name T501
Test name
Test status
Simulation time 1690843608 ps
CPU time 2.65 seconds
Started Jun 09 02:29:32 PM PDT 24
Finished Jun 09 02:29:34 PM PDT 24
Peak memory 216068 kb
Host smart-ceba2c65-a59b-4595-b2d6-261dabb397fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504198183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.504198183
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1395405065
Short name T310
Test name
Test status
Simulation time 1941569157 ps
CPU time 8.12 seconds
Started Jun 09 02:29:35 PM PDT 24
Finished Jun 09 02:29:43 PM PDT 24
Peak memory 216096 kb
Host smart-ab639733-f9fd-42ad-ab7a-cbfdac9f0c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395405065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1395405065
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3643847643
Short name T344
Test name
Test status
Simulation time 39429954 ps
CPU time 0.76 seconds
Started Jun 09 02:29:49 PM PDT 24
Finished Jun 09 02:29:50 PM PDT 24
Peak memory 205260 kb
Host smart-e6529090-f41c-4d9b-9db8-a01b4fe7784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643847643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3643847643
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.504848766
Short name T754
Test name
Test status
Simulation time 240997995 ps
CPU time 4.24 seconds
Started Jun 09 02:29:57 PM PDT 24
Finished Jun 09 02:30:02 PM PDT 24
Peak memory 224320 kb
Host smart-baf2e19d-0df5-4bd4-84ad-89562748ccc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504848766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.504848766
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4283296277
Short name T821
Test name
Test status
Simulation time 42380819 ps
CPU time 0.69 seconds
Started Jun 09 02:29:13 PM PDT 24
Finished Jun 09 02:29:14 PM PDT 24
Peak memory 204428 kb
Host smart-7371b04c-6e25-46f8-b499-c3100172a3fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283296277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
283296277
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2441559295
Short name T433
Test name
Test status
Simulation time 2376989124 ps
CPU time 7.49 seconds
Started Jun 09 02:28:55 PM PDT 24
Finished Jun 09 02:29:03 PM PDT 24
Peak memory 232548 kb
Host smart-64d80462-0e5e-450f-aeb0-e30699eacc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441559295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2441559295
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1285294743
Short name T596
Test name
Test status
Simulation time 82723896 ps
CPU time 0.81 seconds
Started Jun 09 02:29:00 PM PDT 24
Finished Jun 09 02:29:01 PM PDT 24
Peak memory 206236 kb
Host smart-548d0b72-eff6-4fde-a94f-16050115da3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285294743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1285294743
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3689399019
Short name T948
Test name
Test status
Simulation time 56357861316 ps
CPU time 104.16 seconds
Started Jun 09 02:29:03 PM PDT 24
Finished Jun 09 02:30:47 PM PDT 24
Peak memory 248996 kb
Host smart-d22e7cf0-d409-47c1-a3cb-33d5b7010caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689399019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3689399019
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2383135810
Short name T231
Test name
Test status
Simulation time 16192243440 ps
CPU time 56.18 seconds
Started Jun 09 02:28:51 PM PDT 24
Finished Jun 09 02:29:47 PM PDT 24
Peak memory 238512 kb
Host smart-76bfef45-4dd7-4833-88ed-59f1fc6840d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383135810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2383135810
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2439418927
Short name T503
Test name
Test status
Simulation time 80028189 ps
CPU time 3.55 seconds
Started Jun 09 02:28:55 PM PDT 24
Finished Jun 09 02:28:59 PM PDT 24
Peak memory 224308 kb
Host smart-04e9a69b-f235-4a32-993c-ee8d14c5a5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439418927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2439418927
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2704827025
Short name T474
Test name
Test status
Simulation time 153067957 ps
CPU time 5.91 seconds
Started Jun 09 02:29:01 PM PDT 24
Finished Jun 09 02:29:07 PM PDT 24
Peak memory 232544 kb
Host smart-8eb81158-198d-453f-9e75-58cd0b9fd0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704827025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2704827025
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.361250876
Short name T670
Test name
Test status
Simulation time 7038379565 ps
CPU time 17.77 seconds
Started Jun 09 02:28:48 PM PDT 24
Finished Jun 09 02:29:06 PM PDT 24
Peak memory 224356 kb
Host smart-ee069d05-4d65-4371-b806-ea699feed1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361250876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.361250876
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1997696349
Short name T373
Test name
Test status
Simulation time 46281632 ps
CPU time 1.04 seconds
Started Jun 09 02:28:57 PM PDT 24
Finished Jun 09 02:28:58 PM PDT 24
Peak memory 217604 kb
Host smart-2d4c7f5b-894a-40d0-be18-f1106373e76c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997696349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1997696349
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2834049735
Short name T228
Test name
Test status
Simulation time 419417532 ps
CPU time 3.97 seconds
Started Jun 09 02:28:59 PM PDT 24
Finished Jun 09 02:29:03 PM PDT 24
Peak memory 232520 kb
Host smart-fc74ba25-8712-45a7-a75d-ff82f7804d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834049735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2834049735
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2129728588
Short name T912
Test name
Test status
Simulation time 8410654975 ps
CPU time 10.56 seconds
Started Jun 09 02:29:03 PM PDT 24
Finished Jun 09 02:29:14 PM PDT 24
Peak memory 232564 kb
Host smart-81f4d288-912b-477b-9e54-fb7a238891d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129728588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2129728588
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.300326604
Short name T361
Test name
Test status
Simulation time 1740863879 ps
CPU time 6.11 seconds
Started Jun 09 02:28:52 PM PDT 24
Finished Jun 09 02:28:59 PM PDT 24
Peak memory 220080 kb
Host smart-d788d42b-e48d-47b8-b546-d64d02b6732c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=300326604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.300326604
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1646745832
Short name T60
Test name
Test status
Simulation time 496500313 ps
CPU time 1.12 seconds
Started Jun 09 02:29:03 PM PDT 24
Finished Jun 09 02:29:05 PM PDT 24
Peak memory 234996 kb
Host smart-a9c534a7-f0e5-4759-b55b-c8d2eeeda2e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646745832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1646745832
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3777814290
Short name T121
Test name
Test status
Simulation time 7255354234 ps
CPU time 54.42 seconds
Started Jun 09 02:29:00 PM PDT 24
Finished Jun 09 02:29:55 PM PDT 24
Peak memory 249036 kb
Host smart-4da0576d-e131-4b8a-aa03-a70fd774cc9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777814290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3777814290
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1921030405
Short name T618
Test name
Test status
Simulation time 6251973563 ps
CPU time 36.06 seconds
Started Jun 09 02:28:49 PM PDT 24
Finished Jun 09 02:29:26 PM PDT 24
Peak memory 216140 kb
Host smart-4a96147a-16d8-47fb-aad1-40a89240ec50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921030405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1921030405
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2936219995
Short name T356
Test name
Test status
Simulation time 182790995 ps
CPU time 1.12 seconds
Started Jun 09 02:28:54 PM PDT 24
Finished Jun 09 02:28:56 PM PDT 24
Peak memory 206764 kb
Host smart-fc590dc8-3ac5-430e-ba8b-e97ac8cf4e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936219995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2936219995
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1799046923
Short name T463
Test name
Test status
Simulation time 47954594 ps
CPU time 1.27 seconds
Started Jun 09 02:29:07 PM PDT 24
Finished Jun 09 02:29:08 PM PDT 24
Peak memory 216080 kb
Host smart-11b90d68-67f1-4bd7-bf3d-ac3ecb936975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799046923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1799046923
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2954090990
Short name T747
Test name
Test status
Simulation time 53108112 ps
CPU time 0.76 seconds
Started Jun 09 02:28:58 PM PDT 24
Finished Jun 09 02:28:59 PM PDT 24
Peak memory 205596 kb
Host smart-f444c185-35e9-4fd3-a8f9-e3f1f5bcc02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954090990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2954090990
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.726061625
Short name T926
Test name
Test status
Simulation time 15119060487 ps
CPU time 23.07 seconds
Started Jun 09 02:29:01 PM PDT 24
Finished Jun 09 02:29:25 PM PDT 24
Peak memory 232552 kb
Host smart-56bcad69-626d-4e79-bf95-ba14d72d7295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726061625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.726061625
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2434548844
Short name T672
Test name
Test status
Simulation time 15003600 ps
CPU time 0.74 seconds
Started Jun 09 02:30:03 PM PDT 24
Finished Jun 09 02:30:04 PM PDT 24
Peak memory 204540 kb
Host smart-e82a1eef-2435-4f15-87a8-13117bd38573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434548844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2434548844
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3690347198
Short name T392
Test name
Test status
Simulation time 163644074 ps
CPU time 4.71 seconds
Started Jun 09 02:29:46 PM PDT 24
Finished Jun 09 02:29:51 PM PDT 24
Peak memory 224312 kb
Host smart-e1807b1f-3b67-455b-8f66-0d42ba7c7a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690347198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3690347198
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3082099017
Short name T336
Test name
Test status
Simulation time 39820545 ps
CPU time 0.82 seconds
Started Jun 09 02:29:46 PM PDT 24
Finished Jun 09 02:29:48 PM PDT 24
Peak memory 206232 kb
Host smart-795d7b62-2c76-4902-acc1-302ddc45450c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082099017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3082099017
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2178710102
Short name T744
Test name
Test status
Simulation time 2502258643 ps
CPU time 17.77 seconds
Started Jun 09 02:29:37 PM PDT 24
Finished Jun 09 02:29:55 PM PDT 24
Peak memory 234656 kb
Host smart-80316ab9-2418-48e8-914a-12c4a24b8889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178710102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2178710102
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.500658260
Short name T193
Test name
Test status
Simulation time 3576811769 ps
CPU time 50.88 seconds
Started Jun 09 02:29:46 PM PDT 24
Finished Jun 09 02:30:37 PM PDT 24
Peak memory 240860 kb
Host smart-58ea5e55-d40b-4ff8-a3a9-cbf0fb96760b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500658260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.500658260
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.119401636
Short name T311
Test name
Test status
Simulation time 486611620 ps
CPU time 8.96 seconds
Started Jun 09 02:29:53 PM PDT 24
Finished Jun 09 02:30:03 PM PDT 24
Peak memory 234144 kb
Host smart-7d067d94-196a-43af-8830-580b4637c52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119401636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.119401636
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2434239343
Short name T951
Test name
Test status
Simulation time 983986348 ps
CPU time 7.19 seconds
Started Jun 09 02:29:42 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 218412 kb
Host smart-2833b22d-0546-4e75-82d2-ef951abe17e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434239343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2434239343
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.42662879
Short name T279
Test name
Test status
Simulation time 20342040830 ps
CPU time 84.69 seconds
Started Jun 09 02:29:49 PM PDT 24
Finished Jun 09 02:31:14 PM PDT 24
Peak memory 232556 kb
Host smart-4fd9b471-cc11-40cb-8cd1-369e2c748641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42662879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.42662879
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3150103182
Short name T883
Test name
Test status
Simulation time 227697944 ps
CPU time 3.93 seconds
Started Jun 09 02:29:38 PM PDT 24
Finished Jun 09 02:29:42 PM PDT 24
Peak memory 232524 kb
Host smart-512e4679-5745-4da9-b8fa-0d3b7390e4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150103182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3150103182
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2446107421
Short name T710
Test name
Test status
Simulation time 5982861769 ps
CPU time 16.01 seconds
Started Jun 09 02:29:57 PM PDT 24
Finished Jun 09 02:30:14 PM PDT 24
Peak memory 232568 kb
Host smart-de998a20-3ccb-4d67-9738-c989df331310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446107421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2446107421
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1772289863
Short name T790
Test name
Test status
Simulation time 163538847 ps
CPU time 3.84 seconds
Started Jun 09 02:29:52 PM PDT 24
Finished Jun 09 02:29:56 PM PDT 24
Peak memory 218632 kb
Host smart-c380fd6d-dfa2-4af9-81da-f488d1fff389
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1772289863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1772289863
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3491273036
Short name T925
Test name
Test status
Simulation time 13706081249 ps
CPU time 23.12 seconds
Started Jun 09 02:29:51 PM PDT 24
Finished Jun 09 02:30:14 PM PDT 24
Peak memory 216124 kb
Host smart-3794036d-65c9-4c11-8c2f-1d9848ec7e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491273036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3491273036
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1637499378
Short name T569
Test name
Test status
Simulation time 6052032281 ps
CPU time 9.4 seconds
Started Jun 09 02:29:57 PM PDT 24
Finished Jun 09 02:30:07 PM PDT 24
Peak memory 216064 kb
Host smart-0dae59a7-3ee1-406e-b887-649580e2fc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637499378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1637499378
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1163866490
Short name T298
Test name
Test status
Simulation time 63790068 ps
CPU time 1.28 seconds
Started Jun 09 02:30:01 PM PDT 24
Finished Jun 09 02:30:03 PM PDT 24
Peak memory 216040 kb
Host smart-b345baed-1ee6-4a20-b8ac-5c60a0a0b91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163866490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1163866490
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1592655338
Short name T435
Test name
Test status
Simulation time 21436372 ps
CPU time 0.75 seconds
Started Jun 09 02:29:59 PM PDT 24
Finished Jun 09 02:30:00 PM PDT 24
Peak memory 205612 kb
Host smart-c08c3016-7c6b-4685-9d4a-61a4e10d3ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592655338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1592655338
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3707110208
Short name T913
Test name
Test status
Simulation time 122193391 ps
CPU time 2.77 seconds
Started Jun 09 02:29:52 PM PDT 24
Finished Jun 09 02:29:55 PM PDT 24
Peak memory 232284 kb
Host smart-5b901a88-4485-4625-b8f0-e2902db3cf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707110208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3707110208
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2639531378
Short name T604
Test name
Test status
Simulation time 60549140 ps
CPU time 0.72 seconds
Started Jun 09 02:29:47 PM PDT 24
Finished Jun 09 02:29:48 PM PDT 24
Peak memory 204540 kb
Host smart-7b0632c9-1fa1-41e2-833a-2a10003ac87c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639531378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2639531378
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1728790917
Short name T338
Test name
Test status
Simulation time 3669900376 ps
CPU time 14.63 seconds
Started Jun 09 02:29:59 PM PDT 24
Finished Jun 09 02:30:14 PM PDT 24
Peak memory 224404 kb
Host smart-f03e2933-1119-4371-ae17-d5ac49548870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728790917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1728790917
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.879543142
Short name T953
Test name
Test status
Simulation time 18877088 ps
CPU time 0.83 seconds
Started Jun 09 02:29:54 PM PDT 24
Finished Jun 09 02:29:55 PM PDT 24
Peak memory 206228 kb
Host smart-3167f54a-5a71-447d-8c4e-308968d178cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879543142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.879543142
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.874450166
Short name T599
Test name
Test status
Simulation time 25858652486 ps
CPU time 179.62 seconds
Started Jun 09 02:29:50 PM PDT 24
Finished Jun 09 02:32:50 PM PDT 24
Peak memory 249084 kb
Host smart-c23c27e5-ba2b-4d00-be68-5c128dde883b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874450166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.874450166
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2150077686
Short name T202
Test name
Test status
Simulation time 76889359486 ps
CPU time 200.69 seconds
Started Jun 09 02:29:55 PM PDT 24
Finished Jun 09 02:33:17 PM PDT 24
Peak memory 268716 kb
Host smart-71601211-2463-45bc-a45b-f88a6cb502e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150077686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2150077686
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.699361260
Short name T14
Test name
Test status
Simulation time 3640545032 ps
CPU time 85.52 seconds
Started Jun 09 02:29:59 PM PDT 24
Finished Jun 09 02:31:25 PM PDT 24
Peak memory 250672 kb
Host smart-5628e64b-7142-4521-a170-e21ee536dbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699361260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.699361260
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1881890513
Short name T731
Test name
Test status
Simulation time 3844723572 ps
CPU time 29.61 seconds
Started Jun 09 02:30:11 PM PDT 24
Finished Jun 09 02:30:41 PM PDT 24
Peak memory 240800 kb
Host smart-e3f46584-526c-428c-9821-a890bdc2588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881890513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1881890513
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3037046984
Short name T360
Test name
Test status
Simulation time 946685706 ps
CPU time 11.2 seconds
Started Jun 09 02:30:01 PM PDT 24
Finished Jun 09 02:30:13 PM PDT 24
Peak memory 232524 kb
Host smart-978aa0cd-16e6-4b52-8a09-8e961df3d7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037046984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3037046984
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1390337056
Short name T397
Test name
Test status
Simulation time 732129213 ps
CPU time 7.63 seconds
Started Jun 09 02:29:49 PM PDT 24
Finished Jun 09 02:29:57 PM PDT 24
Peak memory 232504 kb
Host smart-811b466d-5ea4-46b8-8e1a-053e0fbe45f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390337056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1390337056
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2995553975
Short name T424
Test name
Test status
Simulation time 1369969300 ps
CPU time 4.07 seconds
Started Jun 09 02:29:55 PM PDT 24
Finished Jun 09 02:30:00 PM PDT 24
Peak memory 224252 kb
Host smart-7247e9b5-44d4-4b73-bdad-342c180242bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995553975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2995553975
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3175917524
Short name T611
Test name
Test status
Simulation time 94633484 ps
CPU time 2.33 seconds
Started Jun 09 02:29:51 PM PDT 24
Finished Jun 09 02:29:54 PM PDT 24
Peak memory 224336 kb
Host smart-aa1be8f6-cd78-40f6-80e6-8e7958b433f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175917524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3175917524
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2133309760
Short name T644
Test name
Test status
Simulation time 540576096 ps
CPU time 4.52 seconds
Started Jun 09 02:29:59 PM PDT 24
Finished Jun 09 02:30:04 PM PDT 24
Peak memory 222792 kb
Host smart-f91a2760-3e3a-4d2e-9567-3db2d4c18e75
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2133309760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2133309760
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.448226247
Short name T123
Test name
Test status
Simulation time 83504004318 ps
CPU time 389.2 seconds
Started Jun 09 02:29:48 PM PDT 24
Finished Jun 09 02:36:18 PM PDT 24
Peak memory 256808 kb
Host smart-864a95e0-146f-4529-a272-3c7981556bbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448226247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.448226247
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2738854956
Short name T971
Test name
Test status
Simulation time 3105235378 ps
CPU time 21.89 seconds
Started Jun 09 02:29:58 PM PDT 24
Finished Jun 09 02:30:20 PM PDT 24
Peak memory 216156 kb
Host smart-0c5367f5-cad0-425a-8366-624f1e38f514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738854956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2738854956
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3078413261
Short name T652
Test name
Test status
Simulation time 8402110395 ps
CPU time 6.8 seconds
Started Jun 09 02:29:51 PM PDT 24
Finished Jun 09 02:29:58 PM PDT 24
Peak memory 216100 kb
Host smart-0205caab-e6d1-414d-b55e-2d5e518c98cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078413261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3078413261
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.710252625
Short name T816
Test name
Test status
Simulation time 180339604 ps
CPU time 1.43 seconds
Started Jun 09 02:29:47 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 216004 kb
Host smart-946e3ba6-679b-4511-81f6-5ae2c034833d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710252625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.710252625
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2555899694
Short name T517
Test name
Test status
Simulation time 134657669 ps
CPU time 0.83 seconds
Started Jun 09 02:29:53 PM PDT 24
Finished Jun 09 02:29:55 PM PDT 24
Peak memory 205600 kb
Host smart-8c771db8-8df9-4ca4-9ce9-6df135fa7283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555899694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2555899694
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3083543670
Short name T623
Test name
Test status
Simulation time 9054074318 ps
CPU time 3.69 seconds
Started Jun 09 02:29:51 PM PDT 24
Finished Jun 09 02:29:54 PM PDT 24
Peak memory 224352 kb
Host smart-155bbfdf-44be-43c5-872c-522d96399556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083543670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3083543670
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.528516736
Short name T646
Test name
Test status
Simulation time 80380544 ps
CPU time 0.74 seconds
Started Jun 09 02:29:50 PM PDT 24
Finished Jun 09 02:29:51 PM PDT 24
Peak memory 204536 kb
Host smart-10edb054-1ebf-4fc7-ad13-14530558fb18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528516736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.528516736
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2991076323
Short name T512
Test name
Test status
Simulation time 884074667 ps
CPU time 4.58 seconds
Started Jun 09 02:29:53 PM PDT 24
Finished Jun 09 02:29:58 PM PDT 24
Peak memory 224292 kb
Host smart-45dcb0b0-fe04-44df-8cca-7f15a696264a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991076323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2991076323
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3050889910
Short name T354
Test name
Test status
Simulation time 115193827 ps
CPU time 0.75 seconds
Started Jun 09 02:29:54 PM PDT 24
Finished Jun 09 02:29:55 PM PDT 24
Peak memory 205200 kb
Host smart-59923af4-2b8a-47e9-9eac-356d77a069a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050889910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3050889910
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2616525605
Short name T558
Test name
Test status
Simulation time 12289067851 ps
CPU time 90.16 seconds
Started Jun 09 02:29:53 PM PDT 24
Finished Jun 09 02:31:24 PM PDT 24
Peak memory 237908 kb
Host smart-c1d53769-cf6d-43c2-b291-2ce87bff752e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616525605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2616525605
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.696230366
Short name T31
Test name
Test status
Simulation time 113254551106 ps
CPU time 130 seconds
Started Jun 09 02:30:08 PM PDT 24
Finished Jun 09 02:32:18 PM PDT 24
Peak memory 249728 kb
Host smart-d8b1cfe6-0f43-4f3e-a343-349b30a6ce35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696230366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.696230366
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.718402486
Short name T262
Test name
Test status
Simulation time 44058653133 ps
CPU time 219.5 seconds
Started Jun 09 02:30:03 PM PDT 24
Finished Jun 09 02:33:43 PM PDT 24
Peak memory 257196 kb
Host smart-0f860f49-f3c7-4508-809f-e8122a6a0238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718402486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.718402486
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1349918948
Short name T528
Test name
Test status
Simulation time 311796578 ps
CPU time 5.19 seconds
Started Jun 09 02:29:53 PM PDT 24
Finished Jun 09 02:29:59 PM PDT 24
Peak memory 224260 kb
Host smart-41ac3884-4f70-4dd9-b647-de55496b155a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349918948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1349918948
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.985237008
Short name T784
Test name
Test status
Simulation time 1758556469 ps
CPU time 3.54 seconds
Started Jun 09 02:30:01 PM PDT 24
Finished Jun 09 02:30:05 PM PDT 24
Peak memory 232516 kb
Host smart-f6331fe3-767a-4985-99f5-d8b4ef76187a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985237008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.985237008
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3698413047
Short name T2
Test name
Test status
Simulation time 4841972863 ps
CPU time 14.66 seconds
Started Jun 09 02:29:58 PM PDT 24
Finished Jun 09 02:30:13 PM PDT 24
Peak memory 224240 kb
Host smart-aa16a215-3243-42cd-be6d-429986f92571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698413047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3698413047
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3414310156
Short name T635
Test name
Test status
Simulation time 184697387 ps
CPU time 3.7 seconds
Started Jun 09 02:29:48 PM PDT 24
Finished Jun 09 02:29:52 PM PDT 24
Peak memory 224336 kb
Host smart-137301e1-18e8-48cd-87b6-68659d3da088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414310156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3414310156
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.46762762
Short name T820
Test name
Test status
Simulation time 347336745 ps
CPU time 3.25 seconds
Started Jun 09 02:29:54 PM PDT 24
Finished Jun 09 02:29:57 PM PDT 24
Peak memory 232508 kb
Host smart-e505c293-19a2-49d1-b862-1d2b9216ae77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46762762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.46762762
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3420175574
Short name T970
Test name
Test status
Simulation time 114834547 ps
CPU time 3.18 seconds
Started Jun 09 02:29:50 PM PDT 24
Finished Jun 09 02:29:53 PM PDT 24
Peak memory 219904 kb
Host smart-6f9d5521-e481-4280-bc7b-c26aaa0c942b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3420175574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3420175574
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3680818332
Short name T26
Test name
Test status
Simulation time 5995843599 ps
CPU time 24 seconds
Started Jun 09 02:29:50 PM PDT 24
Finished Jun 09 02:30:14 PM PDT 24
Peak memory 224404 kb
Host smart-c2ba8027-d792-4910-8e67-0d8bec26f0cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680818332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3680818332
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3181072262
Short name T444
Test name
Test status
Simulation time 3947565939 ps
CPU time 13.1 seconds
Started Jun 09 02:29:59 PM PDT 24
Finished Jun 09 02:30:13 PM PDT 24
Peak memory 216156 kb
Host smart-febbcdd2-a57c-45e3-b187-94ec599f7792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181072262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3181072262
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.130954507
Short name T407
Test name
Test status
Simulation time 4901998260 ps
CPU time 14.22 seconds
Started Jun 09 02:29:58 PM PDT 24
Finished Jun 09 02:30:12 PM PDT 24
Peak memory 216108 kb
Host smart-daf0e066-6698-472e-ba87-c4c0f3ed94d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130954507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.130954507
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3361630484
Short name T303
Test name
Test status
Simulation time 99150761 ps
CPU time 1.49 seconds
Started Jun 09 02:29:52 PM PDT 24
Finished Jun 09 02:29:53 PM PDT 24
Peak memory 216056 kb
Host smart-1176e90e-1b7d-4970-8a51-b1c9a42ec43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361630484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3361630484
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.909554449
Short name T683
Test name
Test status
Simulation time 27278909 ps
CPU time 0.8 seconds
Started Jun 09 02:29:53 PM PDT 24
Finished Jun 09 02:29:54 PM PDT 24
Peak memory 205596 kb
Host smart-0ac3834f-829d-471d-99d7-7b36be3b775c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909554449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.909554449
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1565029489
Short name T949
Test name
Test status
Simulation time 1227496322 ps
CPU time 9.57 seconds
Started Jun 09 02:29:56 PM PDT 24
Finished Jun 09 02:30:06 PM PDT 24
Peak memory 224300 kb
Host smart-5dfea578-f608-422e-8691-c3f9ad21564c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565029489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1565029489
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1570106026
Short name T565
Test name
Test status
Simulation time 23064583 ps
CPU time 0.72 seconds
Started Jun 09 02:29:55 PM PDT 24
Finished Jun 09 02:29:56 PM PDT 24
Peak memory 205504 kb
Host smart-5932adc4-da3b-4bb7-aaf7-5756b5ae9e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570106026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1570106026
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.674579401
Short name T621
Test name
Test status
Simulation time 15961416161 ps
CPU time 36.19 seconds
Started Jun 09 02:30:00 PM PDT 24
Finished Jun 09 02:30:36 PM PDT 24
Peak memory 224336 kb
Host smart-70a81d46-e06c-4809-b0ca-a24e489a42e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674579401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.674579401
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3932563978
Short name T849
Test name
Test status
Simulation time 61463304 ps
CPU time 0.77 seconds
Started Jun 09 02:29:50 PM PDT 24
Finished Jun 09 02:29:51 PM PDT 24
Peak memory 206236 kb
Host smart-5b9da2bc-123e-44f1-99ad-694bbd0a17dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932563978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3932563978
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3615796708
Short name T401
Test name
Test status
Simulation time 17701398 ps
CPU time 0.77 seconds
Started Jun 09 02:30:01 PM PDT 24
Finished Jun 09 02:30:02 PM PDT 24
Peak memory 215704 kb
Host smart-65e0aeb6-62e9-417e-8d72-37e5a56c25b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615796708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3615796708
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2328233589
Short name T857
Test name
Test status
Simulation time 17571148162 ps
CPU time 148.61 seconds
Started Jun 09 02:29:54 PM PDT 24
Finished Jun 09 02:32:23 PM PDT 24
Peak memory 238164 kb
Host smart-2766e7c6-60aa-48df-b7c4-11ace815f978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328233589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2328233589
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3239783324
Short name T794
Test name
Test status
Simulation time 169088810 ps
CPU time 5.12 seconds
Started Jun 09 02:30:01 PM PDT 24
Finished Jun 09 02:30:06 PM PDT 24
Peak memory 232496 kb
Host smart-baf0718b-6d2e-48dc-a9f8-34aae94cf944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239783324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3239783324
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3609347062
Short name T479
Test name
Test status
Simulation time 5612187759 ps
CPU time 11.5 seconds
Started Jun 09 02:29:56 PM PDT 24
Finished Jun 09 02:30:08 PM PDT 24
Peak memory 228240 kb
Host smart-9e557343-70be-4484-8e6f-7062dc89b2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609347062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3609347062
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3675293129
Short name T675
Test name
Test status
Simulation time 3570732024 ps
CPU time 17.19 seconds
Started Jun 09 02:29:58 PM PDT 24
Finished Jun 09 02:30:15 PM PDT 24
Peak memory 224332 kb
Host smart-ceecab92-2691-4270-994c-4d584e21f127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675293129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3675293129
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3661304963
Short name T742
Test name
Test status
Simulation time 32879355 ps
CPU time 2.28 seconds
Started Jun 09 02:29:44 PM PDT 24
Finished Jun 09 02:29:46 PM PDT 24
Peak memory 232248 kb
Host smart-a241a0de-caee-435f-8f44-c4b08402c4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661304963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3661304963
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4127667789
Short name T770
Test name
Test status
Simulation time 1006878007 ps
CPU time 4.78 seconds
Started Jun 09 02:30:00 PM PDT 24
Finished Jun 09 02:30:06 PM PDT 24
Peak memory 232452 kb
Host smart-91759f99-0728-4b3f-b6bd-38a1ec722e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127667789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4127667789
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3480369192
Short name T577
Test name
Test status
Simulation time 87664019 ps
CPU time 3.86 seconds
Started Jun 09 02:30:03 PM PDT 24
Finished Jun 09 02:30:07 PM PDT 24
Peak memory 222276 kb
Host smart-2542419f-ccbe-4826-a82a-4db119760d9f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3480369192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3480369192
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1825189534
Short name T669
Test name
Test status
Simulation time 14514401361 ps
CPU time 109.45 seconds
Started Jun 09 02:29:54 PM PDT 24
Finished Jun 09 02:31:43 PM PDT 24
Peak memory 233848 kb
Host smart-af394fc7-df6f-4058-9560-4dee11ad4c52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825189534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1825189534
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2271559295
Short name T294
Test name
Test status
Simulation time 30518171505 ps
CPU time 39.55 seconds
Started Jun 09 02:29:53 PM PDT 24
Finished Jun 09 02:30:33 PM PDT 24
Peak memory 216156 kb
Host smart-77abc61f-a67f-4832-a01a-202b5e594e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271559295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2271559295
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3745564928
Short name T330
Test name
Test status
Simulation time 5192568798 ps
CPU time 13.99 seconds
Started Jun 09 02:29:52 PM PDT 24
Finished Jun 09 02:30:06 PM PDT 24
Peak memory 216108 kb
Host smart-c4314fe4-be95-49ab-83a6-148c51c25dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745564928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3745564928
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1972954544
Short name T613
Test name
Test status
Simulation time 62953609 ps
CPU time 1.5 seconds
Started Jun 09 02:29:57 PM PDT 24
Finished Jun 09 02:29:59 PM PDT 24
Peak memory 216064 kb
Host smart-78bb0d58-d22f-4e31-b6dc-9eb05dd6c829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972954544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1972954544
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3615968171
Short name T575
Test name
Test status
Simulation time 63596481 ps
CPU time 0.84 seconds
Started Jun 09 02:29:52 PM PDT 24
Finished Jun 09 02:29:53 PM PDT 24
Peak memory 205604 kb
Host smart-7b6b0aa8-f641-46f0-86b4-23331076b426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615968171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3615968171
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1032837994
Short name T631
Test name
Test status
Simulation time 4136366836 ps
CPU time 17.33 seconds
Started Jun 09 02:29:58 PM PDT 24
Finished Jun 09 02:30:16 PM PDT 24
Peak memory 224356 kb
Host smart-5d36c21c-a1b6-4f48-a0cd-ae892028fcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032837994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1032837994
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1875371517
Short name T550
Test name
Test status
Simulation time 17468264 ps
CPU time 0.68 seconds
Started Jun 09 02:29:59 PM PDT 24
Finished Jun 09 02:30:00 PM PDT 24
Peak memory 205176 kb
Host smart-a7c440aa-1de0-4d94-9a11-f6d436be98a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875371517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1875371517
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3286595477
Short name T499
Test name
Test status
Simulation time 564656150 ps
CPU time 4.03 seconds
Started Jun 09 02:30:05 PM PDT 24
Finished Jun 09 02:30:09 PM PDT 24
Peak memory 232512 kb
Host smart-e6eff022-d8bb-4ef3-8cd2-2cc996eeb05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286595477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3286595477
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3375588530
Short name T639
Test name
Test status
Simulation time 24495754 ps
CPU time 0.76 seconds
Started Jun 09 02:29:56 PM PDT 24
Finished Jun 09 02:29:57 PM PDT 24
Peak memory 206216 kb
Host smart-d5d8df10-2a9f-4e24-8c98-1d19b9c472b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375588530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3375588530
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.201996468
Short name T350
Test name
Test status
Simulation time 8558181435 ps
CPU time 34.49 seconds
Started Jun 09 02:30:06 PM PDT 24
Finished Jun 09 02:30:41 PM PDT 24
Peak memory 240864 kb
Host smart-c494c7f0-458c-46da-992a-5632875b4304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201996468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.201996468
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.503038689
Short name T920
Test name
Test status
Simulation time 303437270 ps
CPU time 3.2 seconds
Started Jun 09 02:29:54 PM PDT 24
Finished Jun 09 02:29:58 PM PDT 24
Peak memory 224248 kb
Host smart-256cd863-bdc8-434b-bf78-49e061fd7d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503038689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.503038689
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3152735432
Short name T698
Test name
Test status
Simulation time 3680926463 ps
CPU time 18.12 seconds
Started Jun 09 02:29:59 PM PDT 24
Finished Jun 09 02:30:18 PM PDT 24
Peak memory 224372 kb
Host smart-97357f37-41de-482c-a3fe-dad33a4835ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152735432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3152735432
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.9985001
Short name T702
Test name
Test status
Simulation time 5921370500 ps
CPU time 11.57 seconds
Started Jun 09 02:30:09 PM PDT 24
Finished Jun 09 02:30:21 PM PDT 24
Peak memory 232012 kb
Host smart-64d6d539-5143-46d4-936a-24c643d7edc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9985001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.9985001
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1194402884
Short name T157
Test name
Test status
Simulation time 436490003 ps
CPU time 5.76 seconds
Started Jun 09 02:29:56 PM PDT 24
Finished Jun 09 02:30:02 PM PDT 24
Peak memory 232520 kb
Host smart-311c71cf-8c7d-48d2-987c-a0103eb9922d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194402884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1194402884
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3849714671
Short name T533
Test name
Test status
Simulation time 2552324979 ps
CPU time 9.5 seconds
Started Jun 09 02:30:03 PM PDT 24
Finished Jun 09 02:30:13 PM PDT 24
Peak memory 232600 kb
Host smart-876de7e5-c812-4335-a2af-abcc4c73b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849714671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3849714671
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.322711619
Short name T832
Test name
Test status
Simulation time 4353437323 ps
CPU time 8.93 seconds
Started Jun 09 02:29:58 PM PDT 24
Finished Jun 09 02:30:08 PM PDT 24
Peak memory 222780 kb
Host smart-bf957bc1-ce65-4585-be7b-9ae5ba5f1a81
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=322711619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.322711619
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.227421153
Short name T36
Test name
Test status
Simulation time 175711319788 ps
CPU time 412.89 seconds
Started Jun 09 02:30:04 PM PDT 24
Finished Jun 09 02:36:57 PM PDT 24
Peak memory 266676 kb
Host smart-e640447e-0c08-4a64-888e-874d508cdcc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227421153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.227421153
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3313556303
Short name T818
Test name
Test status
Simulation time 1585393413 ps
CPU time 15.24 seconds
Started Jun 09 02:29:55 PM PDT 24
Finished Jun 09 02:30:10 PM PDT 24
Peak memory 216096 kb
Host smart-aeb2b957-c4f7-4e76-9a70-9e1407a5faaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313556303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3313556303
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2795752459
Short name T507
Test name
Test status
Simulation time 12479335926 ps
CPU time 16.68 seconds
Started Jun 09 02:29:53 PM PDT 24
Finished Jun 09 02:30:10 PM PDT 24
Peak memory 216172 kb
Host smart-782eebff-05f6-401b-8f79-19861ae370a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795752459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2795752459
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2427129129
Short name T430
Test name
Test status
Simulation time 114563504 ps
CPU time 1.12 seconds
Started Jun 09 02:29:58 PM PDT 24
Finished Jun 09 02:29:59 PM PDT 24
Peak memory 207824 kb
Host smart-d6b5928d-d8f9-4e44-86ca-b60b79ad6a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427129129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2427129129
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.816470945
Short name T531
Test name
Test status
Simulation time 63018458 ps
CPU time 0.9 seconds
Started Jun 09 02:30:13 PM PDT 24
Finished Jun 09 02:30:14 PM PDT 24
Peak memory 205600 kb
Host smart-677cccde-f779-47e4-97a7-fdf12eefcbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816470945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.816470945
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2432878098
Short name T271
Test name
Test status
Simulation time 4251748309 ps
CPU time 5.76 seconds
Started Jun 09 02:30:08 PM PDT 24
Finished Jun 09 02:30:14 PM PDT 24
Peak memory 232544 kb
Host smart-14f4ca24-c2a1-44bb-b541-b008e3551c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432878098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2432878098
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2247136505
Short name T516
Test name
Test status
Simulation time 12926376 ps
CPU time 0.74 seconds
Started Jun 09 02:30:11 PM PDT 24
Finished Jun 09 02:30:12 PM PDT 24
Peak memory 204520 kb
Host smart-23533a73-7bce-429a-b4ca-9fec6b2ca2a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247136505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2247136505
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1777874004
Short name T870
Test name
Test status
Simulation time 1100962834 ps
CPU time 4.45 seconds
Started Jun 09 02:30:04 PM PDT 24
Finished Jun 09 02:30:09 PM PDT 24
Peak memory 232564 kb
Host smart-52b9c810-69a5-4bac-972b-32ee5231a7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777874004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1777874004
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.218171637
Short name T871
Test name
Test status
Simulation time 15155952 ps
CPU time 0.79 seconds
Started Jun 09 02:29:53 PM PDT 24
Finished Jun 09 02:29:55 PM PDT 24
Peak memory 205536 kb
Host smart-82434d13-0570-4054-9014-189cb2f5817c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218171637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.218171637
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1200950766
Short name T233
Test name
Test status
Simulation time 10144384237 ps
CPU time 27.82 seconds
Started Jun 09 02:30:06 PM PDT 24
Finished Jun 09 02:30:34 PM PDT 24
Peak memory 255280 kb
Host smart-fd1861e7-b060-472b-a115-1eb9ca5eb4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200950766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1200950766
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3361122924
Short name T160
Test name
Test status
Simulation time 52899095502 ps
CPU time 478.49 seconds
Started Jun 09 02:29:59 PM PDT 24
Finished Jun 09 02:37:58 PM PDT 24
Peak memory 256392 kb
Host smart-928a6aac-fce8-4508-9dc6-088632221b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361122924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3361122924
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3673574321
Short name T910
Test name
Test status
Simulation time 4340312654 ps
CPU time 15.03 seconds
Started Jun 09 02:29:57 PM PDT 24
Finished Jun 09 02:30:12 PM PDT 24
Peak memory 224344 kb
Host smart-1dfa01a0-1fd4-4097-9798-c039edfc7340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673574321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3673574321
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3979402160
Short name T546
Test name
Test status
Simulation time 26845805957 ps
CPU time 100.49 seconds
Started Jun 09 02:30:07 PM PDT 24
Finished Jun 09 02:31:48 PM PDT 24
Peak memory 232680 kb
Host smart-4f9a460e-f320-4cc9-aca9-f2bfb2e3d9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979402160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3979402160
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.164443337
Short name T874
Test name
Test status
Simulation time 18558786374 ps
CPU time 16.18 seconds
Started Jun 09 02:30:02 PM PDT 24
Finished Jun 09 02:30:18 PM PDT 24
Peak memory 232568 kb
Host smart-78b122d3-2110-4101-a1bb-42fe79d72593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164443337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.164443337
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3191867553
Short name T898
Test name
Test status
Simulation time 1441772510 ps
CPU time 7.88 seconds
Started Jun 09 02:29:55 PM PDT 24
Finished Jun 09 02:30:03 PM PDT 24
Peak memory 232688 kb
Host smart-4fa03c58-9511-4dc3-9009-c99b00ea4616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191867553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3191867553
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3009396514
Short name T864
Test name
Test status
Simulation time 3238478652 ps
CPU time 9.82 seconds
Started Jun 09 02:30:01 PM PDT 24
Finished Jun 09 02:30:11 PM PDT 24
Peak memory 222840 kb
Host smart-1d09dc88-2485-46f7-933e-d89f7421acf7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3009396514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3009396514
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.407290118
Short name T597
Test name
Test status
Simulation time 3455980004 ps
CPU time 40.31 seconds
Started Jun 09 02:29:55 PM PDT 24
Finished Jun 09 02:30:36 PM PDT 24
Peak memory 237072 kb
Host smart-4b5eca25-7fb3-4781-b136-6be9642b9234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407290118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.407290118
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3584735601
Short name T72
Test name
Test status
Simulation time 6760020684 ps
CPU time 22.93 seconds
Started Jun 09 02:29:55 PM PDT 24
Finished Jun 09 02:30:18 PM PDT 24
Peak memory 216408 kb
Host smart-c58b1e82-e2bc-4925-8270-dfb34779031d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584735601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3584735601
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.23702545
Short name T668
Test name
Test status
Simulation time 41946700340 ps
CPU time 8.05 seconds
Started Jun 09 02:30:00 PM PDT 24
Finished Jun 09 02:30:08 PM PDT 24
Peak memory 215716 kb
Host smart-16a8bec1-83ac-4c54-8920-42bd56c1a0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23702545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.23702545
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2821795173
Short name T328
Test name
Test status
Simulation time 453060568 ps
CPU time 1.54 seconds
Started Jun 09 02:30:04 PM PDT 24
Finished Jun 09 02:30:05 PM PDT 24
Peak memory 216120 kb
Host smart-532a0a88-3c96-48ee-8c0c-39494731c53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821795173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2821795173
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2350922611
Short name T403
Test name
Test status
Simulation time 39803514 ps
CPU time 0.82 seconds
Started Jun 09 02:29:51 PM PDT 24
Finished Jun 09 02:29:53 PM PDT 24
Peak memory 205592 kb
Host smart-a74b37d0-ce65-475f-b17c-81f2c98c0629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350922611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2350922611
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2588696249
Short name T706
Test name
Test status
Simulation time 292803084 ps
CPU time 4.14 seconds
Started Jun 09 02:29:51 PM PDT 24
Finished Jun 09 02:29:56 PM PDT 24
Peak memory 232540 kb
Host smart-73a78863-52ef-455d-89d6-f0d9773cd7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588696249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2588696249
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2486351128
Short name T346
Test name
Test status
Simulation time 17435047 ps
CPU time 0.68 seconds
Started Jun 09 02:30:02 PM PDT 24
Finished Jun 09 02:30:03 PM PDT 24
Peak memory 205128 kb
Host smart-54178d58-8f74-4765-ab00-2f0bbab56956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486351128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2486351128
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.15588350
Short name T249
Test name
Test status
Simulation time 72283835 ps
CPU time 2.96 seconds
Started Jun 09 02:29:56 PM PDT 24
Finished Jun 09 02:29:59 PM PDT 24
Peak memory 232544 kb
Host smart-67937a65-67c5-449f-99c2-80d0f2447ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15588350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.15588350
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.551872997
Short name T725
Test name
Test status
Simulation time 19793432 ps
CPU time 0.76 seconds
Started Jun 09 02:30:04 PM PDT 24
Finished Jun 09 02:30:05 PM PDT 24
Peak memory 206216 kb
Host smart-b0eaafe2-5e19-487c-b4a8-cd3ee3451da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551872997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.551872997
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2301168318
Short name T481
Test name
Test status
Simulation time 27425616881 ps
CPU time 193.11 seconds
Started Jun 09 02:29:55 PM PDT 24
Finished Jun 09 02:33:09 PM PDT 24
Peak memory 249012 kb
Host smart-22f0ea90-3d86-47f1-aab5-702ddbdcb553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301168318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2301168318
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.4046189392
Short name T212
Test name
Test status
Simulation time 4476740450 ps
CPU time 81.16 seconds
Started Jun 09 02:30:00 PM PDT 24
Finished Jun 09 02:31:21 PM PDT 24
Peak memory 256412 kb
Host smart-9a1b9ef3-5de7-457d-926f-9c812c3c62ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046189392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.4046189392
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3039779171
Short name T941
Test name
Test status
Simulation time 3473409010 ps
CPU time 17.54 seconds
Started Jun 09 02:30:07 PM PDT 24
Finished Jun 09 02:30:25 PM PDT 24
Peak memory 232620 kb
Host smart-52bfbe80-63d3-459b-a547-d45a6b6567cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039779171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3039779171
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2299028728
Short name T570
Test name
Test status
Simulation time 614528728 ps
CPU time 8.5 seconds
Started Jun 09 02:30:02 PM PDT 24
Finished Jun 09 02:30:11 PM PDT 24
Peak memory 232504 kb
Host smart-3569e954-fd42-4df3-a8ae-ff3aef68b2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299028728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2299028728
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.700226265
Short name T721
Test name
Test status
Simulation time 6028780715 ps
CPU time 19.26 seconds
Started Jun 09 02:30:11 PM PDT 24
Finished Jun 09 02:30:30 PM PDT 24
Peak memory 232568 kb
Host smart-3b5c9d53-0556-48cf-a74c-e5d66d796698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700226265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.700226265
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3019549007
Short name T612
Test name
Test status
Simulation time 1683823376 ps
CPU time 5.87 seconds
Started Jun 09 02:30:06 PM PDT 24
Finished Jun 09 02:30:12 PM PDT 24
Peak memory 232516 kb
Host smart-e783dcbd-a734-4861-8807-d49c4c514ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019549007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3019549007
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1475737230
Short name T486
Test name
Test status
Simulation time 1009863765 ps
CPU time 4.21 seconds
Started Jun 09 02:29:58 PM PDT 24
Finished Jun 09 02:30:02 PM PDT 24
Peak memory 224344 kb
Host smart-6c18c5b3-28d2-4707-81d3-41c697f522b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475737230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1475737230
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2785531313
Short name T643
Test name
Test status
Simulation time 264283501 ps
CPU time 4.52 seconds
Started Jun 09 02:30:12 PM PDT 24
Finished Jun 09 02:30:16 PM PDT 24
Peak memory 218600 kb
Host smart-39188c8e-fd54-4f72-9bbf-84db17cb5333
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2785531313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2785531313
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.435388215
Short name T840
Test name
Test status
Simulation time 18962795311 ps
CPU time 14.49 seconds
Started Jun 09 02:29:53 PM PDT 24
Finished Jun 09 02:30:08 PM PDT 24
Peak memory 216144 kb
Host smart-d8db0056-66a2-4d82-adde-e3f79ead3425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435388215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.435388215
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2728608896
Short name T319
Test name
Test status
Simulation time 817233336 ps
CPU time 5.48 seconds
Started Jun 09 02:30:03 PM PDT 24
Finished Jun 09 02:30:09 PM PDT 24
Peak memory 216004 kb
Host smart-006353fc-1079-417b-aa42-388b9ca15ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728608896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2728608896
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3827376020
Short name T362
Test name
Test status
Simulation time 17438965 ps
CPU time 0.7 seconds
Started Jun 09 02:30:01 PM PDT 24
Finished Jun 09 02:30:02 PM PDT 24
Peak memory 205268 kb
Host smart-3d5e1c05-bc5e-4a5d-8df0-a8db7baa6a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827376020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3827376020
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.929269124
Short name T317
Test name
Test status
Simulation time 321337695 ps
CPU time 0.81 seconds
Started Jun 09 02:30:11 PM PDT 24
Finished Jun 09 02:30:12 PM PDT 24
Peak memory 205608 kb
Host smart-36866829-9bae-48e2-a13b-c7e8e08ddfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929269124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.929269124
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3883399890
Short name T903
Test name
Test status
Simulation time 43189121 ps
CPU time 2.38 seconds
Started Jun 09 02:30:00 PM PDT 24
Finished Jun 09 02:30:02 PM PDT 24
Peak memory 224064 kb
Host smart-8f54a2a0-1481-4ed5-89ca-51197a296ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883399890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3883399890
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1459352576
Short name T872
Test name
Test status
Simulation time 23437061 ps
CPU time 0.74 seconds
Started Jun 09 02:30:03 PM PDT 24
Finished Jun 09 02:30:04 PM PDT 24
Peak memory 205160 kb
Host smart-aefbae30-275c-4018-8267-edc978511ad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459352576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1459352576
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2298109072
Short name T873
Test name
Test status
Simulation time 221122323 ps
CPU time 4.63 seconds
Started Jun 09 02:29:56 PM PDT 24
Finished Jun 09 02:30:01 PM PDT 24
Peak memory 224272 kb
Host smart-c7b73e73-646f-470f-97be-cb88ecde6a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298109072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2298109072
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.111532768
Short name T936
Test name
Test status
Simulation time 13245959 ps
CPU time 0.76 seconds
Started Jun 09 02:30:07 PM PDT 24
Finished Jun 09 02:30:08 PM PDT 24
Peak memory 206556 kb
Host smart-c8800b26-c2e9-4dab-b76a-1e0802cab3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111532768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.111532768
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3708317246
Short name T256
Test name
Test status
Simulation time 7993884215 ps
CPU time 17.4 seconds
Started Jun 09 02:30:10 PM PDT 24
Finished Jun 09 02:30:28 PM PDT 24
Peak memory 224396 kb
Host smart-7ab55043-7742-401e-a092-79fbc01dd574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708317246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3708317246
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.4217010664
Short name T28
Test name
Test status
Simulation time 113336147614 ps
CPU time 274.84 seconds
Started Jun 09 02:30:14 PM PDT 24
Finished Jun 09 02:34:49 PM PDT 24
Peak memory 249036 kb
Host smart-a9c8007c-7c6e-4311-bb67-7ba97970f99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217010664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.4217010664
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1997577091
Short name T369
Test name
Test status
Simulation time 13983136253 ps
CPU time 65.83 seconds
Started Jun 09 02:29:58 PM PDT 24
Finished Jun 09 02:31:04 PM PDT 24
Peak memory 256012 kb
Host smart-6a7161df-a2d0-4968-9dda-49a76bcda1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997577091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1997577091
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1777017758
Short name T771
Test name
Test status
Simulation time 420460930 ps
CPU time 7.05 seconds
Started Jun 09 02:30:11 PM PDT 24
Finished Jun 09 02:30:19 PM PDT 24
Peak memory 224304 kb
Host smart-961a68bc-8ad6-4f46-99f3-76250842d3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777017758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1777017758
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1186317660
Short name T446
Test name
Test status
Simulation time 188887454 ps
CPU time 2.11 seconds
Started Jun 09 02:30:00 PM PDT 24
Finished Jun 09 02:30:02 PM PDT 24
Peak memory 222936 kb
Host smart-7b549a76-a2d4-4504-b114-1d0b27fc292d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186317660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1186317660
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2384147050
Short name T513
Test name
Test status
Simulation time 18232123137 ps
CPU time 50 seconds
Started Jun 09 02:30:00 PM PDT 24
Finished Jun 09 02:30:50 PM PDT 24
Peak memory 236700 kb
Host smart-19e551f0-2071-480c-b2f6-5b1405bf1d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384147050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2384147050
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3075215195
Short name T959
Test name
Test status
Simulation time 11921586600 ps
CPU time 22.5 seconds
Started Jun 09 02:30:14 PM PDT 24
Finished Jun 09 02:30:37 PM PDT 24
Peak memory 224336 kb
Host smart-747cee0e-9224-47d7-9d6d-e91f036613f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075215195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3075215195
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2514453488
Short name T552
Test name
Test status
Simulation time 7860005961 ps
CPU time 13.21 seconds
Started Jun 09 02:29:59 PM PDT 24
Finished Jun 09 02:30:12 PM PDT 24
Peak memory 240512 kb
Host smart-af89e922-f940-429e-affe-0b352ca6c623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514453488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2514453488
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.273725602
Short name T564
Test name
Test status
Simulation time 398184610 ps
CPU time 5.06 seconds
Started Jun 09 02:30:03 PM PDT 24
Finished Jun 09 02:30:08 PM PDT 24
Peak memory 222204 kb
Host smart-a4aeda56-c87d-4dd0-96c0-0077a9d60fa3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=273725602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.273725602
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3095500810
Short name T797
Test name
Test status
Simulation time 53571120 ps
CPU time 1.03 seconds
Started Jun 09 02:30:07 PM PDT 24
Finished Jun 09 02:30:08 PM PDT 24
Peak memory 206408 kb
Host smart-e4053ad8-1812-4c09-a4db-6d9e0d4e458f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095500810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3095500810
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4244854403
Short name T290
Test name
Test status
Simulation time 21504270029 ps
CPU time 26.6 seconds
Started Jun 09 02:30:06 PM PDT 24
Finished Jun 09 02:30:33 PM PDT 24
Peak memory 216116 kb
Host smart-b97ff937-fbf3-4c3e-b322-d111b4f46bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244854403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4244854403
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3935256940
Short name T585
Test name
Test status
Simulation time 696121365 ps
CPU time 2.84 seconds
Started Jun 09 02:30:06 PM PDT 24
Finished Jun 09 02:30:09 PM PDT 24
Peak memory 216056 kb
Host smart-206e35df-f9f1-4452-a693-01b87f42826f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935256940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3935256940
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2103605412
Short name T322
Test name
Test status
Simulation time 303242576 ps
CPU time 1.33 seconds
Started Jun 09 02:30:08 PM PDT 24
Finished Jun 09 02:30:10 PM PDT 24
Peak memory 216068 kb
Host smart-26dfaf79-70fa-4c6e-8139-884a7f0b9ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103605412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2103605412
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.385566018
Short name T429
Test name
Test status
Simulation time 389087216 ps
CPU time 0.92 seconds
Started Jun 09 02:30:11 PM PDT 24
Finished Jun 09 02:30:12 PM PDT 24
Peak memory 205596 kb
Host smart-d0d50ecc-e332-42b3-91e5-9e108ee11f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385566018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.385566018
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1963477665
Short name T265
Test name
Test status
Simulation time 16024747754 ps
CPU time 29.39 seconds
Started Jun 09 02:30:06 PM PDT 24
Finished Jun 09 02:30:36 PM PDT 24
Peak memory 240308 kb
Host smart-9bf3b924-5016-437f-8c16-904caf79b86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963477665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1963477665
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.521662343
Short name T729
Test name
Test status
Simulation time 47907559 ps
CPU time 0.72 seconds
Started Jun 09 02:30:00 PM PDT 24
Finished Jun 09 02:30:01 PM PDT 24
Peak memory 205208 kb
Host smart-a714f3de-28be-4aad-85ff-68fb6c3ec47a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521662343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.521662343
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.121393287
Short name T622
Test name
Test status
Simulation time 375960763 ps
CPU time 5.94 seconds
Started Jun 09 02:30:22 PM PDT 24
Finished Jun 09 02:30:29 PM PDT 24
Peak memory 224296 kb
Host smart-fdd59ef9-5db0-407d-b763-fc289b173a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121393287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.121393287
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1492551636
Short name T697
Test name
Test status
Simulation time 49358735 ps
CPU time 0.75 seconds
Started Jun 09 02:30:15 PM PDT 24
Finished Jun 09 02:30:16 PM PDT 24
Peak memory 205204 kb
Host smart-cb38cbd7-b2e3-4020-bed8-7507c0e9c13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492551636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1492551636
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3508839967
Short name T957
Test name
Test status
Simulation time 16602005455 ps
CPU time 112.21 seconds
Started Jun 09 02:30:23 PM PDT 24
Finished Jun 09 02:32:15 PM PDT 24
Peak memory 248992 kb
Host smart-03e875e5-4388-4bf6-a1f1-1d09fb8d97af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508839967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3508839967
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3810676393
Short name T824
Test name
Test status
Simulation time 5423584811 ps
CPU time 8.26 seconds
Started Jun 09 02:30:22 PM PDT 24
Finished Jun 09 02:30:31 PM PDT 24
Peak memory 217168 kb
Host smart-af3705a4-aadd-4093-bce2-9efdbb050bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810676393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3810676393
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2493222902
Short name T578
Test name
Test status
Simulation time 4991385266 ps
CPU time 65.29 seconds
Started Jun 09 02:30:21 PM PDT 24
Finished Jun 09 02:31:27 PM PDT 24
Peak memory 241116 kb
Host smart-18b2f1ad-3213-41ce-be62-fab9c6e08bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493222902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2493222902
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.972064303
Short name T280
Test name
Test status
Simulation time 1040069825 ps
CPU time 6.7 seconds
Started Jun 09 02:30:02 PM PDT 24
Finished Jun 09 02:30:09 PM PDT 24
Peak memory 232532 kb
Host smart-efaff019-d7ec-41df-89c3-e05d69f66857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972064303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.972064303
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3556898626
Short name T540
Test name
Test status
Simulation time 8835223891 ps
CPU time 26.29 seconds
Started Jun 09 02:30:01 PM PDT 24
Finished Jun 09 02:30:28 PM PDT 24
Peak memory 232604 kb
Host smart-4a55911f-13f2-4f31-b08b-1f6f9b0fb214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556898626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3556898626
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1590538480
Short name T568
Test name
Test status
Simulation time 2474828005 ps
CPU time 13.63 seconds
Started Jun 09 02:30:19 PM PDT 24
Finished Jun 09 02:30:33 PM PDT 24
Peak memory 232588 kb
Host smart-c2c7edf2-91a3-4f15-be6c-ce8daaac8bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590538480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1590538480
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1708961260
Short name T932
Test name
Test status
Simulation time 182536476 ps
CPU time 2.13 seconds
Started Jun 09 02:30:17 PM PDT 24
Finished Jun 09 02:30:20 PM PDT 24
Peak memory 218332 kb
Host smart-36e9d48b-baf1-4f28-bf08-593344bcd44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708961260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1708961260
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3871480759
Short name T147
Test name
Test status
Simulation time 708512679 ps
CPU time 2.86 seconds
Started Jun 09 02:30:07 PM PDT 24
Finished Jun 09 02:30:10 PM PDT 24
Peak memory 232536 kb
Host smart-983fb3a7-1605-4257-abcf-4163eb23a5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871480759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3871480759
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2963744625
Short name T852
Test name
Test status
Simulation time 3076739608 ps
CPU time 10.29 seconds
Started Jun 09 02:30:00 PM PDT 24
Finished Jun 09 02:30:10 PM PDT 24
Peak memory 219116 kb
Host smart-6968fe59-072d-4ce7-93b2-44279d8df87e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2963744625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2963744625
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2662283436
Short name T357
Test name
Test status
Simulation time 84329493 ps
CPU time 1 seconds
Started Jun 09 02:30:16 PM PDT 24
Finished Jun 09 02:30:18 PM PDT 24
Peak memory 206400 kb
Host smart-a456bf91-7823-4a6a-be28-dd380929681e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662283436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2662283436
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2065519154
Short name T432
Test name
Test status
Simulation time 19646360778 ps
CPU time 16.06 seconds
Started Jun 09 02:30:03 PM PDT 24
Finished Jun 09 02:30:19 PM PDT 24
Peak memory 216176 kb
Host smart-a80ba399-647f-4e2f-b356-0a9c21edb989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065519154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2065519154
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.341101291
Short name T300
Test name
Test status
Simulation time 8062752545 ps
CPU time 10.46 seconds
Started Jun 09 02:30:03 PM PDT 24
Finished Jun 09 02:30:14 PM PDT 24
Peak memory 216140 kb
Host smart-84a0682b-b0b6-4dc7-9557-cc99eb527e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341101291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.341101291
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.995342595
Short name T52
Test name
Test status
Simulation time 119226737 ps
CPU time 1.49 seconds
Started Jun 09 02:30:02 PM PDT 24
Finished Jun 09 02:30:04 PM PDT 24
Peak memory 207880 kb
Host smart-da15a0a9-3801-4133-b016-feac0cf1b6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995342595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.995342595
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2472500622
Short name T332
Test name
Test status
Simulation time 67607747 ps
CPU time 0.79 seconds
Started Jun 09 02:30:13 PM PDT 24
Finished Jun 09 02:30:15 PM PDT 24
Peak memory 205572 kb
Host smart-5eb6cadb-3a0c-4a82-a4f8-01c78e052c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472500622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2472500622
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.4231808889
Short name T553
Test name
Test status
Simulation time 23328814957 ps
CPU time 21.44 seconds
Started Jun 09 02:30:17 PM PDT 24
Finished Jun 09 02:30:38 PM PDT 24
Peak memory 232584 kb
Host smart-2ccf59a8-bdd3-4462-80a8-ec3d4c13bdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231808889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.4231808889
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3706520249
Short name T974
Test name
Test status
Simulation time 104024538 ps
CPU time 0.71 seconds
Started Jun 09 02:30:05 PM PDT 24
Finished Jun 09 02:30:06 PM PDT 24
Peak memory 205476 kb
Host smart-28f3fadf-2fb8-452c-b7c2-000ef9d711d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706520249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3706520249
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3565724038
Short name T677
Test name
Test status
Simulation time 918135101 ps
CPU time 3.5 seconds
Started Jun 09 02:30:22 PM PDT 24
Finished Jun 09 02:30:26 PM PDT 24
Peak memory 224336 kb
Host smart-9e667107-fb2e-4130-9112-7138caf3419f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565724038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3565724038
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2726263384
Short name T477
Test name
Test status
Simulation time 13126398 ps
CPU time 0.72 seconds
Started Jun 09 02:30:24 PM PDT 24
Finished Jun 09 02:30:25 PM PDT 24
Peak memory 205532 kb
Host smart-0dd76abb-eab6-43c1-9c38-511eef973f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726263384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2726263384
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3063617599
Short name T67
Test name
Test status
Simulation time 18680971479 ps
CPU time 201.87 seconds
Started Jun 09 02:30:03 PM PDT 24
Finished Jun 09 02:33:26 PM PDT 24
Peak memory 249144 kb
Host smart-467eef21-1f92-4c81-836f-9fea0da16683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063617599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3063617599
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2721645481
Short name T888
Test name
Test status
Simulation time 23108424857 ps
CPU time 106.86 seconds
Started Jun 09 02:30:21 PM PDT 24
Finished Jun 09 02:32:08 PM PDT 24
Peak memory 250156 kb
Host smart-5e418e00-b054-4a72-a127-a04ed4d34ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721645481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2721645481
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3252812139
Short name T752
Test name
Test status
Simulation time 1455927387 ps
CPU time 25.75 seconds
Started Jun 09 02:30:03 PM PDT 24
Finished Jun 09 02:30:29 PM PDT 24
Peak memory 224308 kb
Host smart-05ef5ec4-87b5-4100-b221-53186b1c6ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252812139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3252812139
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1360927580
Short name T377
Test name
Test status
Simulation time 3469440779 ps
CPU time 6.8 seconds
Started Jun 09 02:30:05 PM PDT 24
Finished Jun 09 02:30:12 PM PDT 24
Peak memory 232528 kb
Host smart-f4bef60c-5f33-4c51-b752-e7bc9a0250bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360927580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1360927580
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1192458118
Short name T368
Test name
Test status
Simulation time 118376528 ps
CPU time 2.31 seconds
Started Jun 09 02:30:20 PM PDT 24
Finished Jun 09 02:30:23 PM PDT 24
Peak memory 232248 kb
Host smart-a3aa504a-5391-424b-9377-eb461137de62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192458118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1192458118
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2939725414
Short name T451
Test name
Test status
Simulation time 1027044096 ps
CPU time 6.23 seconds
Started Jun 09 02:30:23 PM PDT 24
Finished Jun 09 02:30:29 PM PDT 24
Peak memory 232528 kb
Host smart-c3c9fd7a-4a9a-4f08-8bc4-1e637d654d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939725414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2939725414
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.4106596523
Short name T879
Test name
Test status
Simulation time 4896951733 ps
CPU time 14.48 seconds
Started Jun 09 02:30:06 PM PDT 24
Finished Jun 09 02:30:21 PM PDT 24
Peak memory 222348 kb
Host smart-74b73b6f-be7d-4ed6-a651-b2f90d201877
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4106596523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.4106596523
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2658560331
Short name T136
Test name
Test status
Simulation time 13990815 ps
CPU time 0.72 seconds
Started Jun 09 02:30:13 PM PDT 24
Finished Jun 09 02:30:14 PM PDT 24
Peak memory 205488 kb
Host smart-8f0c7ce8-f71c-4365-ae80-87c29e8cee38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658560331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2658560331
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3427590857
Short name T931
Test name
Test status
Simulation time 1024131405 ps
CPU time 4.68 seconds
Started Jun 09 02:30:10 PM PDT 24
Finished Jun 09 02:30:15 PM PDT 24
Peak memory 216036 kb
Host smart-8dc22dca-b542-4f2c-bfe7-f7598700d256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427590857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3427590857
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3508377467
Short name T40
Test name
Test status
Simulation time 102592114 ps
CPU time 1.75 seconds
Started Jun 09 02:30:24 PM PDT 24
Finished Jun 09 02:30:26 PM PDT 24
Peak memory 216048 kb
Host smart-4f43b6a0-4b45-4515-bc39-4a238f379dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508377467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3508377467
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3321057162
Short name T323
Test name
Test status
Simulation time 64060823 ps
CPU time 0.71 seconds
Started Jun 09 02:30:17 PM PDT 24
Finished Jun 09 02:30:18 PM PDT 24
Peak memory 205588 kb
Host smart-754f7644-a931-4ade-aef8-0e8633aa763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321057162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3321057162
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2749630205
Short name T194
Test name
Test status
Simulation time 832196327 ps
CPU time 4.54 seconds
Started Jun 09 02:30:23 PM PDT 24
Finished Jun 09 02:30:28 PM PDT 24
Peak memory 224404 kb
Host smart-1b8ac17c-efcc-4196-b57f-71e52b73f3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749630205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2749630205
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2025375072
Short name T609
Test name
Test status
Simulation time 100308599 ps
CPU time 0.72 seconds
Started Jun 09 02:29:11 PM PDT 24
Finished Jun 09 02:29:13 PM PDT 24
Peak memory 205172 kb
Host smart-e561d916-b49f-468c-8255-15dc9b78db56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025375072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
025375072
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2276535538
Short name T64
Test name
Test status
Simulation time 34359751 ps
CPU time 2.25 seconds
Started Jun 09 02:29:05 PM PDT 24
Finished Jun 09 02:29:08 PM PDT 24
Peak memory 232280 kb
Host smart-874146c4-502f-4d84-b84d-11f1bfafda98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276535538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2276535538
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3850732759
Short name T305
Test name
Test status
Simulation time 138773644 ps
CPU time 0.79 seconds
Started Jun 09 02:29:03 PM PDT 24
Finished Jun 09 02:29:05 PM PDT 24
Peak memory 206232 kb
Host smart-a4ba50a2-fe77-4022-898e-18882ca3b17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850732759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3850732759
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3240417912
Short name T273
Test name
Test status
Simulation time 95735682529 ps
CPU time 217.05 seconds
Started Jun 09 02:29:03 PM PDT 24
Finished Jun 09 02:32:40 PM PDT 24
Peak memory 253392 kb
Host smart-64f1ff18-c016-4218-895c-6c818a8e038f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240417912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3240417912
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2847426551
Short name T223
Test name
Test status
Simulation time 4354596598 ps
CPU time 22.2 seconds
Started Jun 09 02:29:01 PM PDT 24
Finished Jun 09 02:29:23 PM PDT 24
Peak memory 235836 kb
Host smart-1d0292db-eede-4335-8253-17bc49484888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847426551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2847426551
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.4174254692
Short name T284
Test name
Test status
Simulation time 16188451519 ps
CPU time 43.05 seconds
Started Jun 09 02:29:04 PM PDT 24
Finished Jun 09 02:29:47 PM PDT 24
Peak memory 232588 kb
Host smart-e1635abb-9388-4c7a-8a8a-d9fce5a3804a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174254692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.4174254692
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2911905949
Short name T750
Test name
Test status
Simulation time 179361972 ps
CPU time 3.32 seconds
Started Jun 09 02:29:14 PM PDT 24
Finished Jun 09 02:29:18 PM PDT 24
Peak memory 224276 kb
Host smart-f44a0ccf-c680-4c4a-af46-cc563d44b1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911905949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2911905949
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1273281644
Short name T692
Test name
Test status
Simulation time 7934903335 ps
CPU time 16.79 seconds
Started Jun 09 02:28:55 PM PDT 24
Finished Jun 09 02:29:12 PM PDT 24
Peak memory 239820 kb
Host smart-7db39f24-6d8a-4896-8a6c-f938fee918dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273281644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1273281644
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.501076706
Short name T399
Test name
Test status
Simulation time 29206547 ps
CPU time 1.17 seconds
Started Jun 09 02:29:02 PM PDT 24
Finished Jun 09 02:29:04 PM PDT 24
Peak memory 216384 kb
Host smart-e21d321f-f2ca-4e7d-9de7-0295a96f4d51
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501076706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.501076706
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3821163090
Short name T892
Test name
Test status
Simulation time 503970642 ps
CPU time 3.93 seconds
Started Jun 09 02:29:07 PM PDT 24
Finished Jun 09 02:29:12 PM PDT 24
Peak memory 224296 kb
Host smart-ee26caac-1b90-45b6-a717-98bbcf3befce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821163090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3821163090
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1149333819
Short name T915
Test name
Test status
Simulation time 680434288 ps
CPU time 3.06 seconds
Started Jun 09 02:28:59 PM PDT 24
Finished Jun 09 02:29:02 PM PDT 24
Peak memory 232540 kb
Host smart-9c2c5ff3-a3e7-4266-8866-acc8f13f45fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149333819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1149333819
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3061167381
Short name T638
Test name
Test status
Simulation time 1275511367 ps
CPU time 8.42 seconds
Started Jun 09 02:28:59 PM PDT 24
Finished Jun 09 02:29:08 PM PDT 24
Peak memory 218596 kb
Host smart-c926cf52-15d0-4449-8ee9-0badc56bcadd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3061167381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3061167381
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4204781195
Short name T59
Test name
Test status
Simulation time 505382038 ps
CPU time 1.22 seconds
Started Jun 09 02:29:12 PM PDT 24
Finished Jun 09 02:29:14 PM PDT 24
Peak memory 234916 kb
Host smart-4dcc40e0-0899-4654-9f6d-41e5868a3af4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204781195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4204781195
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.184723316
Short name T758
Test name
Test status
Simulation time 460284682 ps
CPU time 1.08 seconds
Started Jun 09 02:29:06 PM PDT 24
Finished Jun 09 02:29:07 PM PDT 24
Peak memory 206704 kb
Host smart-4cd57286-1895-4b43-b59f-3812ae306215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184723316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.184723316
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3962414025
Short name T625
Test name
Test status
Simulation time 1929539330 ps
CPU time 10.35 seconds
Started Jun 09 02:29:03 PM PDT 24
Finished Jun 09 02:29:13 PM PDT 24
Peak memory 216220 kb
Host smart-788f7df5-511e-4366-bd99-3c32a42bd380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962414025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3962414025
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2322437365
Short name T848
Test name
Test status
Simulation time 18147922 ps
CPU time 0.73 seconds
Started Jun 09 02:29:01 PM PDT 24
Finished Jun 09 02:29:02 PM PDT 24
Peak memory 205328 kb
Host smart-7b35b804-4152-4d84-abed-98a532e0d4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322437365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2322437365
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3554684188
Short name T581
Test name
Test status
Simulation time 264271890 ps
CPU time 1.02 seconds
Started Jun 09 02:29:01 PM PDT 24
Finished Jun 09 02:29:02 PM PDT 24
Peak memory 207108 kb
Host smart-a009664b-6764-4d41-8d52-e9aed6757c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554684188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3554684188
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.525575669
Short name T649
Test name
Test status
Simulation time 34601863 ps
CPU time 0.79 seconds
Started Jun 09 02:28:59 PM PDT 24
Finished Jun 09 02:29:00 PM PDT 24
Peak memory 205628 kb
Host smart-a8bf2069-a092-4ff9-8a5d-8c4ec2a41a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525575669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.525575669
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3755350120
Short name T800
Test name
Test status
Simulation time 2416246523 ps
CPU time 11.81 seconds
Started Jun 09 02:29:08 PM PDT 24
Finished Jun 09 02:29:20 PM PDT 24
Peak memory 232564 kb
Host smart-c5dce0b1-0e8e-439e-938a-6f1c01c0b7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755350120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3755350120
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1278875959
Short name T587
Test name
Test status
Simulation time 32049892 ps
CPU time 0.67 seconds
Started Jun 09 02:30:13 PM PDT 24
Finished Jun 09 02:30:14 PM PDT 24
Peak memory 205184 kb
Host smart-f9715fab-712a-40b5-a4a7-cc2a674baa14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278875959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1278875959
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2130467044
Short name T817
Test name
Test status
Simulation time 481415806 ps
CPU time 3.34 seconds
Started Jun 09 02:30:04 PM PDT 24
Finished Jun 09 02:30:08 PM PDT 24
Peak memory 224328 kb
Host smart-0803c407-f59a-4af2-92e7-86ddaf1c0dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130467044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2130467044
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.37314863
Short name T648
Test name
Test status
Simulation time 41023417 ps
CPU time 0.82 seconds
Started Jun 09 02:30:28 PM PDT 24
Finished Jun 09 02:30:29 PM PDT 24
Peak memory 206372 kb
Host smart-2a38dd75-fa8d-4af3-8b89-fd94b4082433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37314863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.37314863
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1526424562
Short name T347
Test name
Test status
Simulation time 29487045122 ps
CPU time 54.77 seconds
Started Jun 09 02:30:25 PM PDT 24
Finished Jun 09 02:31:21 PM PDT 24
Peak memory 234792 kb
Host smart-cb0db90e-c6a6-44a3-a35c-fc1513c6587c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526424562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1526424562
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1317571397
Short name T227
Test name
Test status
Simulation time 28241487630 ps
CPU time 282.16 seconds
Started Jun 09 02:30:08 PM PDT 24
Finished Jun 09 02:34:50 PM PDT 24
Peak memory 252616 kb
Host smart-3c42b3b4-f4d3-4148-a11b-8ecdce94df1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317571397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1317571397
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.661144109
Short name T126
Test name
Test status
Simulation time 75408668610 ps
CPU time 709.29 seconds
Started Jun 09 02:30:22 PM PDT 24
Finished Jun 09 02:42:11 PM PDT 24
Peak memory 263472 kb
Host smart-54bf31b3-f374-4a0e-808d-4bda5560a570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661144109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.661144109
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1901397403
Short name T38
Test name
Test status
Simulation time 104735268 ps
CPU time 3.33 seconds
Started Jun 09 02:30:05 PM PDT 24
Finished Jun 09 02:30:08 PM PDT 24
Peak memory 232524 kb
Host smart-555f5f7e-c932-41af-a496-3c0a902bd7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901397403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1901397403
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1046456056
Short name T266
Test name
Test status
Simulation time 1418931614 ps
CPU time 8.17 seconds
Started Jun 09 02:30:05 PM PDT 24
Finished Jun 09 02:30:14 PM PDT 24
Peak memory 224260 kb
Host smart-9607fcb6-ef5d-4c45-8167-50a4af7cb84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046456056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1046456056
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.241792771
Short name T545
Test name
Test status
Simulation time 18375006576 ps
CPU time 43.89 seconds
Started Jun 09 02:30:05 PM PDT 24
Finished Jun 09 02:30:49 PM PDT 24
Peak memory 232584 kb
Host smart-2849888d-9085-4e6b-a2a1-89bf42067270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241792771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.241792771
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3109373173
Short name T340
Test name
Test status
Simulation time 10215152315 ps
CPU time 9.89 seconds
Started Jun 09 02:30:06 PM PDT 24
Finished Jun 09 02:30:16 PM PDT 24
Peak memory 232612 kb
Host smart-32824ba1-0462-4b82-8fad-bafeb0503417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109373173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3109373173
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.405435668
Short name T783
Test name
Test status
Simulation time 4134942205 ps
CPU time 8.38 seconds
Started Jun 09 02:30:06 PM PDT 24
Finished Jun 09 02:30:14 PM PDT 24
Peak memory 240584 kb
Host smart-cfd935aa-d9c7-4dfa-98fc-d3156cc72e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405435668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.405435668
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.35426667
Short name T810
Test name
Test status
Simulation time 4485267237 ps
CPU time 7.74 seconds
Started Jun 09 02:30:05 PM PDT 24
Finished Jun 09 02:30:13 PM PDT 24
Peak memory 219784 kb
Host smart-6eb26790-468e-4020-8dc0-88ecf708bb8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=35426667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direc
t.35426667
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1775055474
Short name T557
Test name
Test status
Simulation time 3190418031 ps
CPU time 72.46 seconds
Started Jun 09 02:30:09 PM PDT 24
Finished Jun 09 02:31:21 PM PDT 24
Peak memory 249028 kb
Host smart-d95d7e95-f9b6-4661-b1b8-8d73ae9949d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775055474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1775055474
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3853464840
Short name T642
Test name
Test status
Simulation time 442422427 ps
CPU time 7.71 seconds
Started Jun 09 02:30:24 PM PDT 24
Finished Jun 09 02:30:32 PM PDT 24
Peak memory 218576 kb
Host smart-96a22edd-0fdb-4220-a6a2-4f402e7678e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853464840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3853464840
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.560269172
Short name T380
Test name
Test status
Simulation time 354781779 ps
CPU time 2.44 seconds
Started Jun 09 02:30:20 PM PDT 24
Finished Jun 09 02:30:23 PM PDT 24
Peak memory 216008 kb
Host smart-14622b81-9e07-4397-807c-a86402aa1c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560269172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.560269172
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2190318438
Short name T450
Test name
Test status
Simulation time 1707692209 ps
CPU time 2.86 seconds
Started Jun 09 02:30:19 PM PDT 24
Finished Jun 09 02:30:22 PM PDT 24
Peak memory 216024 kb
Host smart-10d5d666-d41a-45b1-acfc-bd17b7e83fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190318438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2190318438
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3847670658
Short name T850
Test name
Test status
Simulation time 37485331 ps
CPU time 0.71 seconds
Started Jun 09 02:30:05 PM PDT 24
Finished Jun 09 02:30:06 PM PDT 24
Peak memory 205472 kb
Host smart-29733cfe-01b7-4de6-900b-1547beea9a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847670658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3847670658
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1212755945
Short name T418
Test name
Test status
Simulation time 39197433 ps
CPU time 2.52 seconds
Started Jun 09 02:30:07 PM PDT 24
Finished Jun 09 02:30:09 PM PDT 24
Peak memory 224072 kb
Host smart-086648a8-3bcc-4b2a-92b2-3ce700c508c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212755945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1212755945
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1160096240
Short name T7
Test name
Test status
Simulation time 12003728 ps
CPU time 0.68 seconds
Started Jun 09 02:30:11 PM PDT 24
Finished Jun 09 02:30:12 PM PDT 24
Peak memory 205536 kb
Host smart-3493b473-85dc-432e-b5ad-b66512fc7d04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160096240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1160096240
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3867043984
Short name T448
Test name
Test status
Simulation time 33993154 ps
CPU time 2.5 seconds
Started Jun 09 02:30:07 PM PDT 24
Finished Jun 09 02:30:10 PM PDT 24
Peak memory 232324 kb
Host smart-216b2640-923c-4f4e-8040-fcf6a31346ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867043984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3867043984
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3287768965
Short name T789
Test name
Test status
Simulation time 40682180 ps
CPU time 0.83 seconds
Started Jun 09 02:30:10 PM PDT 24
Finished Jun 09 02:30:11 PM PDT 24
Peak memory 206252 kb
Host smart-96d4fe35-6419-4f17-abfa-b27529bbe814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287768965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3287768965
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2023315938
Short name T680
Test name
Test status
Simulation time 17506098 ps
CPU time 0.74 seconds
Started Jun 09 02:30:23 PM PDT 24
Finished Jun 09 02:30:25 PM PDT 24
Peak memory 215708 kb
Host smart-452fb489-bbb4-4a80-99d3-f04138b05ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023315938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2023315938
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2583432866
Short name T497
Test name
Test status
Simulation time 4821538392 ps
CPU time 49.07 seconds
Started Jun 09 02:30:26 PM PDT 24
Finished Jun 09 02:31:15 PM PDT 24
Peak memory 251820 kb
Host smart-1860ce18-e07f-49df-8f24-81eb89651535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583432866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2583432866
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.822899908
Short name T640
Test name
Test status
Simulation time 1733619084 ps
CPU time 28.57 seconds
Started Jun 09 02:30:22 PM PDT 24
Finished Jun 09 02:30:51 PM PDT 24
Peak memory 224360 kb
Host smart-582790f0-0f14-4748-9d3b-68ba12ab58ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822899908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.822899908
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.825178244
Short name T131
Test name
Test status
Simulation time 1283963294 ps
CPU time 16.98 seconds
Started Jun 09 02:30:08 PM PDT 24
Finished Jun 09 02:30:25 PM PDT 24
Peak memory 224332 kb
Host smart-6956f5ca-00ba-4e50-942c-9650faf31df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825178244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.825178244
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.952336631
Short name T521
Test name
Test status
Simulation time 2419489072 ps
CPU time 3.07 seconds
Started Jun 09 02:30:22 PM PDT 24
Finished Jun 09 02:30:25 PM PDT 24
Peak memory 224336 kb
Host smart-ebd85f76-c1a5-4101-b4a3-c503a8f49430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952336631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.952336631
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.798012301
Short name T270
Test name
Test status
Simulation time 16287666147 ps
CPU time 34.13 seconds
Started Jun 09 02:30:08 PM PDT 24
Finished Jun 09 02:30:43 PM PDT 24
Peak memory 232576 kb
Host smart-1aaaaea4-56da-4f00-8c87-ece69e581a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798012301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.798012301
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.631794353
Short name T158
Test name
Test status
Simulation time 442931216 ps
CPU time 5.36 seconds
Started Jun 09 02:30:07 PM PDT 24
Finished Jun 09 02:30:12 PM PDT 24
Peak memory 240472 kb
Host smart-c10326e7-f5d2-4a8b-882b-8dd121335ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631794353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.631794353
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3359970237
Short name T590
Test name
Test status
Simulation time 1484841562 ps
CPU time 13.3 seconds
Started Jun 09 02:30:19 PM PDT 24
Finished Jun 09 02:30:33 PM PDT 24
Peak memory 239864 kb
Host smart-6d919403-664b-4e87-b107-7c905091a491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359970237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3359970237
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2015874728
Short name T836
Test name
Test status
Simulation time 112156666 ps
CPU time 3.65 seconds
Started Jun 09 02:30:25 PM PDT 24
Finished Jun 09 02:30:29 PM PDT 24
Peak memory 222988 kb
Host smart-496da291-6780-4f4d-a56c-42c39ba4357b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2015874728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2015874728
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3162507918
Short name T447
Test name
Test status
Simulation time 2504550466 ps
CPU time 30.38 seconds
Started Jun 09 02:30:28 PM PDT 24
Finished Jun 09 02:30:59 PM PDT 24
Peak memory 220440 kb
Host smart-d4b06b42-5329-4631-acc5-ceaa59eb4e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162507918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3162507918
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1212330057
Short name T527
Test name
Test status
Simulation time 827529092 ps
CPU time 2.8 seconds
Started Jun 09 02:30:16 PM PDT 24
Finished Jun 09 02:30:19 PM PDT 24
Peak memory 216008 kb
Host smart-c2253934-927e-4d04-b8ba-225d20b1d712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212330057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1212330057
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3576995021
Short name T536
Test name
Test status
Simulation time 343183280 ps
CPU time 2.24 seconds
Started Jun 09 02:30:14 PM PDT 24
Finished Jun 09 02:30:17 PM PDT 24
Peak memory 216252 kb
Host smart-055f38a5-ab4e-472d-b20f-6597b2dd0018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576995021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3576995021
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2399432465
Short name T71
Test name
Test status
Simulation time 51757682 ps
CPU time 0.81 seconds
Started Jun 09 02:30:10 PM PDT 24
Finished Jun 09 02:30:11 PM PDT 24
Peak memory 205596 kb
Host smart-60f0df4a-2180-401a-bb12-2eddc3529386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399432465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2399432465
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3484112173
Short name T170
Test name
Test status
Simulation time 5858339439 ps
CPU time 7.35 seconds
Started Jun 09 02:30:11 PM PDT 24
Finished Jun 09 02:30:18 PM PDT 24
Peak memory 232580 kb
Host smart-de3543a6-7ad0-4bac-a288-0dfbaa4ac94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484112173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3484112173
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.889145963
Short name T579
Test name
Test status
Simulation time 54091872 ps
CPU time 0.71 seconds
Started Jun 09 02:30:31 PM PDT 24
Finished Jun 09 02:30:32 PM PDT 24
Peak memory 205160 kb
Host smart-182f25bc-65cc-42b5-a97e-dcc5a36c5be7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889145963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.889145963
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3985594701
Short name T190
Test name
Test status
Simulation time 662329116 ps
CPU time 3.81 seconds
Started Jun 09 02:30:27 PM PDT 24
Finished Jun 09 02:30:32 PM PDT 24
Peak memory 232616 kb
Host smart-4c2edd54-de28-4a62-8389-2003c10d3d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985594701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3985594701
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3257637887
Short name T388
Test name
Test status
Simulation time 61705798 ps
CPU time 0.77 seconds
Started Jun 09 02:30:25 PM PDT 24
Finished Jun 09 02:30:27 PM PDT 24
Peak memory 206684 kb
Host smart-ee02527e-16ec-4611-899b-9d047daab81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257637887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3257637887
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2780508200
Short name T733
Test name
Test status
Simulation time 18657691223 ps
CPU time 116.92 seconds
Started Jun 09 02:30:14 PM PDT 24
Finished Jun 09 02:32:11 PM PDT 24
Peak memory 256348 kb
Host smart-6a444496-7a90-427c-9731-88fe65ccdf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780508200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2780508200
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3440779781
Short name T17
Test name
Test status
Simulation time 3156714136 ps
CPU time 56.31 seconds
Started Jun 09 02:30:22 PM PDT 24
Finished Jun 09 02:31:19 PM PDT 24
Peak memory 252372 kb
Host smart-229b677b-1a61-47bf-ac92-18331bd02475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440779781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3440779781
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.4226081057
Short name T259
Test name
Test status
Simulation time 3917895637 ps
CPU time 45.29 seconds
Started Jun 09 02:30:18 PM PDT 24
Finished Jun 09 02:31:03 PM PDT 24
Peak memory 248688 kb
Host smart-86d6221b-f0c2-4b2d-86cd-a8237f56f793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226081057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.4226081057
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2345540881
Short name T738
Test name
Test status
Simulation time 201072929 ps
CPU time 6.71 seconds
Started Jun 09 02:30:22 PM PDT 24
Finished Jun 09 02:30:29 PM PDT 24
Peak memory 240712 kb
Host smart-9103f17d-d04c-447b-a4f5-21138813d685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345540881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2345540881
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1173707695
Short name T51
Test name
Test status
Simulation time 4392796624 ps
CPU time 14.96 seconds
Started Jun 09 02:30:12 PM PDT 24
Finished Jun 09 02:30:27 PM PDT 24
Peak memory 221900 kb
Host smart-765d777f-b95c-4fcd-a668-d69349575d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173707695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1173707695
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.563824537
Short name T179
Test name
Test status
Simulation time 221806009 ps
CPU time 2.87 seconds
Started Jun 09 02:30:11 PM PDT 24
Finished Jun 09 02:30:14 PM PDT 24
Peak memory 224240 kb
Host smart-4e8fef28-c289-4e71-81ea-b59ea40f3bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563824537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.563824537
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2493662592
Short name T573
Test name
Test status
Simulation time 2045286964 ps
CPU time 3.52 seconds
Started Jun 09 02:30:10 PM PDT 24
Finished Jun 09 02:30:14 PM PDT 24
Peak memory 224312 kb
Host smart-79ab8270-f619-454c-9c38-d0971c179729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493662592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2493662592
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1574602773
Short name T404
Test name
Test status
Simulation time 8310821997 ps
CPU time 7.54 seconds
Started Jun 09 02:30:09 PM PDT 24
Finished Jun 09 02:30:17 PM PDT 24
Peak memory 224344 kb
Host smart-16203692-0806-47ca-a991-527084646034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574602773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1574602773
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.597018150
Short name T44
Test name
Test status
Simulation time 2061712838 ps
CPU time 8.25 seconds
Started Jun 09 02:30:12 PM PDT 24
Finished Jun 09 02:30:20 PM PDT 24
Peak memory 222264 kb
Host smart-e7624b7c-374b-46d6-9c38-104e8af4439b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=597018150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.597018150
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.4183098707
Short name T737
Test name
Test status
Simulation time 19247911577 ps
CPU time 16.6 seconds
Started Jun 09 02:30:08 PM PDT 24
Finished Jun 09 02:30:25 PM PDT 24
Peak memory 215968 kb
Host smart-dbf30e7a-5717-4cbc-b3f3-4a622ebc92e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183098707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.4183098707
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.561017834
Short name T316
Test name
Test status
Simulation time 206261211 ps
CPU time 1.74 seconds
Started Jun 09 02:30:09 PM PDT 24
Finished Jun 09 02:30:11 PM PDT 24
Peak memory 207640 kb
Host smart-e564cbe0-1a2e-4ad3-8a10-214a2aa596b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561017834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.561017834
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.712275582
Short name T904
Test name
Test status
Simulation time 54209210 ps
CPU time 1.36 seconds
Started Jun 09 02:30:08 PM PDT 24
Finished Jun 09 02:30:09 PM PDT 24
Peak memory 215864 kb
Host smart-5f85f713-27f5-4ca3-bec4-2c41ff236c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712275582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.712275582
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.417113017
Short name T732
Test name
Test status
Simulation time 20717282 ps
CPU time 0.75 seconds
Started Jun 09 02:30:27 PM PDT 24
Finished Jun 09 02:30:28 PM PDT 24
Peak memory 205588 kb
Host smart-d7857633-5b34-4ffa-b19a-27bc9e989bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417113017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.417113017
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.4287641693
Short name T164
Test name
Test status
Simulation time 2731948622 ps
CPU time 10.08 seconds
Started Jun 09 02:30:25 PM PDT 24
Finished Jun 09 02:30:36 PM PDT 24
Peak memory 232592 kb
Host smart-beb32688-be3b-448b-9a59-f3eed78214de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287641693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4287641693
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3321470559
Short name T524
Test name
Test status
Simulation time 12802624 ps
CPU time 0.68 seconds
Started Jun 09 02:30:36 PM PDT 24
Finished Jun 09 02:30:37 PM PDT 24
Peak memory 205044 kb
Host smart-91318a56-1607-4f4c-9325-a6012e4aa881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321470559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3321470559
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.206390692
Short name T247
Test name
Test status
Simulation time 379976036 ps
CPU time 3.59 seconds
Started Jun 09 02:30:24 PM PDT 24
Finished Jun 09 02:30:27 PM PDT 24
Peak memory 224280 kb
Host smart-76730656-33cd-4d6a-b631-28a7f29a1a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206390692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.206390692
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.68389518
Short name T634
Test name
Test status
Simulation time 38790659 ps
CPU time 0.82 seconds
Started Jun 09 02:30:11 PM PDT 24
Finished Jun 09 02:30:12 PM PDT 24
Peak memory 206216 kb
Host smart-e835f00d-0972-43b7-917d-ac86f0cfeea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68389518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.68389518
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.572963034
Short name T709
Test name
Test status
Simulation time 1969417336 ps
CPU time 33.18 seconds
Started Jun 09 02:30:12 PM PDT 24
Finished Jun 09 02:30:46 PM PDT 24
Peak memory 240736 kb
Host smart-539fd731-2234-4b4f-b99a-7db88f5b911e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572963034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.572963034
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2833727947
Short name T264
Test name
Test status
Simulation time 6602191325 ps
CPU time 24.84 seconds
Started Jun 09 02:30:17 PM PDT 24
Finished Jun 09 02:30:42 PM PDT 24
Peak memory 224656 kb
Host smart-b5bf67e3-b13a-4824-85b9-3e51c3bc560d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833727947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2833727947
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2004585000
Short name T923
Test name
Test status
Simulation time 4705770188 ps
CPU time 60.89 seconds
Started Jun 09 02:30:23 PM PDT 24
Finished Jun 09 02:31:25 PM PDT 24
Peak memory 237428 kb
Host smart-483e8c2f-726a-478a-bcec-6ecc1fcf0e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004585000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2004585000
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3418152003
Short name T132
Test name
Test status
Simulation time 2286137825 ps
CPU time 12.08 seconds
Started Jun 09 02:30:32 PM PDT 24
Finished Jun 09 02:30:44 PM PDT 24
Peak memory 233520 kb
Host smart-e4665ccc-88d2-4674-9048-1946fe231c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418152003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3418152003
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1394314846
Short name T462
Test name
Test status
Simulation time 73291111 ps
CPU time 2.31 seconds
Started Jun 09 02:30:34 PM PDT 24
Finished Jun 09 02:30:37 PM PDT 24
Peak memory 222784 kb
Host smart-cd477e41-3d8d-4e6c-98e6-787d4a85f260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394314846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1394314846
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.4022776214
Short name T715
Test name
Test status
Simulation time 17155754471 ps
CPU time 46.21 seconds
Started Jun 09 02:30:27 PM PDT 24
Finished Jun 09 02:31:14 PM PDT 24
Peak memory 232564 kb
Host smart-80c973ba-0188-4274-ad9b-42cedcfcbaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022776214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.4022776214
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1595111929
Short name T198
Test name
Test status
Simulation time 2479841291 ps
CPU time 3.6 seconds
Started Jun 09 02:30:37 PM PDT 24
Finished Jun 09 02:30:41 PM PDT 24
Peak memory 224268 kb
Host smart-e35c8b59-d5e2-411f-8275-31d2d0bf1168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595111929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1595111929
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1825534627
Short name T172
Test name
Test status
Simulation time 14928861842 ps
CPU time 23.48 seconds
Started Jun 09 02:30:35 PM PDT 24
Finished Jun 09 02:30:59 PM PDT 24
Peak memory 232620 kb
Host smart-db501615-4acd-43d1-8f11-158338806b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825534627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1825534627
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1308475198
Short name T415
Test name
Test status
Simulation time 5043405026 ps
CPU time 6.9 seconds
Started Jun 09 02:30:29 PM PDT 24
Finished Jun 09 02:30:36 PM PDT 24
Peak memory 218992 kb
Host smart-943657da-aeed-4132-a585-ebe69f15e2d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1308475198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1308475198
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2342052844
Short name T276
Test name
Test status
Simulation time 35693294945 ps
CPU time 240.9 seconds
Started Jun 09 02:30:33 PM PDT 24
Finished Jun 09 02:34:35 PM PDT 24
Peak memory 283996 kb
Host smart-43746262-c9a3-4c69-a70d-95384167ce2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342052844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2342052844
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3972183382
Short name T390
Test name
Test status
Simulation time 1937945213 ps
CPU time 26.87 seconds
Started Jun 09 02:30:26 PM PDT 24
Finished Jun 09 02:30:53 PM PDT 24
Peak memory 216068 kb
Host smart-bfe3f92f-e6e8-4cd9-a5f0-e1cc1c748f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972183382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3972183382
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1157900293
Short name T663
Test name
Test status
Simulation time 2231879462 ps
CPU time 11.14 seconds
Started Jun 09 02:30:19 PM PDT 24
Finished Jun 09 02:30:30 PM PDT 24
Peak memory 216120 kb
Host smart-34e2ccbd-f20f-42a4-a994-b8c654a9d1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157900293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1157900293
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2198177072
Short name T865
Test name
Test status
Simulation time 41741294 ps
CPU time 1.44 seconds
Started Jun 09 02:30:24 PM PDT 24
Finished Jun 09 02:30:26 PM PDT 24
Peak memory 216052 kb
Host smart-636af518-5812-46fb-9274-1c8008d7419d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198177072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2198177072
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.518875840
Short name T73
Test name
Test status
Simulation time 439115829 ps
CPU time 1.04 seconds
Started Jun 09 02:30:26 PM PDT 24
Finished Jun 09 02:30:27 PM PDT 24
Peak memory 206624 kb
Host smart-ba2d6724-e053-4d9a-b97f-98c06723bdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518875840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.518875840
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.4113012426
Short name T895
Test name
Test status
Simulation time 31910485585 ps
CPU time 24.55 seconds
Started Jun 09 02:30:23 PM PDT 24
Finished Jun 09 02:30:47 PM PDT 24
Peak memory 232616 kb
Host smart-bda14f1a-b57b-4ed7-a367-1072ee4134ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113012426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.4113012426
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.11842434
Short name T826
Test name
Test status
Simulation time 16517795 ps
CPU time 0.73 seconds
Started Jun 09 02:30:31 PM PDT 24
Finished Jun 09 02:30:32 PM PDT 24
Peak memory 205520 kb
Host smart-ed9bdc35-7418-4bdb-916c-32400f0cf3de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11842434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.11842434
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.4267711364
Short name T745
Test name
Test status
Simulation time 1130316973 ps
CPU time 6.64 seconds
Started Jun 09 02:30:32 PM PDT 24
Finished Jun 09 02:30:39 PM PDT 24
Peak memory 224360 kb
Host smart-03cc4603-b82b-45be-8390-3ff8ca2fe17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267711364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.4267711364
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1668696098
Short name T588
Test name
Test status
Simulation time 25787640 ps
CPU time 0.76 seconds
Started Jun 09 02:30:28 PM PDT 24
Finished Jun 09 02:30:29 PM PDT 24
Peak memory 206560 kb
Host smart-0843cf29-9371-4564-8718-9410f38cfead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668696098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1668696098
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.383494719
Short name T712
Test name
Test status
Simulation time 5215004131 ps
CPU time 67.88 seconds
Started Jun 09 02:30:28 PM PDT 24
Finished Jun 09 02:31:36 PM PDT 24
Peak memory 249144 kb
Host smart-5de90dbb-5aa8-4b91-a472-045b82af7e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383494719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.383494719
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3141167164
Short name T203
Test name
Test status
Simulation time 77019478868 ps
CPU time 700.52 seconds
Started Jun 09 02:30:34 PM PDT 24
Finished Jun 09 02:42:15 PM PDT 24
Peak memory 249080 kb
Host smart-3322b30a-30a9-4925-b278-dc9e8a5ac913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141167164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3141167164
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1987854664
Short name T483
Test name
Test status
Simulation time 928690504 ps
CPU time 13.9 seconds
Started Jun 09 02:30:27 PM PDT 24
Finished Jun 09 02:30:41 PM PDT 24
Peak memory 224388 kb
Host smart-2324edfa-1de4-468a-8942-1b93d4382914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987854664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1987854664
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1286879534
Short name T819
Test name
Test status
Simulation time 437995962 ps
CPU time 9.09 seconds
Started Jun 09 02:30:19 PM PDT 24
Finished Jun 09 02:30:28 PM PDT 24
Peak memory 224324 kb
Host smart-18c4e951-7d79-4ac2-b2e4-cadd8ac67034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286879534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1286879534
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3547233
Short name T455
Test name
Test status
Simulation time 832025185 ps
CPU time 4.84 seconds
Started Jun 09 02:30:36 PM PDT 24
Finished Jun 09 02:30:41 PM PDT 24
Peak memory 224292 kb
Host smart-5aa07647-aa20-436d-816c-2430ea7d7849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3547233
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2366064054
Short name T519
Test name
Test status
Simulation time 7767690215 ps
CPU time 22.33 seconds
Started Jun 09 02:30:31 PM PDT 24
Finished Jun 09 02:30:53 PM PDT 24
Peak memory 232608 kb
Host smart-a3aaf212-651c-4cb6-94de-5ed280340090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366064054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2366064054
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3240200285
Short name T384
Test name
Test status
Simulation time 374351210 ps
CPU time 5.44 seconds
Started Jun 09 02:30:35 PM PDT 24
Finished Jun 09 02:30:41 PM PDT 24
Peak memory 232436 kb
Host smart-36ee6f7d-697f-4c8e-8a12-16ab05764fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240200285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3240200285
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.4277207745
Short name T182
Test name
Test status
Simulation time 16982764999 ps
CPU time 11.06 seconds
Started Jun 09 02:30:31 PM PDT 24
Finished Jun 09 02:30:43 PM PDT 24
Peak memory 224340 kb
Host smart-7d6b8d4e-1c50-4663-bf52-a35eae686225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277207745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4277207745
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3914310788
Short name T608
Test name
Test status
Simulation time 2700190417 ps
CPU time 9.74 seconds
Started Jun 09 02:30:25 PM PDT 24
Finished Jun 09 02:30:36 PM PDT 24
Peak memory 222956 kb
Host smart-38bd9e16-e456-4031-b708-e517535e3852
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3914310788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3914310788
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2287507433
Short name T65
Test name
Test status
Simulation time 44128764234 ps
CPU time 275.44 seconds
Started Jun 09 02:30:22 PM PDT 24
Finished Jun 09 02:34:58 PM PDT 24
Peak memory 267536 kb
Host smart-a056d6e0-5018-4fdb-ac16-76a11577849f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287507433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2287507433
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3018403027
Short name T606
Test name
Test status
Simulation time 50960187041 ps
CPU time 25.67 seconds
Started Jun 09 02:30:35 PM PDT 24
Finished Jun 09 02:31:01 PM PDT 24
Peak memory 216168 kb
Host smart-1cc816a5-ad03-4c77-8bfb-261330898df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018403027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3018403027
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1527118562
Short name T489
Test name
Test status
Simulation time 5163868037 ps
CPU time 15.61 seconds
Started Jun 09 02:30:36 PM PDT 24
Finished Jun 09 02:30:52 PM PDT 24
Peak memory 216120 kb
Host smart-e9393900-85e3-4796-b350-d1f57bc2a4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527118562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1527118562
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3823241856
Short name T413
Test name
Test status
Simulation time 11921897 ps
CPU time 0.72 seconds
Started Jun 09 02:30:25 PM PDT 24
Finished Jun 09 02:30:26 PM PDT 24
Peak memory 205272 kb
Host smart-1b39b566-45b4-4ce0-b549-d395e3d80c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823241856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3823241856
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3954410377
Short name T776
Test name
Test status
Simulation time 92637528 ps
CPU time 0.9 seconds
Started Jun 09 02:30:33 PM PDT 24
Finished Jun 09 02:30:34 PM PDT 24
Peak memory 205628 kb
Host smart-c7fbe884-4cd5-40e6-b1a5-68d6a53d877c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954410377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3954410377
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.790091367
Short name T441
Test name
Test status
Simulation time 6730293151 ps
CPU time 12.08 seconds
Started Jun 09 02:30:40 PM PDT 24
Finished Jun 09 02:30:52 PM PDT 24
Peak memory 232480 kb
Host smart-115b5082-cc50-44b2-b8d9-e76073ccca36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790091367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.790091367
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.731376467
Short name T657
Test name
Test status
Simulation time 10839632 ps
CPU time 0.76 seconds
Started Jun 09 02:30:28 PM PDT 24
Finished Jun 09 02:30:29 PM PDT 24
Peak memory 205556 kb
Host smart-2acd837a-c946-4f1b-a627-afb9a62af59d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731376467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.731376467
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.106836705
Short name T75
Test name
Test status
Simulation time 111460913 ps
CPU time 2.54 seconds
Started Jun 09 02:30:27 PM PDT 24
Finished Jun 09 02:30:30 PM PDT 24
Peak memory 224272 kb
Host smart-94b587b3-87cd-45d0-adaf-5ba2ee310a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106836705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.106836705
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.480078731
Short name T551
Test name
Test status
Simulation time 44210669 ps
CPU time 0.77 seconds
Started Jun 09 02:30:31 PM PDT 24
Finished Jun 09 02:30:33 PM PDT 24
Peak memory 206552 kb
Host smart-a733fa9d-417c-4a5f-a7df-5d9a72b7d7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480078731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.480078731
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1204088622
Short name T719
Test name
Test status
Simulation time 296022026 ps
CPU time 6.63 seconds
Started Jun 09 02:30:31 PM PDT 24
Finished Jun 09 02:30:38 PM PDT 24
Peak memory 224320 kb
Host smart-bbe84488-4e1a-421b-876c-c856172963a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204088622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1204088622
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1058962681
Short name T665
Test name
Test status
Simulation time 47640956176 ps
CPU time 192.27 seconds
Started Jun 09 02:30:36 PM PDT 24
Finished Jun 09 02:33:49 PM PDT 24
Peak memory 240872 kb
Host smart-03d5dc5f-8f91-4c96-b7aa-c6d6ce137f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058962681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1058962681
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3868331734
Short name T822
Test name
Test status
Simulation time 1340876499 ps
CPU time 15.34 seconds
Started Jun 09 02:30:44 PM PDT 24
Finished Jun 09 02:31:00 PM PDT 24
Peak memory 224304 kb
Host smart-ff2b8c1b-1ca3-4c74-b936-7983f5678ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868331734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3868331734
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2264765796
Short name T705
Test name
Test status
Simulation time 1911471616 ps
CPU time 25.62 seconds
Started Jun 09 02:30:29 PM PDT 24
Finished Jun 09 02:30:55 PM PDT 24
Peak memory 232532 kb
Host smart-a2837d6f-56ac-4cb6-8f73-bb2c958b5941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264765796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2264765796
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1704871616
Short name T487
Test name
Test status
Simulation time 8033396208 ps
CPU time 15.13 seconds
Started Jun 09 02:30:26 PM PDT 24
Finished Jun 09 02:30:42 PM PDT 24
Peak memory 224336 kb
Host smart-679a3cae-1777-49ca-a897-3bf3fea0aa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704871616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1704871616
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3162226389
Short name T952
Test name
Test status
Simulation time 392901603 ps
CPU time 7.14 seconds
Started Jun 09 02:30:26 PM PDT 24
Finished Jun 09 02:30:34 PM PDT 24
Peak memory 224304 kb
Host smart-98c57efe-534a-4c3d-a7bc-8dc44a5f8f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162226389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3162226389
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2765001511
Short name T967
Test name
Test status
Simulation time 116757243 ps
CPU time 2.42 seconds
Started Jun 09 02:30:22 PM PDT 24
Finished Jun 09 02:30:25 PM PDT 24
Peak memory 224256 kb
Host smart-9116ef7b-c385-46b7-8eb9-afdd68124aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765001511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2765001511
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2390946438
Short name T268
Test name
Test status
Simulation time 25729912220 ps
CPU time 20.21 seconds
Started Jun 09 02:30:43 PM PDT 24
Finished Jun 09 02:31:04 PM PDT 24
Peak memory 232604 kb
Host smart-5356adef-2539-41a3-9e32-7f8ced862995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390946438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2390946438
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2058319947
Short name T381
Test name
Test status
Simulation time 4214249779 ps
CPU time 5.69 seconds
Started Jun 09 02:30:40 PM PDT 24
Finished Jun 09 02:30:46 PM PDT 24
Peak memory 218860 kb
Host smart-5fb2e73f-9e98-43cc-a3ed-26f3af4a7cc6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2058319947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2058319947
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2076029950
Short name T359
Test name
Test status
Simulation time 39771901 ps
CPU time 0.96 seconds
Started Jun 09 02:30:38 PM PDT 24
Finished Jun 09 02:30:39 PM PDT 24
Peak memory 206540 kb
Host smart-a850e9a3-3011-4afa-bb76-9c16823c8866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076029950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2076029950
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.46800138
Short name T846
Test name
Test status
Simulation time 3149803368 ps
CPU time 28.84 seconds
Started Jun 09 02:30:28 PM PDT 24
Finished Jun 09 02:30:58 PM PDT 24
Peak memory 216180 kb
Host smart-2f3578cc-4d17-44f0-b3d4-7d1277fa5a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46800138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.46800138
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1039532870
Short name T961
Test name
Test status
Simulation time 396768316 ps
CPU time 1.62 seconds
Started Jun 09 02:30:22 PM PDT 24
Finished Jun 09 02:30:24 PM PDT 24
Peak memory 207684 kb
Host smart-d31809e0-ccac-4fff-aad0-f802130ae4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039532870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1039532870
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2317207796
Short name T927
Test name
Test status
Simulation time 76497017 ps
CPU time 1.48 seconds
Started Jun 09 02:30:28 PM PDT 24
Finished Jun 09 02:30:30 PM PDT 24
Peak memory 216092 kb
Host smart-3ef1dacd-9ec2-4777-b906-27ddac28c5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317207796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2317207796
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4195412866
Short name T315
Test name
Test status
Simulation time 23395107 ps
CPU time 0.72 seconds
Started Jun 09 02:30:25 PM PDT 24
Finished Jun 09 02:30:26 PM PDT 24
Peak memory 205580 kb
Host smart-6e9a83fa-133b-4d2a-b00e-936ee82b349c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195412866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4195412866
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.753934480
Short name T939
Test name
Test status
Simulation time 8812312328 ps
CPU time 9.04 seconds
Started Jun 09 02:30:32 PM PDT 24
Finished Jun 09 02:30:41 PM PDT 24
Peak memory 224384 kb
Host smart-a1518350-f41c-4519-be81-f3336610c145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753934480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.753934480
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.4097377842
Short name T372
Test name
Test status
Simulation time 15655152 ps
CPU time 0.71 seconds
Started Jun 09 02:30:40 PM PDT 24
Finished Jun 09 02:30:41 PM PDT 24
Peak memory 205148 kb
Host smart-89616106-27d4-4e0e-afba-c34c53a2ccfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097377842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
4097377842
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1724191175
Short name T627
Test name
Test status
Simulation time 256296086 ps
CPU time 5.41 seconds
Started Jun 09 02:30:36 PM PDT 24
Finished Jun 09 02:30:41 PM PDT 24
Peak memory 232560 kb
Host smart-f80ad448-de96-4011-b319-563ecaacc5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724191175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1724191175
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.4236076867
Short name T766
Test name
Test status
Simulation time 65652311 ps
CPU time 0.8 seconds
Started Jun 09 02:30:28 PM PDT 24
Finished Jun 09 02:30:29 PM PDT 24
Peak memory 206208 kb
Host smart-963fbc64-1aa8-41d4-9adc-4060bee1f0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236076867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4236076867
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.669905592
Short name T838
Test name
Test status
Simulation time 3622007950 ps
CPU time 65.61 seconds
Started Jun 09 02:30:27 PM PDT 24
Finished Jun 09 02:31:33 PM PDT 24
Peak memory 250432 kb
Host smart-6a576f5b-e2e5-4287-9e6c-b1399acdead3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669905592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.669905592
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2720146978
Short name T402
Test name
Test status
Simulation time 20666449735 ps
CPU time 29.71 seconds
Started Jun 09 02:30:41 PM PDT 24
Finished Jun 09 02:31:11 PM PDT 24
Peak memory 217420 kb
Host smart-b3f2ffae-8790-41d0-a15c-0d7255929f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720146978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2720146978
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1189113178
Short name T339
Test name
Test status
Simulation time 101468174745 ps
CPU time 267.91 seconds
Started Jun 09 02:30:39 PM PDT 24
Finished Jun 09 02:35:08 PM PDT 24
Peak memory 255732 kb
Host smart-826c42f9-8c5e-45d9-aea1-0243c8fecab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189113178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1189113178
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3624372211
Short name T438
Test name
Test status
Simulation time 262668063 ps
CPU time 6.29 seconds
Started Jun 09 02:30:37 PM PDT 24
Finished Jun 09 02:30:43 PM PDT 24
Peak memory 232452 kb
Host smart-f1ceed78-2f87-453c-b4bd-112021354575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624372211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3624372211
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.975810768
Short name T269
Test name
Test status
Simulation time 1050379439 ps
CPU time 4 seconds
Started Jun 09 02:30:26 PM PDT 24
Finished Jun 09 02:30:31 PM PDT 24
Peak memory 224284 kb
Host smart-fe01faa3-2acd-41bc-b22b-da54a689cb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975810768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.975810768
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.664872656
Short name T156
Test name
Test status
Simulation time 129477925 ps
CPU time 2.86 seconds
Started Jun 09 02:30:24 PM PDT 24
Finished Jun 09 02:30:27 PM PDT 24
Peak memory 224336 kb
Host smart-d02de9cd-e767-47e8-a636-f8ed10266daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664872656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.664872656
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1939350196
Short name T767
Test name
Test status
Simulation time 1372235819 ps
CPU time 6.26 seconds
Started Jun 09 02:30:42 PM PDT 24
Finished Jun 09 02:30:49 PM PDT 24
Peak memory 224232 kb
Host smart-1d5d985a-1828-4a45-90b9-c7c8b299ec74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939350196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1939350196
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3733800487
Short name T370
Test name
Test status
Simulation time 197093737 ps
CPU time 2.35 seconds
Started Jun 09 02:30:38 PM PDT 24
Finished Jun 09 02:30:41 PM PDT 24
Peak memory 232544 kb
Host smart-eec4d71b-e367-48a8-ad2f-2a4d54b6ba1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733800487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3733800487
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2351473187
Short name T582
Test name
Test status
Simulation time 6328996005 ps
CPU time 6.09 seconds
Started Jun 09 02:30:23 PM PDT 24
Finished Jun 09 02:30:29 PM PDT 24
Peak memory 222296 kb
Host smart-fa2e1b27-223b-4473-91f7-395a048b7171
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2351473187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2351473187
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1051699701
Short name T946
Test name
Test status
Simulation time 80001838 ps
CPU time 1.18 seconds
Started Jun 09 02:30:37 PM PDT 24
Finished Jun 09 02:30:39 PM PDT 24
Peak memory 206532 kb
Host smart-f5d7858f-1592-4c39-89a0-ade15f0a7d1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051699701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1051699701
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2497204362
Short name T723
Test name
Test status
Simulation time 12404808696 ps
CPU time 26.28 seconds
Started Jun 09 02:30:33 PM PDT 24
Finished Jun 09 02:30:59 PM PDT 24
Peak memory 216400 kb
Host smart-b784e3e5-86be-4250-8074-498d25b37b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497204362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2497204362
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3392025705
Short name T966
Test name
Test status
Simulation time 285296056 ps
CPU time 1.91 seconds
Started Jun 09 02:30:23 PM PDT 24
Finished Jun 09 02:30:25 PM PDT 24
Peak memory 216084 kb
Host smart-d07f2d95-1075-451b-b8eb-4620cce9371b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392025705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3392025705
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2102255038
Short name T584
Test name
Test status
Simulation time 26429992 ps
CPU time 0.75 seconds
Started Jun 09 02:30:40 PM PDT 24
Finished Jun 09 02:30:41 PM PDT 24
Peak memory 205620 kb
Host smart-679deabd-8fbe-4fe3-9e1e-b15574392efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102255038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2102255038
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3691339237
Short name T773
Test name
Test status
Simulation time 31807384 ps
CPU time 0.72 seconds
Started Jun 09 02:30:35 PM PDT 24
Finished Jun 09 02:30:36 PM PDT 24
Peak memory 205228 kb
Host smart-0b2d58ae-cb4b-47f0-815b-bbdde86806d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691339237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3691339237
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1515994664
Short name T772
Test name
Test status
Simulation time 119449854 ps
CPU time 2.24 seconds
Started Jun 09 02:30:41 PM PDT 24
Finished Jun 09 02:30:44 PM PDT 24
Peak memory 224288 kb
Host smart-d71c83f0-110e-4622-b9ec-5bce9625b978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515994664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1515994664
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3489182028
Short name T720
Test name
Test status
Simulation time 14999558 ps
CPU time 0.71 seconds
Started Jun 09 02:30:38 PM PDT 24
Finished Jun 09 02:30:39 PM PDT 24
Peak memory 204540 kb
Host smart-871322d2-167c-4173-b4b6-112457530d42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489182028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3489182028
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.664578009
Short name T594
Test name
Test status
Simulation time 3222040399 ps
CPU time 8.64 seconds
Started Jun 09 02:30:26 PM PDT 24
Finished Jun 09 02:30:35 PM PDT 24
Peak memory 224400 kb
Host smart-59144be6-a4ca-4eee-8748-442150fad549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664578009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.664578009
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1445641077
Short name T530
Test name
Test status
Simulation time 13009958 ps
CPU time 0.75 seconds
Started Jun 09 02:30:35 PM PDT 24
Finished Jun 09 02:30:37 PM PDT 24
Peak memory 205196 kb
Host smart-5fb9baae-15e5-442a-9c87-81fa45381b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445641077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1445641077
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1012640479
Short name T691
Test name
Test status
Simulation time 81206317791 ps
CPU time 148.77 seconds
Started Jun 09 02:30:39 PM PDT 24
Finished Jun 09 02:33:08 PM PDT 24
Peak memory 248960 kb
Host smart-79592120-5b79-4c8c-8d74-881d73f3a794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012640479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1012640479
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1419833530
Short name T43
Test name
Test status
Simulation time 25858833775 ps
CPU time 277.08 seconds
Started Jun 09 02:30:28 PM PDT 24
Finished Jun 09 02:35:05 PM PDT 24
Peak memory 269048 kb
Host smart-2609d079-7267-4f05-9a8c-9b254fdf827e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419833530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1419833530
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3185393162
Short name T8
Test name
Test status
Simulation time 16877679194 ps
CPU time 40.16 seconds
Started Jun 09 02:30:31 PM PDT 24
Finished Jun 09 02:31:12 PM PDT 24
Peak memory 239516 kb
Host smart-f6767930-4f91-4cb7-95bd-c6a7a945a8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185393162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3185393162
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.592640687
Short name T601
Test name
Test status
Simulation time 2455582306 ps
CPU time 39.12 seconds
Started Jun 09 02:30:45 PM PDT 24
Finished Jun 09 02:31:24 PM PDT 24
Peak memory 232572 kb
Host smart-f66848be-e5d8-4b2a-b1b7-fc4887c110b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592640687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.592640687
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.132344785
Short name T532
Test name
Test status
Simulation time 366309817 ps
CPU time 2.89 seconds
Started Jun 09 02:30:41 PM PDT 24
Finished Jun 09 02:30:44 PM PDT 24
Peak memory 224240 kb
Host smart-6737ac6c-8e6a-46a8-b142-a6d69012ce48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132344785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.132344785
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2269137496
Short name T442
Test name
Test status
Simulation time 4794669764 ps
CPU time 48.71 seconds
Started Jun 09 02:30:48 PM PDT 24
Finished Jun 09 02:31:37 PM PDT 24
Peak memory 248824 kb
Host smart-84c1c05f-3fa9-4acf-8eca-90e23b7a8847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269137496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2269137496
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3823677095
Short name T50
Test name
Test status
Simulation time 84091153 ps
CPU time 2.2 seconds
Started Jun 09 02:30:27 PM PDT 24
Finished Jun 09 02:30:30 PM PDT 24
Peak memory 232276 kb
Host smart-43b559d2-56a1-434d-a219-87527cda94a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823677095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3823677095
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1692848287
Short name T63
Test name
Test status
Simulation time 2009972585 ps
CPU time 7.28 seconds
Started Jun 09 02:30:43 PM PDT 24
Finished Jun 09 02:30:51 PM PDT 24
Peak memory 240424 kb
Host smart-a6a31aea-b4be-49dd-a13a-a1b93a148e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692848287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1692848287
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.78676228
Short name T117
Test name
Test status
Simulation time 805003835 ps
CPU time 4.55 seconds
Started Jun 09 02:30:37 PM PDT 24
Finished Jun 09 02:30:41 PM PDT 24
Peak memory 222688 kb
Host smart-fe98a71f-e021-4edb-a465-63b6149f3e11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=78676228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direc
t.78676228
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.337568687
Short name T592
Test name
Test status
Simulation time 5167870987 ps
CPU time 22.68 seconds
Started Jun 09 02:30:40 PM PDT 24
Finished Jun 09 02:31:03 PM PDT 24
Peak memory 216136 kb
Host smart-74189390-1815-4539-adef-17941bf9237e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337568687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.337568687
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1506623570
Short name T899
Test name
Test status
Simulation time 2512115790 ps
CPU time 10.03 seconds
Started Jun 09 02:30:45 PM PDT 24
Finished Jun 09 02:30:55 PM PDT 24
Peak memory 216048 kb
Host smart-56f468f9-32c0-47fe-81cc-17cbc6a4dc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506623570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1506623570
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2678821330
Short name T730
Test name
Test status
Simulation time 21004016 ps
CPU time 0.78 seconds
Started Jun 09 02:30:46 PM PDT 24
Finished Jun 09 02:30:47 PM PDT 24
Peak memory 205624 kb
Host smart-7e2c3cdd-b780-4d34-9571-cfef2944f768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678821330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2678821330
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.464012187
Short name T309
Test name
Test status
Simulation time 31544352 ps
CPU time 0.76 seconds
Started Jun 09 02:30:27 PM PDT 24
Finished Jun 09 02:30:28 PM PDT 24
Peak memory 205612 kb
Host smart-47d1cdaf-1013-45e8-9bfa-ead21c048a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464012187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.464012187
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3335778428
Short name T934
Test name
Test status
Simulation time 892323067 ps
CPU time 2.47 seconds
Started Jun 09 02:30:31 PM PDT 24
Finished Jun 09 02:30:34 PM PDT 24
Peak memory 232296 kb
Host smart-bf86daec-1783-4c7f-ad37-e05881eeb515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335778428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3335778428
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.918306136
Short name T843
Test name
Test status
Simulation time 41021525 ps
CPU time 0.71 seconds
Started Jun 09 02:30:33 PM PDT 24
Finished Jun 09 02:30:34 PM PDT 24
Peak memory 204524 kb
Host smart-095501ea-a80d-48ed-aa59-0c41595c5e8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918306136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.918306136
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.552925872
Short name T651
Test name
Test status
Simulation time 426306686 ps
CPU time 2.84 seconds
Started Jun 09 02:30:33 PM PDT 24
Finished Jun 09 02:30:36 PM PDT 24
Peak memory 224296 kb
Host smart-b91ba08f-b0ef-497f-8b98-d98dbb07a79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552925872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.552925872
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3193667981
Short name T351
Test name
Test status
Simulation time 100446292 ps
CPU time 0.78 seconds
Started Jun 09 02:30:35 PM PDT 24
Finished Jun 09 02:30:36 PM PDT 24
Peak memory 206224 kb
Host smart-f3789698-c28d-472e-81fe-c557cde6c556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193667981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3193667981
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.381231534
Short name T353
Test name
Test status
Simulation time 59914481 ps
CPU time 0.79 seconds
Started Jun 09 02:30:41 PM PDT 24
Finished Jun 09 02:30:43 PM PDT 24
Peak memory 215692 kb
Host smart-9da8d29a-d668-40f5-b840-0edf11253bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381231534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.381231534
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1927039759
Short name T225
Test name
Test status
Simulation time 73437799764 ps
CPU time 161.6 seconds
Started Jun 09 02:30:28 PM PDT 24
Finished Jun 09 02:33:10 PM PDT 24
Peak memory 273256 kb
Host smart-89625ac2-110c-4aef-8cee-99f776c25660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927039759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1927039759
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.218772273
Short name T394
Test name
Test status
Simulation time 128937704 ps
CPU time 2.52 seconds
Started Jun 09 02:30:43 PM PDT 24
Finished Jun 09 02:30:46 PM PDT 24
Peak memory 224320 kb
Host smart-1a86e53e-c734-4d1f-9923-49a7c6eb40f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218772273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.218772273
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2895459422
Short name T908
Test name
Test status
Simulation time 2415146795 ps
CPU time 6.39 seconds
Started Jun 09 02:30:37 PM PDT 24
Finished Jun 09 02:30:44 PM PDT 24
Peak memory 232552 kb
Host smart-26143ab0-812a-41b5-9fd0-0c18398ff7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895459422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2895459422
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2039851008
Short name T199
Test name
Test status
Simulation time 2511097821 ps
CPU time 18.68 seconds
Started Jun 09 02:30:44 PM PDT 24
Finished Jun 09 02:31:03 PM PDT 24
Peak memory 232592 kb
Host smart-4dca3de4-af52-46d5-ba91-f8c75463dad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039851008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2039851008
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.160977457
Short name T453
Test name
Test status
Simulation time 1668426505 ps
CPU time 10.5 seconds
Started Jun 09 02:30:47 PM PDT 24
Finished Jun 09 02:30:58 PM PDT 24
Peak memory 240532 kb
Host smart-a7d04fb5-dffc-4470-afa4-441980ddd7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160977457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.160977457
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2462173700
Short name T419
Test name
Test status
Simulation time 354138375 ps
CPU time 2.06 seconds
Started Jun 09 02:30:46 PM PDT 24
Finished Jun 09 02:30:49 PM PDT 24
Peak memory 222756 kb
Host smart-6e48ecc3-d086-434e-8ca7-a9fe837a55f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462173700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2462173700
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4254073021
Short name T645
Test name
Test status
Simulation time 4839960868 ps
CPU time 13.71 seconds
Started Jun 09 02:30:46 PM PDT 24
Finished Jun 09 02:31:01 PM PDT 24
Peak memory 219784 kb
Host smart-cd0e0cae-db65-4c7b-9db0-7a9801c7256a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4254073021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4254073021
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2144931321
Short name T798
Test name
Test status
Simulation time 1077018324 ps
CPU time 9.04 seconds
Started Jun 09 02:30:43 PM PDT 24
Finished Jun 09 02:30:53 PM PDT 24
Peak memory 216116 kb
Host smart-eacd90e3-e5e9-416f-b9c8-da253e9c261d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144931321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2144931321
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2116042727
Short name T119
Test name
Test status
Simulation time 22748824 ps
CPU time 0.75 seconds
Started Jun 09 02:30:41 PM PDT 24
Finished Jun 09 02:30:42 PM PDT 24
Peak memory 205292 kb
Host smart-441d9951-a83b-4b6f-91a6-1c7b5f7b0670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116042727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2116042727
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3829878050
Short name T529
Test name
Test status
Simulation time 40363700 ps
CPU time 0.95 seconds
Started Jun 09 02:30:38 PM PDT 24
Finished Jun 09 02:30:40 PM PDT 24
Peak memory 206680 kb
Host smart-ee29a89c-d86f-40f6-993f-c8bd038124e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829878050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3829878050
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.759292423
Short name T396
Test name
Test status
Simulation time 117137747 ps
CPU time 0.81 seconds
Started Jun 09 02:30:32 PM PDT 24
Finished Jun 09 02:30:33 PM PDT 24
Peak memory 205608 kb
Host smart-454ce4bd-4c7c-4768-9b0a-3cf2c36252e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759292423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.759292423
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.493092586
Short name T815
Test name
Test status
Simulation time 227869101 ps
CPU time 4.67 seconds
Started Jun 09 02:30:44 PM PDT 24
Finished Jun 09 02:30:49 PM PDT 24
Peak memory 232516 kb
Host smart-e8c6adb5-8560-4203-a770-5a11aab46d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493092586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.493092586
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1888152474
Short name T679
Test name
Test status
Simulation time 11371102 ps
CPU time 0.74 seconds
Started Jun 09 02:30:42 PM PDT 24
Finished Jun 09 02:30:43 PM PDT 24
Peak memory 204716 kb
Host smart-b726d6cb-3dc3-4021-801b-26ba2b05dc34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888152474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1888152474
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1547951398
Short name T197
Test name
Test status
Simulation time 255577808 ps
CPU time 3.74 seconds
Started Jun 09 02:30:50 PM PDT 24
Finished Jun 09 02:30:55 PM PDT 24
Peak memory 232516 kb
Host smart-1dce8f4b-4ba0-43ec-a1da-8539b24c34f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547951398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1547951398
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1088959486
Short name T506
Test name
Test status
Simulation time 22838391 ps
CPU time 0.73 seconds
Started Jun 09 02:30:38 PM PDT 24
Finished Jun 09 02:30:39 PM PDT 24
Peak memory 205188 kb
Host smart-633c83ad-8844-4757-a4e9-6558d47d2102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088959486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1088959486
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3658495884
Short name T610
Test name
Test status
Simulation time 34298423179 ps
CPU time 51.5 seconds
Started Jun 09 02:30:32 PM PDT 24
Finished Jun 09 02:31:24 PM PDT 24
Peak memory 240352 kb
Host smart-c66a4f14-660a-471b-9f59-cb184d830ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658495884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3658495884
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3004224039
Short name T889
Test name
Test status
Simulation time 38447776095 ps
CPU time 41.02 seconds
Started Jun 09 02:30:45 PM PDT 24
Finished Jun 09 02:31:27 PM PDT 24
Peak memory 237112 kb
Host smart-4fcf2d77-3845-4c6a-ba7c-f7e0e945a0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004224039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3004224039
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2779913549
Short name T120
Test name
Test status
Simulation time 10583681545 ps
CPU time 65.91 seconds
Started Jun 09 02:30:42 PM PDT 24
Finished Jun 09 02:31:49 PM PDT 24
Peak memory 248912 kb
Host smart-95d81e4e-e3b6-45d1-a5b9-172e8cc76f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779913549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2779913549
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2892804711
Short name T544
Test name
Test status
Simulation time 29632653620 ps
CPU time 36.06 seconds
Started Jun 09 02:30:38 PM PDT 24
Finished Jun 09 02:31:15 PM PDT 24
Peak memory 249000 kb
Host smart-94488dd5-84d2-4eb9-a855-848a3e76d8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892804711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2892804711
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3896681153
Short name T681
Test name
Test status
Simulation time 643983037 ps
CPU time 3.33 seconds
Started Jun 09 02:30:45 PM PDT 24
Finished Jun 09 02:30:49 PM PDT 24
Peak memory 224256 kb
Host smart-3af146de-bec7-488d-b9fe-610772cb81b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896681153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3896681153
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1816614258
Short name T374
Test name
Test status
Simulation time 375139286 ps
CPU time 3.2 seconds
Started Jun 09 02:30:51 PM PDT 24
Finished Jun 09 02:30:55 PM PDT 24
Peak memory 224216 kb
Host smart-6d6ea72a-bdf9-4591-b068-ff0ee73746de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816614258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1816614258
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3040690867
Short name T178
Test name
Test status
Simulation time 10184537404 ps
CPU time 15.59 seconds
Started Jun 09 02:30:43 PM PDT 24
Finished Jun 09 02:30:59 PM PDT 24
Peak memory 224356 kb
Host smart-f7a6779b-5907-47c0-a6fb-ffaf51e4e29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040690867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3040690867
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.378939540
Short name T969
Test name
Test status
Simulation time 8593914924 ps
CPU time 13.21 seconds
Started Jun 09 02:30:47 PM PDT 24
Finished Jun 09 02:31:01 PM PDT 24
Peak memory 224324 kb
Host smart-ae132adb-8616-4a52-a324-e78390397f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378939540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.378939540
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1609594837
Short name T561
Test name
Test status
Simulation time 870252458 ps
CPU time 6.74 seconds
Started Jun 09 02:30:37 PM PDT 24
Finished Jun 09 02:30:44 PM PDT 24
Peak memory 219836 kb
Host smart-eda8414c-10a9-45c0-b80a-009472bd3d17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1609594837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1609594837
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1334042180
Short name T146
Test name
Test status
Simulation time 51374224 ps
CPU time 0.88 seconds
Started Jun 09 02:30:45 PM PDT 24
Finished Jun 09 02:30:46 PM PDT 24
Peak memory 206236 kb
Host smart-02954255-5ccb-4be9-ace9-2cddc7001636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334042180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1334042180
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1616465681
Short name T694
Test name
Test status
Simulation time 2067258129 ps
CPU time 11.09 seconds
Started Jun 09 02:30:42 PM PDT 24
Finished Jun 09 02:30:54 PM PDT 24
Peak memory 216020 kb
Host smart-cad541c7-0acc-4bca-a23a-181d1d411dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616465681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1616465681
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2647846399
Short name T777
Test name
Test status
Simulation time 455167801 ps
CPU time 3.57 seconds
Started Jun 09 02:30:35 PM PDT 24
Finished Jun 09 02:30:38 PM PDT 24
Peak memory 216044 kb
Host smart-a7e7ba09-ebb7-4337-812d-a9debe16dc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647846399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2647846399
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1100171644
Short name T457
Test name
Test status
Simulation time 240274451 ps
CPU time 4.74 seconds
Started Jun 09 02:30:51 PM PDT 24
Finished Jun 09 02:30:57 PM PDT 24
Peak memory 216056 kb
Host smart-72bf1ebb-a8fc-427f-94c8-100f531d424b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100171644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1100171644
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.504861300
Short name T768
Test name
Test status
Simulation time 1461121420 ps
CPU time 1.02 seconds
Started Jun 09 02:30:32 PM PDT 24
Finished Jun 09 02:30:34 PM PDT 24
Peak memory 206628 kb
Host smart-5552b063-5c49-4a12-b9cd-fc0e4059f60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504861300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.504861300
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3009832455
Short name T184
Test name
Test status
Simulation time 336566415 ps
CPU time 5.43 seconds
Started Jun 09 02:30:37 PM PDT 24
Finished Jun 09 02:30:43 PM PDT 24
Peak memory 232512 kb
Host smart-28ee77c2-652c-4b49-ba73-25af02085f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009832455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3009832455
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1668631341
Short name T470
Test name
Test status
Simulation time 17051041 ps
CPU time 0.73 seconds
Started Jun 09 02:29:07 PM PDT 24
Finished Jun 09 02:29:09 PM PDT 24
Peak memory 204516 kb
Host smart-dd9bafe9-4556-4e62-9ff8-711ed2e735e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668631341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
668631341
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3790348577
Short name T482
Test name
Test status
Simulation time 447552118 ps
CPU time 3.27 seconds
Started Jun 09 02:29:08 PM PDT 24
Finished Jun 09 02:29:12 PM PDT 24
Peak memory 232556 kb
Host smart-8932b8ab-535a-4051-a481-c1f2d53b053e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790348577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3790348577
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3047315368
Short name T829
Test name
Test status
Simulation time 20434003 ps
CPU time 0.76 seconds
Started Jun 09 02:29:15 PM PDT 24
Finished Jun 09 02:29:16 PM PDT 24
Peak memory 205192 kb
Host smart-2d9ed881-534b-4e70-b40e-aee5c559ed7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047315368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3047315368
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3605630778
Short name T845
Test name
Test status
Simulation time 74220625 ps
CPU time 0.78 seconds
Started Jun 09 02:29:04 PM PDT 24
Finished Jun 09 02:29:10 PM PDT 24
Peak memory 215704 kb
Host smart-2b740113-4c5b-4ab3-9f48-8d6e6ff60637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605630778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3605630778
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3382609355
Short name T765
Test name
Test status
Simulation time 223185855719 ps
CPU time 352.11 seconds
Started Jun 09 02:29:09 PM PDT 24
Finished Jun 09 02:35:01 PM PDT 24
Peak memory 236672 kb
Host smart-79f2c475-5a93-4668-bd86-195afeb36a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382609355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3382609355
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1384661932
Short name T718
Test name
Test status
Simulation time 7970684345 ps
CPU time 57.81 seconds
Started Jun 09 02:29:10 PM PDT 24
Finished Jun 09 02:30:08 PM PDT 24
Peak memory 249020 kb
Host smart-a9e3b1fc-9eeb-4a8e-b1cf-100f1906b7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384661932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1384661932
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1852131505
Short name T753
Test name
Test status
Simulation time 425336141 ps
CPU time 7.87 seconds
Started Jun 09 02:29:04 PM PDT 24
Finished Jun 09 02:29:12 PM PDT 24
Peak memory 236644 kb
Host smart-42bb9387-6af8-4275-a7e6-4966d6a8c1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852131505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1852131505
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3013045503
Short name T260
Test name
Test status
Simulation time 1319793087 ps
CPU time 12.54 seconds
Started Jun 09 02:29:11 PM PDT 24
Finished Jun 09 02:29:29 PM PDT 24
Peak memory 224248 kb
Host smart-5930b733-efd4-4d9e-80ad-10e38f4bbb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013045503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3013045503
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.796568541
Short name T833
Test name
Test status
Simulation time 4942641211 ps
CPU time 64.76 seconds
Started Jun 09 02:29:00 PM PDT 24
Finished Jun 09 02:30:06 PM PDT 24
Peak memory 232560 kb
Host smart-fd3d5734-02bf-40e9-88a9-c3764833788b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796568541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.796568541
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3918225529
Short name T24
Test name
Test status
Simulation time 94192533 ps
CPU time 1.04 seconds
Started Jun 09 02:29:02 PM PDT 24
Finished Jun 09 02:29:03 PM PDT 24
Peak memory 217616 kb
Host smart-a12dff44-a5e6-4318-a7f5-e8f5464ee9a0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918225529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3918225529
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2592216738
Short name T955
Test name
Test status
Simulation time 10775646444 ps
CPU time 8.82 seconds
Started Jun 09 02:29:08 PM PDT 24
Finished Jun 09 02:29:17 PM PDT 24
Peak memory 232532 kb
Host smart-03674e8c-236a-4ab2-b052-49b5a8001610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592216738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2592216738
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2187451634
Short name T345
Test name
Test status
Simulation time 55226874237 ps
CPU time 30.76 seconds
Started Jun 09 02:28:59 PM PDT 24
Finished Jun 09 02:29:30 PM PDT 24
Peak memory 232592 kb
Host smart-6223a6fa-8b84-4c3a-b014-f2235ac0a639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187451634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2187451634
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.630624796
Short name T406
Test name
Test status
Simulation time 101247957 ps
CPU time 3.61 seconds
Started Jun 09 02:29:30 PM PDT 24
Finished Jun 09 02:29:34 PM PDT 24
Peak memory 220116 kb
Host smart-718f81ba-5314-4397-afc8-1ec5938eb300
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=630624796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.630624796
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3781917849
Short name T56
Test name
Test status
Simulation time 59478903 ps
CPU time 1.02 seconds
Started Jun 09 02:29:12 PM PDT 24
Finished Jun 09 02:29:13 PM PDT 24
Peak memory 234920 kb
Host smart-ed2e145c-be45-4fed-aea2-94b41d4764ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781917849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3781917849
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.11086240
Short name T796
Test name
Test status
Simulation time 1636099963 ps
CPU time 26.27 seconds
Started Jun 09 02:29:03 PM PDT 24
Finished Jun 09 02:29:30 PM PDT 24
Peak memory 227360 kb
Host smart-406e03cd-b72d-4214-afb2-939c8587b0dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11086240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_
all.11086240
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1794236966
Short name T331
Test name
Test status
Simulation time 41866011554 ps
CPU time 48.38 seconds
Started Jun 09 02:29:06 PM PDT 24
Finished Jun 09 02:29:54 PM PDT 24
Peak memory 216164 kb
Host smart-c4b06daa-5fce-4bdc-9609-46f4cf075dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794236966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1794236966
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.634656925
Short name T866
Test name
Test status
Simulation time 1062026907 ps
CPU time 3.07 seconds
Started Jun 09 02:28:58 PM PDT 24
Finished Jun 09 02:29:01 PM PDT 24
Peak memory 216092 kb
Host smart-82af17a9-89a0-4011-8a10-e6c2b2de93eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634656925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.634656925
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1715537657
Short name T314
Test name
Test status
Simulation time 66711062 ps
CPU time 1.54 seconds
Started Jun 09 02:29:01 PM PDT 24
Finished Jun 09 02:29:03 PM PDT 24
Peak memory 207800 kb
Host smart-b1e97a8e-548d-4ee6-b73f-110be5f51793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715537657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1715537657
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1689625704
Short name T896
Test name
Test status
Simulation time 348689891 ps
CPU time 0.93 seconds
Started Jun 09 02:29:08 PM PDT 24
Finished Jun 09 02:29:14 PM PDT 24
Peak memory 205608 kb
Host smart-5c699d67-980c-441b-bc52-99a8f58da69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689625704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1689625704
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2205338526
Short name T480
Test name
Test status
Simulation time 17361757448 ps
CPU time 12.56 seconds
Started Jun 09 02:29:07 PM PDT 24
Finished Jun 09 02:29:20 PM PDT 24
Peak memory 232580 kb
Host smart-e2645ad6-3408-4fe6-b00f-4096f3e18708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205338526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2205338526
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2655669723
Short name T947
Test name
Test status
Simulation time 91512725 ps
CPU time 0.71 seconds
Started Jun 09 02:30:34 PM PDT 24
Finished Jun 09 02:30:35 PM PDT 24
Peak memory 205180 kb
Host smart-ee2c6c17-176d-4b0a-9fd5-6f14f11adb43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655669723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2655669723
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.643914106
Short name T809
Test name
Test status
Simulation time 2535083878 ps
CPU time 7.41 seconds
Started Jun 09 02:30:48 PM PDT 24
Finished Jun 09 02:30:56 PM PDT 24
Peak memory 232620 kb
Host smart-92eaeed3-31a4-494a-b9d5-58bc2231470d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643914106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.643914106
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4138380085
Short name T735
Test name
Test status
Simulation time 16584402 ps
CPU time 0.8 seconds
Started Jun 09 02:30:48 PM PDT 24
Finished Jun 09 02:30:49 PM PDT 24
Peak memory 205168 kb
Host smart-c70aa661-5f2c-4812-80e0-3c40ab92a4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138380085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4138380085
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.945781039
Short name T371
Test name
Test status
Simulation time 17097623 ps
CPU time 0.76 seconds
Started Jun 09 02:30:37 PM PDT 24
Finished Jun 09 02:30:38 PM PDT 24
Peak memory 215700 kb
Host smart-adfd9a91-edb2-41bc-968f-201d4919849c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945781039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.945781039
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3939838614
Short name T389
Test name
Test status
Simulation time 503322614093 ps
CPU time 237.78 seconds
Started Jun 09 02:30:34 PM PDT 24
Finished Jun 09 02:34:32 PM PDT 24
Peak memory 254024 kb
Host smart-3d966706-f5d5-482c-96e9-2c22b2f09f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939838614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3939838614
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4098402018
Short name T130
Test name
Test status
Simulation time 2526151770 ps
CPU time 10.62 seconds
Started Jun 09 02:30:41 PM PDT 24
Finished Jun 09 02:30:52 PM PDT 24
Peak memory 240776 kb
Host smart-1881374e-edc7-4082-aa7d-1d940dc8e75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098402018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4098402018
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.9758555
Short name T534
Test name
Test status
Simulation time 5337303193 ps
CPU time 16.35 seconds
Started Jun 09 02:30:50 PM PDT 24
Finished Jun 09 02:31:08 PM PDT 24
Peak memory 224384 kb
Host smart-e9688c3a-cbdb-4a01-bb2a-41ec84e02e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9758555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.9758555
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3594764565
Short name T853
Test name
Test status
Simulation time 652795287 ps
CPU time 10.6 seconds
Started Jun 09 02:30:42 PM PDT 24
Finished Jun 09 02:30:53 PM PDT 24
Peak memory 232488 kb
Host smart-c9ca6ff5-3483-481b-8f22-05a2bce98b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594764565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3594764565
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1691244306
Short name T844
Test name
Test status
Simulation time 339071500 ps
CPU time 5.89 seconds
Started Jun 09 02:30:46 PM PDT 24
Finished Jun 09 02:30:52 PM PDT 24
Peak memory 224264 kb
Host smart-bcc460a4-e619-4310-92d4-760dbf50df9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691244306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1691244306
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.69840966
Short name T933
Test name
Test status
Simulation time 5566109094 ps
CPU time 10.41 seconds
Started Jun 09 02:30:47 PM PDT 24
Finished Jun 09 02:30:58 PM PDT 24
Peak memory 224408 kb
Host smart-5d734488-483c-4f2e-96a7-25458800b516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69840966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.69840966
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3382798970
Short name T684
Test name
Test status
Simulation time 179009437 ps
CPU time 3.73 seconds
Started Jun 09 02:30:47 PM PDT 24
Finished Jun 09 02:30:51 PM PDT 24
Peak memory 219884 kb
Host smart-5bfdcc5f-3e21-4ea6-9af3-15419b2e4485
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3382798970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3382798970
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3117040749
Short name T762
Test name
Test status
Simulation time 8891529488 ps
CPU time 15.11 seconds
Started Jun 09 02:30:43 PM PDT 24
Finished Jun 09 02:30:58 PM PDT 24
Peak memory 216364 kb
Host smart-faa2b77f-af17-4a8d-9138-a1cfbeeb11f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117040749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3117040749
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.247762268
Short name T856
Test name
Test status
Simulation time 848415048 ps
CPU time 2.91 seconds
Started Jun 09 02:30:33 PM PDT 24
Finished Jun 09 02:30:36 PM PDT 24
Peak memory 215876 kb
Host smart-c1239468-e8d0-4754-a950-1d6c211383e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247762268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.247762268
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1522616613
Short name T726
Test name
Test status
Simulation time 23274590 ps
CPU time 1.2 seconds
Started Jun 09 02:30:33 PM PDT 24
Finished Jun 09 02:30:34 PM PDT 24
Peak memory 216188 kb
Host smart-6c604f20-00b4-42ea-bd6d-db1f8a5bff94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522616613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1522616613
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1581842489
Short name T358
Test name
Test status
Simulation time 119646348 ps
CPU time 0.78 seconds
Started Jun 09 02:30:34 PM PDT 24
Finished Jun 09 02:30:36 PM PDT 24
Peak memory 205600 kb
Host smart-16b0497f-ea2e-42a9-95e9-c1894a764cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581842489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1581842489
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2396599915
Short name T385
Test name
Test status
Simulation time 563038307 ps
CPU time 7.57 seconds
Started Jun 09 02:30:44 PM PDT 24
Finished Jun 09 02:30:52 PM PDT 24
Peak memory 224312 kb
Host smart-8c3918c8-f32f-4f78-9d51-572dcf57bae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396599915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2396599915
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4012235882
Short name T880
Test name
Test status
Simulation time 25957454 ps
CPU time 0.68 seconds
Started Jun 09 02:30:47 PM PDT 24
Finished Jun 09 02:30:48 PM PDT 24
Peak memory 205156 kb
Host smart-d0c38925-914b-496f-a3dd-e5eb61cf786a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012235882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4012235882
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.890350999
Short name T938
Test name
Test status
Simulation time 854191687 ps
CPU time 4.38 seconds
Started Jun 09 02:30:46 PM PDT 24
Finished Jun 09 02:30:50 PM PDT 24
Peak memory 224324 kb
Host smart-b32902a3-df9b-4fb1-891f-d105b51abe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890350999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.890350999
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3237708288
Short name T306
Test name
Test status
Simulation time 176416429 ps
CPU time 0.81 seconds
Started Jun 09 02:30:45 PM PDT 24
Finished Jun 09 02:30:46 PM PDT 24
Peak memory 206556 kb
Host smart-6760685f-731a-4179-99ef-fb25ab11fdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237708288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3237708288
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1853572156
Short name T154
Test name
Test status
Simulation time 2292154935 ps
CPU time 46.31 seconds
Started Jun 09 02:30:45 PM PDT 24
Finished Jun 09 02:31:31 PM PDT 24
Peak memory 250684 kb
Host smart-48ebddcc-ad03-4e53-8ebf-1a45ac8aea25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853572156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1853572156
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1360690500
Short name T124
Test name
Test status
Simulation time 12247119861 ps
CPU time 44.73 seconds
Started Jun 09 02:30:44 PM PDT 24
Finished Jun 09 02:31:30 PM PDT 24
Peak memory 251504 kb
Host smart-401a3807-7818-4ce4-a053-fe0e54038bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360690500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1360690500
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1316434703
Short name T440
Test name
Test status
Simulation time 26441998917 ps
CPU time 32.19 seconds
Started Jun 09 02:30:47 PM PDT 24
Finished Jun 09 02:31:19 PM PDT 24
Peak memory 224452 kb
Host smart-43d76732-4343-4c1c-a461-af73010053ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316434703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1316434703
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3068553366
Short name T894
Test name
Test status
Simulation time 187649401 ps
CPU time 4.7 seconds
Started Jun 09 02:30:55 PM PDT 24
Finished Jun 09 02:31:01 PM PDT 24
Peak memory 234468 kb
Host smart-a1caf410-d56f-4ccf-b400-5eca9eef568c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068553366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3068553366
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4006454744
Short name T831
Test name
Test status
Simulation time 160954564 ps
CPU time 4.15 seconds
Started Jun 09 02:30:49 PM PDT 24
Finished Jun 09 02:30:54 PM PDT 24
Peak memory 224268 kb
Host smart-e740e83a-db1c-4e1a-b820-9cfe696d5f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006454744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4006454744
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2233531183
Short name T944
Test name
Test status
Simulation time 1225523086 ps
CPU time 8.09 seconds
Started Jun 09 02:30:43 PM PDT 24
Finished Jun 09 02:30:51 PM PDT 24
Peak memory 224276 kb
Host smart-2fc8ce3b-4703-4c12-a912-db9649d3cc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233531183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2233531183
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.796625252
Short name T804
Test name
Test status
Simulation time 534497635 ps
CPU time 7.36 seconds
Started Jun 09 02:30:35 PM PDT 24
Finished Jun 09 02:30:42 PM PDT 24
Peak memory 232512 kb
Host smart-779d025c-71e2-4981-b59e-a89a0e3b255b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796625252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.796625252
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2457864254
Short name T258
Test name
Test status
Simulation time 1275533509 ps
CPU time 6.76 seconds
Started Jun 09 02:30:50 PM PDT 24
Finished Jun 09 02:30:58 PM PDT 24
Peak memory 224360 kb
Host smart-576bc598-6c8e-4bdf-94b8-f0be78ccd3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457864254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2457864254
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3639605367
Short name T911
Test name
Test status
Simulation time 239211452 ps
CPU time 3.43 seconds
Started Jun 09 02:30:40 PM PDT 24
Finished Jun 09 02:30:43 PM PDT 24
Peak memory 219912 kb
Host smart-7abcbcd2-268e-4e28-80cc-61d09967529b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3639605367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3639605367
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.140402383
Short name T217
Test name
Test status
Simulation time 13599116087 ps
CPU time 200.35 seconds
Started Jun 09 02:30:50 PM PDT 24
Finished Jun 09 02:34:11 PM PDT 24
Peak memory 272224 kb
Host smart-6aa277b0-b188-4af4-85a2-e3d23c1ad169
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140402383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.140402383
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.733010219
Short name T774
Test name
Test status
Simulation time 33862485 ps
CPU time 0.77 seconds
Started Jun 09 02:30:45 PM PDT 24
Finished Jun 09 02:30:46 PM PDT 24
Peak memory 205356 kb
Host smart-755489f8-ef67-44bd-b151-8d3e1a6a0db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733010219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.733010219
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1939787162
Short name T900
Test name
Test status
Simulation time 1088256011 ps
CPU time 3.84 seconds
Started Jun 09 02:30:34 PM PDT 24
Finished Jun 09 02:30:38 PM PDT 24
Peak memory 215848 kb
Host smart-eed76319-d9b0-46ac-b55e-716a03aedc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939787162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1939787162
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3995773672
Short name T400
Test name
Test status
Simulation time 263836404 ps
CPU time 2.72 seconds
Started Jun 09 02:30:38 PM PDT 24
Finished Jun 09 02:30:41 PM PDT 24
Peak memory 216024 kb
Host smart-e7fc54c8-4775-4625-9958-493ec3104f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995773672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3995773672
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.117219198
Short name T828
Test name
Test status
Simulation time 83761783 ps
CPU time 0.95 seconds
Started Jun 09 02:30:34 PM PDT 24
Finished Jun 09 02:30:36 PM PDT 24
Peak memory 205588 kb
Host smart-04f2a664-ff9d-4ec9-b6f8-d0d91eb87b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117219198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.117219198
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3031746228
Short name T169
Test name
Test status
Simulation time 117142800 ps
CPU time 2.81 seconds
Started Jun 09 02:30:50 PM PDT 24
Finished Jun 09 02:30:54 PM PDT 24
Peak memory 232528 kb
Host smart-77ea1d19-97e5-4f37-9d13-2fb1ac54660b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031746228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3031746228
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.411566459
Short name T363
Test name
Test status
Simulation time 33941594 ps
CPU time 0.69 seconds
Started Jun 09 02:30:50 PM PDT 24
Finished Jun 09 02:30:51 PM PDT 24
Peak memory 204504 kb
Host smart-e8d9a00b-77c6-44bf-86bf-9a5a7febc609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411566459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.411566459
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.121126042
Short name T252
Test name
Test status
Simulation time 174680982 ps
CPU time 3.85 seconds
Started Jun 09 02:30:50 PM PDT 24
Finished Jun 09 02:30:55 PM PDT 24
Peak memory 224312 kb
Host smart-8e2d0107-71fe-4cb1-967b-cadca582ed5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121126042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.121126042
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2924584086
Short name T365
Test name
Test status
Simulation time 35256321 ps
CPU time 0.74 seconds
Started Jun 09 02:30:35 PM PDT 24
Finished Jun 09 02:30:36 PM PDT 24
Peak memory 206560 kb
Host smart-9e332eb5-9783-4fa4-9eb7-434edc757512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924584086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2924584086
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.843721177
Short name T495
Test name
Test status
Simulation time 83452031412 ps
CPU time 284.37 seconds
Started Jun 09 02:30:54 PM PDT 24
Finished Jun 09 02:35:39 PM PDT 24
Peak memory 256860 kb
Host smart-0b9f4f0a-4d70-47f4-998d-491cfc26f00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843721177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.843721177
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2621839984
Short name T586
Test name
Test status
Simulation time 56958633543 ps
CPU time 236.6 seconds
Started Jun 09 02:30:44 PM PDT 24
Finished Jun 09 02:34:41 PM PDT 24
Peak memory 249072 kb
Host smart-c4b21bd7-5d1c-483a-83f7-642ff91a4789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621839984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2621839984
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4280144850
Short name T159
Test name
Test status
Simulation time 1075528701 ps
CPU time 4.48 seconds
Started Jun 09 02:30:40 PM PDT 24
Finished Jun 09 02:30:45 PM PDT 24
Peak memory 224272 kb
Host smart-f7942d64-4dec-4c80-bc03-2fb8c7e241e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280144850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4280144850
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3722060102
Short name T278
Test name
Test status
Simulation time 245277828 ps
CPU time 5.6 seconds
Started Jun 09 02:30:51 PM PDT 24
Finished Jun 09 02:30:58 PM PDT 24
Peak memory 224484 kb
Host smart-4536ad1d-fac7-4468-97b1-d65bab2073ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722060102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3722060102
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.199663738
Short name T29
Test name
Test status
Simulation time 1484426844 ps
CPU time 8.24 seconds
Started Jun 09 02:30:45 PM PDT 24
Finished Jun 09 02:30:53 PM PDT 24
Peak memory 240712 kb
Host smart-0a59bd55-1cfe-4907-a444-0b30be646ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199663738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.199663738
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.39026452
Short name T542
Test name
Test status
Simulation time 456052662 ps
CPU time 3.55 seconds
Started Jun 09 02:30:44 PM PDT 24
Finished Jun 09 02:30:48 PM PDT 24
Peak memory 224472 kb
Host smart-c63842bf-34fc-4109-9f84-dddcf0d37990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39026452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.39026452
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1543720378
Short name T405
Test name
Test status
Simulation time 936929243 ps
CPU time 4.58 seconds
Started Jun 09 02:30:48 PM PDT 24
Finished Jun 09 02:30:53 PM PDT 24
Peak memory 219152 kb
Host smart-a0d8c54d-f93b-45b5-8509-77101ae73a53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1543720378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1543720378
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.868779667
Short name T18
Test name
Test status
Simulation time 9919614092 ps
CPU time 65.52 seconds
Started Jun 09 02:30:53 PM PDT 24
Finished Jun 09 02:31:59 PM PDT 24
Peak memory 255216 kb
Host smart-0c43eacb-4e8f-4451-a401-4d3040ff35f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868779667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.868779667
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1945515190
Short name T45
Test name
Test status
Simulation time 1323867061 ps
CPU time 15.94 seconds
Started Jun 09 02:30:45 PM PDT 24
Finished Jun 09 02:31:01 PM PDT 24
Peak memory 216288 kb
Host smart-ca8d81aa-21eb-4719-ab70-04a48b837902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945515190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1945515190
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3200994054
Short name T658
Test name
Test status
Simulation time 57395648 ps
CPU time 1.11 seconds
Started Jun 09 02:30:50 PM PDT 24
Finished Jun 09 02:30:52 PM PDT 24
Peak memory 205780 kb
Host smart-09b90a40-7251-485c-a5a1-358a4676af30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200994054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3200994054
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2702311973
Short name T906
Test name
Test status
Simulation time 30177876 ps
CPU time 0.67 seconds
Started Jun 09 02:30:37 PM PDT 24
Finished Jun 09 02:30:38 PM PDT 24
Peak memory 205256 kb
Host smart-7a6ec79f-c753-4555-af4b-a7485013926c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702311973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2702311973
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.441654983
Short name T378
Test name
Test status
Simulation time 92145754 ps
CPU time 0.78 seconds
Started Jun 09 02:30:44 PM PDT 24
Finished Jun 09 02:30:45 PM PDT 24
Peak memory 205612 kb
Host smart-0ac47fde-1110-402e-8690-3e0b31d5e14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441654983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.441654983
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2284067630
Short name T791
Test name
Test status
Simulation time 1082282465 ps
CPU time 2.32 seconds
Started Jun 09 02:30:46 PM PDT 24
Finished Jun 09 02:30:48 PM PDT 24
Peak memory 224360 kb
Host smart-60238e7f-6022-4669-a53b-3955c4be7c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284067630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2284067630
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.787947351
Short name T554
Test name
Test status
Simulation time 31309724 ps
CPU time 0.7 seconds
Started Jun 09 02:30:57 PM PDT 24
Finished Jun 09 02:30:59 PM PDT 24
Peak memory 205180 kb
Host smart-a6a3a62b-0728-4294-80e2-5f43b7c51f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787947351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.787947351
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3688109835
Short name T830
Test name
Test status
Simulation time 561027244 ps
CPU time 6.41 seconds
Started Jun 09 02:30:49 PM PDT 24
Finished Jun 09 02:30:56 PM PDT 24
Peak memory 232524 kb
Host smart-54f538ec-939a-40f8-a9df-30d737ee6baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688109835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3688109835
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2395734402
Short name T452
Test name
Test status
Simulation time 17554795 ps
CPU time 0.77 seconds
Started Jun 09 02:30:48 PM PDT 24
Finished Jun 09 02:30:50 PM PDT 24
Peak memory 206564 kb
Host smart-36e8af79-ac78-4955-85e0-89dc8d9967ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395734402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2395734402
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3648612950
Short name T167
Test name
Test status
Simulation time 4940889845 ps
CPU time 42 seconds
Started Jun 09 02:30:50 PM PDT 24
Finished Jun 09 02:31:33 PM PDT 24
Peak memory 252228 kb
Host smart-1ae5b4e8-1b7b-4837-bb8f-62dd08fffb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648612950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3648612950
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4012216935
Short name T423
Test name
Test status
Simulation time 5152985001 ps
CPU time 56.26 seconds
Started Jun 09 02:30:51 PM PDT 24
Finished Jun 09 02:31:48 PM PDT 24
Peak memory 257020 kb
Host smart-1c686263-3cf1-4571-9a9e-c0bb05002c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012216935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4012216935
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1798498446
Short name T135
Test name
Test status
Simulation time 12688127681 ps
CPU time 21.95 seconds
Started Jun 09 02:30:48 PM PDT 24
Finished Jun 09 02:31:11 PM PDT 24
Peak memory 249836 kb
Host smart-62646a19-e6c3-49dc-bda9-5bd9242fcfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798498446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1798498446
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.999626681
Short name T366
Test name
Test status
Simulation time 154282442 ps
CPU time 2.54 seconds
Started Jun 09 02:30:45 PM PDT 24
Finished Jun 09 02:30:48 PM PDT 24
Peak memory 224276 kb
Host smart-e1186021-8ec3-4dd5-92b6-842c9966523d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999626681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.999626681
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2155577732
Short name T629
Test name
Test status
Simulation time 745254714 ps
CPU time 10.92 seconds
Started Jun 09 02:30:50 PM PDT 24
Finished Jun 09 02:31:02 PM PDT 24
Peak memory 228340 kb
Host smart-78398ccf-4f22-4ab4-a9d8-2dabdc668afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155577732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2155577732
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.513479372
Short name T728
Test name
Test status
Simulation time 146249553 ps
CPU time 2.27 seconds
Started Jun 09 02:30:50 PM PDT 24
Finished Jun 09 02:30:54 PM PDT 24
Peak memory 224268 kb
Host smart-7e26c7de-a9fb-4d45-b43b-c11964339ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513479372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.513479372
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3742179119
Short name T589
Test name
Test status
Simulation time 4513727000 ps
CPU time 8.63 seconds
Started Jun 09 02:30:37 PM PDT 24
Finished Jun 09 02:30:46 PM PDT 24
Peak memory 232636 kb
Host smart-b06e4737-ffd7-42b6-80bf-132c03d5ebd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742179119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3742179119
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3280794098
Short name T422
Test name
Test status
Simulation time 4561266189 ps
CPU time 17.69 seconds
Started Jun 09 02:30:51 PM PDT 24
Finished Jun 09 02:31:09 PM PDT 24
Peak memory 219164 kb
Host smart-1d5c5d0c-fecf-4bbe-aa42-756badcd2048
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3280794098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3280794098
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2727483712
Short name T593
Test name
Test status
Simulation time 22071641864 ps
CPU time 86.53 seconds
Started Jun 09 02:30:49 PM PDT 24
Finished Jun 09 02:32:16 PM PDT 24
Peak memory 249104 kb
Host smart-a6fb7e68-f237-4ddf-b223-ee4780e993e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727483712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2727483712
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.126342179
Short name T576
Test name
Test status
Simulation time 2596198971 ps
CPU time 23.78 seconds
Started Jun 09 02:30:47 PM PDT 24
Finished Jun 09 02:31:11 PM PDT 24
Peak memory 216216 kb
Host smart-e6b35a2d-b8f2-41d3-9b3f-b73182107888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126342179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.126342179
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2042969781
Short name T722
Test name
Test status
Simulation time 53573659 ps
CPU time 0.71 seconds
Started Jun 09 02:30:49 PM PDT 24
Finished Jun 09 02:30:50 PM PDT 24
Peak memory 205328 kb
Host smart-6167f574-856a-4f97-b039-eaae942f2556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042969781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2042969781
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1838090844
Short name T963
Test name
Test status
Simulation time 2738328909 ps
CPU time 3.59 seconds
Started Jun 09 02:30:46 PM PDT 24
Finished Jun 09 02:30:50 PM PDT 24
Peak memory 216268 kb
Host smart-3e6c1a39-96c1-4ad7-8090-c6b6bc80219e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838090844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1838090844
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2011172965
Short name T764
Test name
Test status
Simulation time 393500706 ps
CPU time 0.86 seconds
Started Jun 09 02:30:52 PM PDT 24
Finished Jun 09 02:30:54 PM PDT 24
Peak memory 205596 kb
Host smart-bc11bd14-b038-4f62-a456-41e9209966fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011172965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2011172965
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3415996919
Short name T763
Test name
Test status
Simulation time 209897032 ps
CPU time 2.37 seconds
Started Jun 09 02:30:44 PM PDT 24
Finished Jun 09 02:30:47 PM PDT 24
Peak memory 224048 kb
Host smart-78539bfd-e681-4ae9-b2f3-6bfb31463493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415996919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3415996919
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4104173060
Short name T676
Test name
Test status
Simulation time 10361729 ps
CPU time 0.73 seconds
Started Jun 09 02:30:51 PM PDT 24
Finished Jun 09 02:30:52 PM PDT 24
Peak memory 204520 kb
Host smart-41929893-066d-461a-ba28-49cc61c140ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104173060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4104173060
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2732855914
Short name T616
Test name
Test status
Simulation time 455448304 ps
CPU time 4.66 seconds
Started Jun 09 02:30:57 PM PDT 24
Finished Jun 09 02:31:02 PM PDT 24
Peak memory 232408 kb
Host smart-fe9c940a-4f0b-4a0a-be87-602a78730bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732855914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2732855914
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2785988491
Short name T307
Test name
Test status
Simulation time 15682376 ps
CPU time 0.76 seconds
Started Jun 09 02:30:53 PM PDT 24
Finished Jun 09 02:30:54 PM PDT 24
Peak memory 206212 kb
Host smart-5b22e4ee-4c80-4532-8da9-579afb075df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785988491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2785988491
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.4243518289
Short name T620
Test name
Test status
Simulation time 12157296428 ps
CPU time 42.32 seconds
Started Jun 09 02:30:47 PM PDT 24
Finished Jun 09 02:31:30 PM PDT 24
Peak memory 234676 kb
Host smart-c92be06c-42b8-4a1f-ae3b-2b17715cce0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243518289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.4243518289
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2423866361
Short name T901
Test name
Test status
Simulation time 9621235327 ps
CPU time 118.69 seconds
Started Jun 09 02:30:53 PM PDT 24
Finished Jun 09 02:32:52 PM PDT 24
Peak memory 250012 kb
Host smart-31358a3e-166f-4eef-85ca-88b728550dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423866361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2423866361
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.860925283
Short name T166
Test name
Test status
Simulation time 71154825221 ps
CPU time 676.86 seconds
Started Jun 09 02:30:48 PM PDT 24
Finished Jun 09 02:42:06 PM PDT 24
Peak memory 253304 kb
Host smart-cc9806a4-ccce-4a47-800d-7cf3d918ebf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860925283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.860925283
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1074643918
Short name T937
Test name
Test status
Simulation time 290945694 ps
CPU time 8.46 seconds
Started Jun 09 02:30:53 PM PDT 24
Finished Jun 09 02:31:02 PM PDT 24
Peak memory 228436 kb
Host smart-7df2084c-7763-476a-bdd1-dd80039983c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074643918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1074643918
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2464821001
Short name T808
Test name
Test status
Simulation time 1101623332 ps
CPU time 11.39 seconds
Started Jun 09 02:30:58 PM PDT 24
Finished Jun 09 02:31:10 PM PDT 24
Peak memory 232524 kb
Host smart-991f62c9-c1ef-419c-93d3-b58cc606b427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464821001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2464821001
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1644460965
Short name T673
Test name
Test status
Simulation time 3608069926 ps
CPU time 32.89 seconds
Started Jun 09 02:30:52 PM PDT 24
Finished Jun 09 02:31:26 PM PDT 24
Peak memory 248476 kb
Host smart-e0fd4bf5-6c7a-4cc6-9f0f-bddd7e34654b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644460965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1644460965
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3870796699
Short name T254
Test name
Test status
Simulation time 2539345244 ps
CPU time 7.94 seconds
Started Jun 09 02:30:51 PM PDT 24
Finished Jun 09 02:31:00 PM PDT 24
Peak memory 224312 kb
Host smart-238f1a57-b704-4866-9c26-3a254d9d3398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870796699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3870796699
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3835483676
Short name T383
Test name
Test status
Simulation time 16578203923 ps
CPU time 41.84 seconds
Started Jun 09 02:30:54 PM PDT 24
Finished Jun 09 02:31:36 PM PDT 24
Peak memory 249016 kb
Host smart-ea26e4e2-3108-4b59-a2af-2b9ac96cd8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835483676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3835483676
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3375984829
Short name T471
Test name
Test status
Simulation time 3488246344 ps
CPU time 11.89 seconds
Started Jun 09 02:30:54 PM PDT 24
Finished Jun 09 02:31:06 PM PDT 24
Peak memory 222240 kb
Host smart-823e19df-47ec-41ab-bf53-58b447da9058
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3375984829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3375984829
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2234871625
Short name T469
Test name
Test status
Simulation time 5634379276 ps
CPU time 34.3 seconds
Started Jun 09 02:30:52 PM PDT 24
Finished Jun 09 02:31:27 PM PDT 24
Peak memory 216164 kb
Host smart-94fe19bd-8ae3-42cb-87b4-85dda72bc940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234871625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2234871625
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3458579120
Short name T494
Test name
Test status
Simulation time 8601486643 ps
CPU time 21.99 seconds
Started Jun 09 02:30:49 PM PDT 24
Finished Jun 09 02:31:11 PM PDT 24
Peak memory 216152 kb
Host smart-98076e08-bb87-4244-bbfa-2b975239ffba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458579120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3458579120
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.740796501
Short name T690
Test name
Test status
Simulation time 40753085 ps
CPU time 0.81 seconds
Started Jun 09 02:30:51 PM PDT 24
Finished Jun 09 02:30:53 PM PDT 24
Peak memory 206276 kb
Host smart-19d8cab1-5211-4465-a4a2-a4b772366b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740796501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.740796501
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1416819276
Short name T436
Test name
Test status
Simulation time 68087510 ps
CPU time 0.92 seconds
Started Jun 09 02:30:48 PM PDT 24
Finished Jun 09 02:30:50 PM PDT 24
Peak memory 206076 kb
Host smart-78f69d2f-cee2-4897-aea5-242302e9becc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416819276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1416819276
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3918045068
Short name T701
Test name
Test status
Simulation time 26963503125 ps
CPU time 10.1 seconds
Started Jun 09 02:30:57 PM PDT 24
Finished Jun 09 02:31:08 PM PDT 24
Peak memory 224376 kb
Host smart-29aa6d94-0303-4e80-9999-334663c7ac7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918045068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3918045068
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1296742114
Short name T324
Test name
Test status
Simulation time 11142387 ps
CPU time 0.72 seconds
Started Jun 09 02:31:00 PM PDT 24
Finished Jun 09 02:31:01 PM PDT 24
Peak memory 205208 kb
Host smart-4b6918f4-e356-4bd8-aa20-17be9f13021b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296742114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1296742114
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.4103121114
Short name T973
Test name
Test status
Simulation time 165940548 ps
CPU time 4.5 seconds
Started Jun 09 02:30:53 PM PDT 24
Finished Jun 09 02:30:58 PM PDT 24
Peak memory 232516 kb
Host smart-87a73a32-08a4-4385-9fcc-6664eef865af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103121114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.4103121114
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.4049893802
Short name T53
Test name
Test status
Simulation time 28035168 ps
CPU time 0.79 seconds
Started Jun 09 02:30:50 PM PDT 24
Finished Jun 09 02:30:52 PM PDT 24
Peak memory 206456 kb
Host smart-460ec110-449e-436f-9a92-f50f9405fcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049893802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.4049893802
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1631724823
Short name T929
Test name
Test status
Simulation time 15538026599 ps
CPU time 77.57 seconds
Started Jun 09 02:30:47 PM PDT 24
Finished Jun 09 02:32:05 PM PDT 24
Peak memory 240460 kb
Host smart-70121f46-eae6-4529-8a6b-672f30cf9c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631724823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1631724823
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2766810849
Short name T174
Test name
Test status
Simulation time 425793885242 ps
CPU time 460.85 seconds
Started Jun 09 02:30:51 PM PDT 24
Finished Jun 09 02:38:33 PM PDT 24
Peak memory 251492 kb
Host smart-e9701b5d-f5b4-40a8-833a-673aebd6b77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766810849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2766810849
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1155299360
Short name T275
Test name
Test status
Simulation time 4746280676 ps
CPU time 114.33 seconds
Started Jun 09 02:31:01 PM PDT 24
Finished Jun 09 02:32:56 PM PDT 24
Peak memory 249208 kb
Host smart-57a41b14-fbb8-4c53-b445-561353126198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155299360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1155299360
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2754094474
Short name T4
Test name
Test status
Simulation time 992468456 ps
CPU time 4.11 seconds
Started Jun 09 02:30:53 PM PDT 24
Finished Jun 09 02:30:58 PM PDT 24
Peak memory 224336 kb
Host smart-c177d920-4db3-4e36-8629-6b42dbb42f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754094474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2754094474
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.75957952
Short name T466
Test name
Test status
Simulation time 1648601077 ps
CPU time 3.64 seconds
Started Jun 09 02:30:56 PM PDT 24
Finished Jun 09 02:31:00 PM PDT 24
Peak memory 218380 kb
Host smart-f29b4d71-c106-4990-a50f-d77c9790e3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75957952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.75957952
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3264948598
Short name T615
Test name
Test status
Simulation time 109401705 ps
CPU time 2.57 seconds
Started Jun 09 02:30:53 PM PDT 24
Finished Jun 09 02:30:56 PM PDT 24
Peak memory 232292 kb
Host smart-86c8fe3a-5e61-438a-aa37-b03ea80511be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264948598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3264948598
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1168168595
Short name T411
Test name
Test status
Simulation time 25784921349 ps
CPU time 22.94 seconds
Started Jun 09 02:30:49 PM PDT 24
Finished Jun 09 02:31:13 PM PDT 24
Peak memory 232564 kb
Host smart-38a53d57-473a-40d2-961c-bd20af32c401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168168595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1168168595
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1323170951
Short name T782
Test name
Test status
Simulation time 232773522020 ps
CPU time 30.94 seconds
Started Jun 09 02:30:44 PM PDT 24
Finished Jun 09 02:31:16 PM PDT 24
Peak memory 238948 kb
Host smart-984dfd34-04c0-455c-9e61-32fbfae45996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323170951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1323170951
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.137013801
Short name T393
Test name
Test status
Simulation time 262448172 ps
CPU time 3.46 seconds
Started Jun 09 02:30:52 PM PDT 24
Finished Jun 09 02:30:56 PM PDT 24
Peak memory 218964 kb
Host smart-a80826fc-04cf-4f7a-983b-219eb6e0898d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=137013801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.137013801
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.134210635
Short name T299
Test name
Test status
Simulation time 3461913374 ps
CPU time 9.94 seconds
Started Jun 09 02:30:49 PM PDT 24
Finished Jun 09 02:31:00 PM PDT 24
Peak memory 216156 kb
Host smart-2dd1c718-6428-477b-b0b9-62e0ab42adee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134210635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.134210635
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.85822718
Short name T535
Test name
Test status
Simulation time 47761046 ps
CPU time 1.07 seconds
Started Jun 09 02:30:53 PM PDT 24
Finished Jun 09 02:30:54 PM PDT 24
Peak memory 207468 kb
Host smart-5863e380-3276-4b67-b5d1-6ebd2d42f8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85822718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.85822718
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2174535286
Short name T641
Test name
Test status
Simulation time 868674538 ps
CPU time 2.03 seconds
Started Jun 09 02:30:51 PM PDT 24
Finished Jun 09 02:30:54 PM PDT 24
Peak memory 216052 kb
Host smart-37c1070f-2860-4b00-ac9b-f9b5b900eb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174535286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2174535286
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1175834152
Short name T301
Test name
Test status
Simulation time 25090962 ps
CPU time 0.98 seconds
Started Jun 09 02:30:50 PM PDT 24
Finished Jun 09 02:30:52 PM PDT 24
Peak memory 205596 kb
Host smart-6b7ae47a-81a2-4a2e-83b7-eb59a61e63f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175834152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1175834152
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2315707226
Short name T890
Test name
Test status
Simulation time 488652692 ps
CPU time 2.46 seconds
Started Jun 09 02:30:49 PM PDT 24
Finished Jun 09 02:30:52 PM PDT 24
Peak memory 224324 kb
Host smart-997677c6-bdb4-42d9-a2c9-a9d04f150758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315707226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2315707226
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2812560331
Short name T662
Test name
Test status
Simulation time 12940051 ps
CPU time 0.74 seconds
Started Jun 09 02:31:01 PM PDT 24
Finished Jun 09 02:31:02 PM PDT 24
Peak memory 204536 kb
Host smart-0d79e771-e306-43ae-b927-18ba78113337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812560331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2812560331
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1529901686
Short name T682
Test name
Test status
Simulation time 246955373 ps
CPU time 2.96 seconds
Started Jun 09 02:30:49 PM PDT 24
Finished Jun 09 02:30:53 PM PDT 24
Peak memory 232536 kb
Host smart-3d66d25d-8278-45fd-92cb-67171821e161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529901686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1529901686
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.662825645
Short name T458
Test name
Test status
Simulation time 20736928 ps
CPU time 0.86 seconds
Started Jun 09 02:30:55 PM PDT 24
Finished Jun 09 02:30:57 PM PDT 24
Peak memory 206232 kb
Host smart-278f580f-45f0-427c-9aee-831eb62ad7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662825645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.662825645
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.4049846413
Short name T666
Test name
Test status
Simulation time 9787263626 ps
CPU time 80.88 seconds
Started Jun 09 02:30:59 PM PDT 24
Finished Jun 09 02:32:21 PM PDT 24
Peak memory 238416 kb
Host smart-860bc7cb-b281-4a5a-99b1-52e05eed4ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049846413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4049846413
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1739845599
Short name T443
Test name
Test status
Simulation time 5813279371 ps
CPU time 20.95 seconds
Started Jun 09 02:31:00 PM PDT 24
Finished Jun 09 02:31:22 PM PDT 24
Peak memory 240488 kb
Host smart-835cfafa-1e9b-4c20-a5fa-f8be571b172c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739845599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1739845599
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.554944778
Short name T21
Test name
Test status
Simulation time 13002162628 ps
CPU time 38.97 seconds
Started Jun 09 02:30:57 PM PDT 24
Finished Jun 09 02:31:36 PM PDT 24
Peak memory 250352 kb
Host smart-6f614393-06aa-49a7-8ced-d55f1e1261f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554944778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.554944778
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2334308761
Short name T537
Test name
Test status
Simulation time 170024841 ps
CPU time 4.41 seconds
Started Jun 09 02:30:54 PM PDT 24
Finished Jun 09 02:30:58 PM PDT 24
Peak memory 224328 kb
Host smart-9f3cc978-cbc9-4c78-acb7-566b024ae0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334308761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2334308761
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1851812720
Short name T257
Test name
Test status
Simulation time 5776720798 ps
CPU time 10.44 seconds
Started Jun 09 02:30:56 PM PDT 24
Finished Jun 09 02:31:07 PM PDT 24
Peak memory 224340 kb
Host smart-e5553a22-e819-4fa6-b625-ae83a360e1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851812720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1851812720
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.398407497
Short name T940
Test name
Test status
Simulation time 23620668571 ps
CPU time 60.36 seconds
Started Jun 09 02:30:50 PM PDT 24
Finished Jun 09 02:31:52 PM PDT 24
Peak memory 240752 kb
Host smart-75bd8d87-2d8e-49eb-ab13-fa5ebc1a4696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398407497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.398407497
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1575678931
Short name T454
Test name
Test status
Simulation time 11597070125 ps
CPU time 11.33 seconds
Started Jun 09 02:31:00 PM PDT 24
Finished Jun 09 02:31:12 PM PDT 24
Peak memory 224212 kb
Host smart-00b6d697-4898-4e0b-a2e7-55e7677c5e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575678931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1575678931
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1689650234
Short name T437
Test name
Test status
Simulation time 502752294 ps
CPU time 3.7 seconds
Started Jun 09 02:30:48 PM PDT 24
Finished Jun 09 02:30:52 PM PDT 24
Peak memory 224324 kb
Host smart-bcc69352-0441-4970-870f-0133c87be5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689650234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1689650234
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3014805215
Short name T539
Test name
Test status
Simulation time 715322718 ps
CPU time 10.16 seconds
Started Jun 09 02:30:58 PM PDT 24
Finished Jun 09 02:31:09 PM PDT 24
Peak memory 223040 kb
Host smart-778e6551-d9ff-48e7-8752-d5fbb808e15f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3014805215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3014805215
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1271962129
Short name T555
Test name
Test status
Simulation time 405334698 ps
CPU time 1 seconds
Started Jun 09 02:31:00 PM PDT 24
Finished Jun 09 02:31:01 PM PDT 24
Peak memory 206472 kb
Host smart-59b3e978-9890-47ac-9113-72a26a51c64c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271962129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1271962129
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2768921015
Short name T741
Test name
Test status
Simulation time 26430187005 ps
CPU time 34.13 seconds
Started Jun 09 02:31:01 PM PDT 24
Finished Jun 09 02:31:36 PM PDT 24
Peak memory 216112 kb
Host smart-0a92de40-abcf-4758-b84f-ab42181d0c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768921015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2768921015
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1506697140
Short name T825
Test name
Test status
Simulation time 3020191574 ps
CPU time 6.9 seconds
Started Jun 09 02:30:53 PM PDT 24
Finished Jun 09 02:31:01 PM PDT 24
Peak memory 216104 kb
Host smart-ac9e95ce-0b63-46cb-ad8c-5dadec20838c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506697140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1506697140
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1601824977
Short name T602
Test name
Test status
Simulation time 159623152 ps
CPU time 1.91 seconds
Started Jun 09 02:30:54 PM PDT 24
Finished Jun 09 02:30:56 PM PDT 24
Peak memory 216052 kb
Host smart-d463dca4-19db-47ee-90e2-713f145e13ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601824977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1601824977
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2159301750
Short name T510
Test name
Test status
Simulation time 24804675 ps
CPU time 0.79 seconds
Started Jun 09 02:30:59 PM PDT 24
Finished Jun 09 02:31:00 PM PDT 24
Peak memory 205576 kb
Host smart-b78efef9-7d09-446e-b939-35b1ecab11ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159301750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2159301750
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.4191682046
Short name T799
Test name
Test status
Simulation time 434040528 ps
CPU time 8.21 seconds
Started Jun 09 02:31:06 PM PDT 24
Finished Jun 09 02:31:14 PM PDT 24
Peak memory 233612 kb
Host smart-287b0f43-6902-4f17-8737-5b92f37035b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191682046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4191682046
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2188321252
Short name T868
Test name
Test status
Simulation time 79330760 ps
CPU time 0.69 seconds
Started Jun 09 02:30:59 PM PDT 24
Finished Jun 09 02:31:01 PM PDT 24
Peak memory 205112 kb
Host smart-ee79f8e3-7c90-43d4-ad52-7568ca2b2d44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188321252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2188321252
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2637793274
Short name T3
Test name
Test status
Simulation time 745380485 ps
CPU time 8.06 seconds
Started Jun 09 02:31:02 PM PDT 24
Finished Jun 09 02:31:11 PM PDT 24
Peak memory 232568 kb
Host smart-55c4e988-2aa5-48cd-9be3-67688054d1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637793274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2637793274
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1844393973
Short name T919
Test name
Test status
Simulation time 26584223 ps
CPU time 0.79 seconds
Started Jun 09 02:30:58 PM PDT 24
Finished Jun 09 02:30:59 PM PDT 24
Peak memory 206748 kb
Host smart-df793da2-e9c8-4da1-8ac7-72af3d67c4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844393973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1844393973
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3130974292
Short name T781
Test name
Test status
Simulation time 7863053847 ps
CPU time 8.89 seconds
Started Jun 09 02:31:04 PM PDT 24
Finished Jun 09 02:31:13 PM PDT 24
Peak memory 217308 kb
Host smart-30c8f2a4-12f8-4a75-a25d-b0cd14120dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130974292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3130974292
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2360335073
Short name T163
Test name
Test status
Simulation time 45774012221 ps
CPU time 172.73 seconds
Started Jun 09 02:31:02 PM PDT 24
Finished Jun 09 02:33:55 PM PDT 24
Peak memory 262804 kb
Host smart-a8339d59-30a7-4681-9f2d-0c8ef5d31c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360335073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2360335073
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.586763749
Short name T387
Test name
Test status
Simulation time 958618707 ps
CPU time 4.24 seconds
Started Jun 09 02:30:57 PM PDT 24
Finished Jun 09 02:31:02 PM PDT 24
Peak memory 218564 kb
Host smart-97d6b8d6-66a4-4401-897d-a6c93f7dd5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586763749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.586763749
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2894451473
Short name T930
Test name
Test status
Simulation time 77026428 ps
CPU time 2.25 seconds
Started Jun 09 02:30:59 PM PDT 24
Finished Jun 09 02:31:01 PM PDT 24
Peak memory 232552 kb
Host smart-50894e2e-d848-45eb-97c0-a599ed6f93b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894451473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2894451473
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1032943393
Short name T875
Test name
Test status
Simulation time 98726851933 ps
CPU time 51.07 seconds
Started Jun 09 02:31:01 PM PDT 24
Finished Jun 09 02:31:52 PM PDT 24
Peak memory 240216 kb
Host smart-71f530a4-cb4c-479a-9b3e-67f62010ab80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032943393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1032943393
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4234731725
Short name T277
Test name
Test status
Simulation time 531691087 ps
CPU time 4.94 seconds
Started Jun 09 02:30:57 PM PDT 24
Finished Jun 09 02:31:02 PM PDT 24
Peak memory 232520 kb
Host smart-8666d825-605b-4c7d-bb85-b9a4f7e7cbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234731725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4234731725
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4131554458
Short name T414
Test name
Test status
Simulation time 199382369 ps
CPU time 5.13 seconds
Started Jun 09 02:31:01 PM PDT 24
Finished Jun 09 02:31:07 PM PDT 24
Peak memory 232508 kb
Host smart-c8c6e240-0567-4f08-82c8-44052bb269cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131554458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4131554458
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2962335041
Short name T37
Test name
Test status
Simulation time 1145752886 ps
CPU time 16.76 seconds
Started Jun 09 02:30:59 PM PDT 24
Finished Jun 09 02:31:16 PM PDT 24
Peak memory 218936 kb
Host smart-231bf65f-ab98-42e2-b79d-5dd8174a014f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2962335041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2962335041
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2478022169
Short name T144
Test name
Test status
Simulation time 298070377 ps
CPU time 1.26 seconds
Started Jun 09 02:30:57 PM PDT 24
Finished Jun 09 02:30:59 PM PDT 24
Peak memory 206580 kb
Host smart-44189a7d-0827-4831-bd51-c896d1d0d219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478022169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2478022169
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2495098171
Short name T9
Test name
Test status
Simulation time 5076151886 ps
CPU time 12.92 seconds
Started Jun 09 02:31:00 PM PDT 24
Finished Jun 09 02:31:13 PM PDT 24
Peak memory 216168 kb
Host smart-659c8106-6faa-4387-8288-c74768a1cfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495098171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2495098171
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1206452888
Short name T475
Test name
Test status
Simulation time 1831061956 ps
CPU time 5.29 seconds
Started Jun 09 02:30:49 PM PDT 24
Finished Jun 09 02:30:55 PM PDT 24
Peak memory 216084 kb
Host smart-343edaad-5184-4d93-b7ef-e5bdbcdc2307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206452888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1206452888
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.184616118
Short name T964
Test name
Test status
Simulation time 1515346810 ps
CPU time 2.41 seconds
Started Jun 09 02:30:56 PM PDT 24
Finished Jun 09 02:30:59 PM PDT 24
Peak memory 216064 kb
Host smart-c5265615-0bac-4b9d-a0ff-baaa99a68566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184616118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.184616118
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1432798800
Short name T687
Test name
Test status
Simulation time 17204215 ps
CPU time 0.73 seconds
Started Jun 09 02:30:51 PM PDT 24
Finished Jun 09 02:30:53 PM PDT 24
Peak memory 205600 kb
Host smart-661dcb2a-050d-4d81-af0e-0b21f5601458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432798800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1432798800
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2780491806
Short name T956
Test name
Test status
Simulation time 360424866 ps
CPU time 6.68 seconds
Started Jun 09 02:31:01 PM PDT 24
Finished Jun 09 02:31:08 PM PDT 24
Peak memory 224308 kb
Host smart-323345bb-ecd0-4ffe-bc11-2c6dae93aeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780491806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2780491806
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1648404766
Short name T348
Test name
Test status
Simulation time 13242032 ps
CPU time 0.78 seconds
Started Jun 09 02:31:00 PM PDT 24
Finished Jun 09 02:31:01 PM PDT 24
Peak memory 204528 kb
Host smart-310bc8db-fe09-48bc-9384-c248eee67abf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648404766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1648404766
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1348196688
Short name T420
Test name
Test status
Simulation time 1565387506 ps
CPU time 3.28 seconds
Started Jun 09 02:31:03 PM PDT 24
Finished Jun 09 02:31:07 PM PDT 24
Peak memory 232532 kb
Host smart-bdfdb1fe-174e-4af7-a106-ad49845d15d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348196688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1348196688
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3137217233
Short name T965
Test name
Test status
Simulation time 17021842 ps
CPU time 0.79 seconds
Started Jun 09 02:30:49 PM PDT 24
Finished Jun 09 02:30:50 PM PDT 24
Peak memory 206212 kb
Host smart-6e79cf90-00bf-406d-bd8d-a3bd2fd69ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137217233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3137217233
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1255463749
Short name T518
Test name
Test status
Simulation time 3078624007 ps
CPU time 49.96 seconds
Started Jun 09 02:30:58 PM PDT 24
Finished Jun 09 02:31:49 PM PDT 24
Peak memory 249204 kb
Host smart-0b04d03a-1a69-44a1-b0b4-b71ea54a7f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255463749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1255463749
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1572057028
Short name T122
Test name
Test status
Simulation time 33771088329 ps
CPU time 302.38 seconds
Started Jun 09 02:31:00 PM PDT 24
Finished Jun 09 02:36:03 PM PDT 24
Peak memory 249076 kb
Host smart-3ce2f5dd-e01b-416c-ada0-651440e55ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572057028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1572057028
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2348434384
Short name T493
Test name
Test status
Simulation time 12271799252 ps
CPU time 114 seconds
Started Jun 09 02:31:02 PM PDT 24
Finished Jun 09 02:32:56 PM PDT 24
Peak memory 240824 kb
Host smart-fb33fd86-02b0-4450-95fb-fd61423f8b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348434384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2348434384
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.525095697
Short name T780
Test name
Test status
Simulation time 10671325451 ps
CPU time 39.19 seconds
Started Jun 09 02:31:03 PM PDT 24
Finished Jun 09 02:31:42 PM PDT 24
Peak memory 232572 kb
Host smart-b5fe0e66-2ccb-4431-844f-8aedd36a4ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525095697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.525095697
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2901826415
Short name T502
Test name
Test status
Simulation time 1497660424 ps
CPU time 3.71 seconds
Started Jun 09 02:31:02 PM PDT 24
Finished Jun 09 02:31:06 PM PDT 24
Peak memory 232536 kb
Host smart-1870befe-66ce-45dc-9430-03f60f68fe4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901826415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2901826415
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3771357184
Short name T538
Test name
Test status
Simulation time 107016019 ps
CPU time 2.05 seconds
Started Jun 09 02:31:04 PM PDT 24
Finished Jun 09 02:31:06 PM PDT 24
Peak memory 222992 kb
Host smart-533fcca6-deb4-44f5-9b74-9ccc0e7d6e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771357184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3771357184
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.42253728
Short name T603
Test name
Test status
Simulation time 517209051 ps
CPU time 4.91 seconds
Started Jun 09 02:30:58 PM PDT 24
Finished Jun 09 02:31:04 PM PDT 24
Peak memory 232504 kb
Host smart-e534074c-5139-4c27-aff0-4966d477e064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42253728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.42253728
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2989855898
Short name T12
Test name
Test status
Simulation time 1176028879 ps
CPU time 3.28 seconds
Started Jun 09 02:30:59 PM PDT 24
Finished Jun 09 02:31:03 PM PDT 24
Peak memory 224308 kb
Host smart-b27f6674-fe49-4cf1-9634-157117f2b3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989855898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2989855898
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2444497755
Short name T134
Test name
Test status
Simulation time 395328596 ps
CPU time 5.12 seconds
Started Jun 09 02:31:03 PM PDT 24
Finished Jun 09 02:31:08 PM PDT 24
Peak memory 222172 kb
Host smart-57824fd9-0def-43be-981e-3c8f4e52efcb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2444497755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2444497755
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1114746462
Short name T195
Test name
Test status
Simulation time 42291981113 ps
CPU time 465.21 seconds
Started Jun 09 02:31:00 PM PDT 24
Finished Jun 09 02:38:45 PM PDT 24
Peak memory 257004 kb
Host smart-9b982906-064d-47ee-8c95-34502b48ca88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114746462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1114746462
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2684206114
Short name T364
Test name
Test status
Simulation time 4743609128 ps
CPU time 6.83 seconds
Started Jun 09 02:30:58 PM PDT 24
Finished Jun 09 02:31:05 PM PDT 24
Peak memory 216156 kb
Host smart-0762a28e-a74d-4e66-a0ba-43d0d7ced97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684206114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2684206114
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2233087432
Short name T921
Test name
Test status
Simulation time 50853359219 ps
CPU time 19.38 seconds
Started Jun 09 02:31:01 PM PDT 24
Finished Jun 09 02:31:21 PM PDT 24
Peak memory 216164 kb
Host smart-03d65d77-0324-4ab1-84f5-4789ee2c6b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233087432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2233087432
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2989946307
Short name T630
Test name
Test status
Simulation time 313578852 ps
CPU time 2.18 seconds
Started Jun 09 02:30:54 PM PDT 24
Finished Jun 09 02:30:56 PM PDT 24
Peak memory 216000 kb
Host smart-614f081d-2b7b-43cf-8d10-da147be41ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989946307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2989946307
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3363366606
Short name T756
Test name
Test status
Simulation time 20018774 ps
CPU time 0.67 seconds
Started Jun 09 02:30:52 PM PDT 24
Finished Jun 09 02:30:53 PM PDT 24
Peak memory 205592 kb
Host smart-daf6d88d-0339-4ea4-ba9f-cdd8551a5dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363366606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3363366606
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2185353249
Short name T248
Test name
Test status
Simulation time 1220694389 ps
CPU time 4.2 seconds
Started Jun 09 02:31:08 PM PDT 24
Finished Jun 09 02:31:13 PM PDT 24
Peak memory 224320 kb
Host smart-79ab8dbe-c8e0-4f36-a126-d91dfbc2e685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185353249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2185353249
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.4054356289
Short name T734
Test name
Test status
Simulation time 11361707 ps
CPU time 0.69 seconds
Started Jun 09 02:31:02 PM PDT 24
Finished Jun 09 02:31:03 PM PDT 24
Peak memory 205500 kb
Host smart-87ac785c-98eb-45c5-9909-3b9fdbd37030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054356289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
4054356289
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3891775034
Short name T671
Test name
Test status
Simulation time 1080495751 ps
CPU time 12 seconds
Started Jun 09 02:31:02 PM PDT 24
Finished Jun 09 02:31:14 PM PDT 24
Peak memory 224300 kb
Host smart-be85a1bf-ae0c-4742-80e3-5b6491f8804f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891775034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3891775034
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1111149218
Short name T660
Test name
Test status
Simulation time 30048653 ps
CPU time 0.79 seconds
Started Jun 09 02:31:00 PM PDT 24
Finished Jun 09 02:31:01 PM PDT 24
Peak memory 206260 kb
Host smart-ee43b9d6-013c-4525-940e-e04cd2de4af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111149218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1111149218
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.4213275838
Short name T884
Test name
Test status
Simulation time 14118561744 ps
CPU time 128.84 seconds
Started Jun 09 02:31:11 PM PDT 24
Finished Jun 09 02:33:20 PM PDT 24
Peak memory 257180 kb
Host smart-b2b4dbe3-bb9a-40bb-a3a6-6cd1eafdcb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213275838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.4213275838
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2147205253
Short name T41
Test name
Test status
Simulation time 18457017743 ps
CPU time 121.69 seconds
Started Jun 09 02:31:03 PM PDT 24
Finished Jun 09 02:33:05 PM PDT 24
Peak memory 249320 kb
Host smart-d163d2a2-44c0-4c94-8b64-d42d9052f264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147205253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2147205253
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4181109064
Short name T647
Test name
Test status
Simulation time 12578633270 ps
CPU time 46.03 seconds
Started Jun 09 02:31:07 PM PDT 24
Finished Jun 09 02:31:53 PM PDT 24
Peak memory 224452 kb
Host smart-c51036c4-2ecd-40cc-a35d-9d95c9cbe464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181109064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4181109064
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1795835125
Short name T282
Test name
Test status
Simulation time 649353591 ps
CPU time 15.49 seconds
Started Jun 09 02:31:08 PM PDT 24
Finished Jun 09 02:31:24 PM PDT 24
Peak memory 232528 kb
Host smart-a9c54c83-a973-4437-b66f-93be93b11093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795835125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1795835125
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1560145929
Short name T183
Test name
Test status
Simulation time 11811339840 ps
CPU time 15.43 seconds
Started Jun 09 02:31:03 PM PDT 24
Finished Jun 09 02:31:19 PM PDT 24
Peak memory 224336 kb
Host smart-54f78afb-0cd3-4fb2-9917-ec9e022611cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560145929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1560145929
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1270744371
Short name T490
Test name
Test status
Simulation time 5854381816 ps
CPU time 46.1 seconds
Started Jun 09 02:31:02 PM PDT 24
Finished Jun 09 02:31:49 PM PDT 24
Peak memory 232588 kb
Host smart-505be86a-87ad-4342-993a-3565db458613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270744371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1270744371
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1746801911
Short name T867
Test name
Test status
Simulation time 18179337390 ps
CPU time 24.21 seconds
Started Jun 09 02:31:02 PM PDT 24
Finished Jun 09 02:31:27 PM PDT 24
Peak memory 232612 kb
Host smart-cb808796-b605-4b26-a73f-920df594850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746801911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1746801911
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2287022603
Short name T398
Test name
Test status
Simulation time 799012712 ps
CPU time 3.26 seconds
Started Jun 09 02:31:06 PM PDT 24
Finished Jun 09 02:31:09 PM PDT 24
Peak memory 232516 kb
Host smart-04b1e4d9-cccb-4990-a566-bdca8eefdedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287022603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2287022603
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2675080808
Short name T748
Test name
Test status
Simulation time 230582710 ps
CPU time 5.18 seconds
Started Jun 09 02:31:07 PM PDT 24
Finished Jun 09 02:31:13 PM PDT 24
Peak memory 222760 kb
Host smart-5129c8f4-00ed-446d-ab04-869a4d5457c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2675080808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2675080808
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2203614772
Short name T292
Test name
Test status
Simulation time 1709415431 ps
CPU time 12.35 seconds
Started Jun 09 02:31:05 PM PDT 24
Finished Jun 09 02:31:18 PM PDT 24
Peak memory 216420 kb
Host smart-89f298c8-a6be-4137-940c-e47d36ebb47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203614772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2203614772
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3758099745
Short name T695
Test name
Test status
Simulation time 548343638 ps
CPU time 1.81 seconds
Started Jun 09 02:31:03 PM PDT 24
Finished Jun 09 02:31:05 PM PDT 24
Peak memory 207636 kb
Host smart-5329a607-3f02-4cb7-89cb-8dde6c5d8c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758099745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3758099745
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3446513562
Short name T511
Test name
Test status
Simulation time 159608531 ps
CPU time 1.48 seconds
Started Jun 09 02:31:04 PM PDT 24
Finished Jun 09 02:31:06 PM PDT 24
Peak memory 216088 kb
Host smart-817e7fbb-1482-4136-8e7f-1de8d7a147d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446513562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3446513562
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1142050107
Short name T391
Test name
Test status
Simulation time 134372428 ps
CPU time 0.82 seconds
Started Jun 09 02:31:06 PM PDT 24
Finished Jun 09 02:31:07 PM PDT 24
Peak memory 205588 kb
Host smart-6ca50a64-064b-4cdc-a9c2-393f189ce031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142050107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1142050107
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1411651666
Short name T267
Test name
Test status
Simulation time 14795954737 ps
CPU time 25.51 seconds
Started Jun 09 02:31:00 PM PDT 24
Finished Jun 09 02:31:26 PM PDT 24
Peak memory 232596 kb
Host smart-85486471-3d01-44e0-9ce9-74d4638526db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411651666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1411651666
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2667738453
Short name T907
Test name
Test status
Simulation time 134735831 ps
CPU time 0.74 seconds
Started Jun 09 02:29:08 PM PDT 24
Finished Jun 09 02:29:09 PM PDT 24
Peak memory 205500 kb
Host smart-3f4f8c35-d18a-433c-ba16-2a1711b1f9f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667738453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
667738453
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3039349851
Short name T685
Test name
Test status
Simulation time 268029266 ps
CPU time 4.23 seconds
Started Jun 09 02:29:08 PM PDT 24
Finished Jun 09 02:29:13 PM PDT 24
Peak memory 232484 kb
Host smart-dd538572-9788-4f49-bea9-8f884dc795ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039349851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3039349851
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4260965587
Short name T716
Test name
Test status
Simulation time 15023141 ps
CPU time 0.79 seconds
Started Jun 09 02:29:03 PM PDT 24
Finished Jun 09 02:29:04 PM PDT 24
Peak memory 206200 kb
Host smart-ec8e1abc-ebad-488e-9a5c-93b02d328707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260965587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4260965587
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2028787291
Short name T505
Test name
Test status
Simulation time 3433243136 ps
CPU time 42.02 seconds
Started Jun 09 02:29:04 PM PDT 24
Finished Jun 09 02:29:47 PM PDT 24
Peak memory 240752 kb
Host smart-d95047d0-cdc8-4211-b987-4f1ddfb8da17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028787291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2028787291
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1340412834
Short name T291
Test name
Test status
Simulation time 3125755429 ps
CPU time 22.79 seconds
Started Jun 09 02:29:07 PM PDT 24
Finished Jun 09 02:29:31 PM PDT 24
Peak memory 217204 kb
Host smart-ac0697dc-4d81-47a4-b37a-3955ca3aa274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340412834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1340412834
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1906278733
Short name T30
Test name
Test status
Simulation time 131230079302 ps
CPU time 326.38 seconds
Started Jun 09 02:29:08 PM PDT 24
Finished Jun 09 02:34:35 PM PDT 24
Peak memory 250388 kb
Host smart-13c4710f-88a1-49e6-8a48-4d1ff08812df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906278733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1906278733
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1340959467
Short name T304
Test name
Test status
Simulation time 1070267847 ps
CPU time 8.64 seconds
Started Jun 09 02:29:21 PM PDT 24
Finished Jun 09 02:29:30 PM PDT 24
Peak memory 240680 kb
Host smart-9b8e65bd-7732-47f0-adad-1788af54cdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340959467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1340959467
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4171598325
Short name T412
Test name
Test status
Simulation time 1155034474 ps
CPU time 6.36 seconds
Started Jun 09 02:29:14 PM PDT 24
Finished Jun 09 02:29:21 PM PDT 24
Peak memory 232520 kb
Host smart-51148f1b-dcce-492e-9a4e-05a69dcc034e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171598325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4171598325
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1383728609
Short name T186
Test name
Test status
Simulation time 705200516 ps
CPU time 14.55 seconds
Started Jun 09 02:29:21 PM PDT 24
Finished Jun 09 02:29:36 PM PDT 24
Peak memory 240756 kb
Host smart-32b5e3ab-951b-4e11-8a98-08857be96738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383728609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1383728609
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.377237377
Short name T468
Test name
Test status
Simulation time 26695233 ps
CPU time 1.07 seconds
Started Jun 09 02:29:20 PM PDT 24
Finished Jun 09 02:29:21 PM PDT 24
Peak memory 216388 kb
Host smart-81d36eb6-3376-456c-9d6b-bb46cbd425c6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377237377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.377237377
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2782099660
Short name T667
Test name
Test status
Simulation time 2343970199 ps
CPU time 4.74 seconds
Started Jun 09 02:29:11 PM PDT 24
Finished Jun 09 02:29:26 PM PDT 24
Peak memory 218452 kb
Host smart-7eb06e5f-7dc5-4a62-a986-b06726b50d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782099660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2782099660
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4247235936
Short name T605
Test name
Test status
Simulation time 1101687195 ps
CPU time 5.72 seconds
Started Jun 09 02:29:17 PM PDT 24
Finished Jun 09 02:29:23 PM PDT 24
Peak memory 224292 kb
Host smart-137bc7c8-9f79-4205-b99e-e5735b00210f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247235936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4247235936
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2265611129
Short name T375
Test name
Test status
Simulation time 950772657 ps
CPU time 4.87 seconds
Started Jun 09 02:29:00 PM PDT 24
Finished Jun 09 02:29:05 PM PDT 24
Peak memory 219116 kb
Host smart-00b103f5-88cd-4bd0-ade0-03b71b89c78c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2265611129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2265611129
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1487061451
Short name T214
Test name
Test status
Simulation time 252888483230 ps
CPU time 770.25 seconds
Started Jun 09 02:29:02 PM PDT 24
Finished Jun 09 02:41:53 PM PDT 24
Peak memory 281188 kb
Host smart-8c0c6647-2f30-4f84-9adb-1b47143453f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487061451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1487061451
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3521438485
Short name T295
Test name
Test status
Simulation time 3909638358 ps
CPU time 10.56 seconds
Started Jun 09 02:28:58 PM PDT 24
Finished Jun 09 02:29:08 PM PDT 24
Peak memory 216152 kb
Host smart-6850737f-30a7-425f-baea-b77ec6426609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521438485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3521438485
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2035207121
Short name T525
Test name
Test status
Simulation time 5589986560 ps
CPU time 5.9 seconds
Started Jun 09 02:29:12 PM PDT 24
Finished Jun 09 02:29:18 PM PDT 24
Peak memory 216104 kb
Host smart-06c15e78-5626-419b-9c7b-4e357e0c8256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035207121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2035207121
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3552768397
Short name T318
Test name
Test status
Simulation time 64106142 ps
CPU time 2.91 seconds
Started Jun 09 02:29:08 PM PDT 24
Finished Jun 09 02:29:11 PM PDT 24
Peak memory 216092 kb
Host smart-80608460-7c2a-40d9-85bd-88ea0dad2bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552768397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3552768397
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.4136824122
Short name T736
Test name
Test status
Simulation time 29929131 ps
CPU time 0.85 seconds
Started Jun 09 02:29:03 PM PDT 24
Finished Jun 09 02:29:04 PM PDT 24
Peak memory 205604 kb
Host smart-3e1dd818-58a3-4bee-bced-833b6c7e0ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136824122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4136824122
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.276269582
Short name T717
Test name
Test status
Simulation time 10664046937 ps
CPU time 29.27 seconds
Started Jun 09 02:29:13 PM PDT 24
Finished Jun 09 02:29:42 PM PDT 24
Peak memory 224300 kb
Host smart-54e2efa3-7e68-4ba0-9496-1b5a9372ac15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276269582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.276269582
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.89337680
Short name T714
Test name
Test status
Simulation time 26548273 ps
CPU time 0.74 seconds
Started Jun 09 02:29:15 PM PDT 24
Finished Jun 09 02:29:16 PM PDT 24
Peak memory 205144 kb
Host smart-097b0757-cd60-4703-84b7-b95f3be89868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89337680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.89337680
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2087769777
Short name T78
Test name
Test status
Simulation time 96307225 ps
CPU time 3 seconds
Started Jun 09 02:29:01 PM PDT 24
Finished Jun 09 02:29:04 PM PDT 24
Peak memory 224352 kb
Host smart-114fa016-8e87-48d1-8c9d-6069ad147cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087769777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2087769777
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2429473646
Short name T523
Test name
Test status
Simulation time 28938058 ps
CPU time 0.74 seconds
Started Jun 09 02:29:15 PM PDT 24
Finished Jun 09 02:29:16 PM PDT 24
Peak memory 205204 kb
Host smart-bedb9a46-93fc-4806-839a-ef80ecd2049d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429473646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2429473646
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2338305608
Short name T162
Test name
Test status
Simulation time 12384100665 ps
CPU time 56.3 seconds
Started Jun 09 02:29:15 PM PDT 24
Finished Jun 09 02:30:12 PM PDT 24
Peak memory 254660 kb
Host smart-a97d386d-b262-4860-9871-501c1b72caa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338305608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2338305608
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1860114133
Short name T464
Test name
Test status
Simulation time 26229557126 ps
CPU time 49.08 seconds
Started Jun 09 02:29:03 PM PDT 24
Finished Jun 09 02:29:53 PM PDT 24
Peak memory 227208 kb
Host smart-5d495bf6-84b7-4862-982c-3dd05e3119e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860114133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1860114133
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1760686348
Short name T177
Test name
Test status
Simulation time 61891855177 ps
CPU time 628.95 seconds
Started Jun 09 02:29:01 PM PDT 24
Finished Jun 09 02:39:31 PM PDT 24
Peak memory 265140 kb
Host smart-46f708d2-1cd1-40d4-bae4-72d9a9049e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760686348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1760686348
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3546995970
Short name T488
Test name
Test status
Simulation time 364122635 ps
CPU time 6.36 seconds
Started Jun 09 02:29:05 PM PDT 24
Finished Jun 09 02:29:11 PM PDT 24
Peak memory 224324 kb
Host smart-26563dc8-bc78-4116-b96e-2508795e781a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546995970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3546995970
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2858243820
Short name T902
Test name
Test status
Simulation time 517071057 ps
CPU time 6.8 seconds
Started Jun 09 02:29:18 PM PDT 24
Finished Jun 09 02:29:25 PM PDT 24
Peak memory 224268 kb
Host smart-424152a5-558e-45af-9de3-ccff66ca9315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858243820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2858243820
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1707430294
Short name T543
Test name
Test status
Simulation time 5709907350 ps
CPU time 9.15 seconds
Started Jun 09 02:29:07 PM PDT 24
Finished Jun 09 02:29:17 PM PDT 24
Peak memory 240600 kb
Host smart-f4fed706-6e55-4786-9961-bc7fc241ceb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707430294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1707430294
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.146934300
Short name T785
Test name
Test status
Simulation time 52277705 ps
CPU time 1.07 seconds
Started Jun 09 02:29:15 PM PDT 24
Finished Jun 09 02:29:16 PM PDT 24
Peak memory 216360 kb
Host smart-4be1e7d9-b59f-4dc9-850b-370ee141379c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146934300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.146934300
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2953409944
Short name T196
Test name
Test status
Simulation time 1365997874 ps
CPU time 5.91 seconds
Started Jun 09 02:29:01 PM PDT 24
Finished Jun 09 02:29:08 PM PDT 24
Peak memory 232504 kb
Host smart-70400061-1668-4c69-a1dc-dabe58c16868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953409944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2953409944
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2440957463
Short name T81
Test name
Test status
Simulation time 11386173855 ps
CPU time 13.47 seconds
Started Jun 09 02:29:08 PM PDT 24
Finished Jun 09 02:29:27 PM PDT 24
Peak memory 224404 kb
Host smart-dfebb2cf-e787-4037-b645-e03f71299dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440957463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2440957463
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.203176571
Short name T962
Test name
Test status
Simulation time 19336818081 ps
CPU time 13.13 seconds
Started Jun 09 02:29:11 PM PDT 24
Finished Jun 09 02:29:25 PM PDT 24
Peak memory 219876 kb
Host smart-3668078d-8cbe-44a0-98af-770d2f9e049f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=203176571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.203176571
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1278869674
Short name T200
Test name
Test status
Simulation time 307249238935 ps
CPU time 591.88 seconds
Started Jun 09 02:29:27 PM PDT 24
Finished Jun 09 02:39:19 PM PDT 24
Peak memory 268452 kb
Host smart-0db5b84c-14ca-42dc-b955-069903e1140d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278869674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1278869674
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3692129371
Short name T696
Test name
Test status
Simulation time 35183264026 ps
CPU time 44.54 seconds
Started Jun 09 02:29:06 PM PDT 24
Finished Jun 09 02:29:51 PM PDT 24
Peak memory 216148 kb
Host smart-b74780ac-b47f-47d3-81ff-6415039675f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692129371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3692129371
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1920217421
Short name T803
Test name
Test status
Simulation time 1098131331 ps
CPU time 4.47 seconds
Started Jun 09 02:29:08 PM PDT 24
Finished Jun 09 02:29:13 PM PDT 24
Peak memory 216076 kb
Host smart-aa644c71-5900-475a-8b83-9bc75cb2ab23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920217421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1920217421
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1473589096
Short name T876
Test name
Test status
Simulation time 328490216 ps
CPU time 1.46 seconds
Started Jun 09 02:29:05 PM PDT 24
Finished Jun 09 02:29:07 PM PDT 24
Peak memory 216100 kb
Host smart-c8f5fc4d-2bec-4a4d-b58e-d00079feed65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473589096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1473589096
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1683760721
Short name T591
Test name
Test status
Simulation time 12533474 ps
CPU time 0.69 seconds
Started Jun 09 02:29:07 PM PDT 24
Finished Jun 09 02:29:08 PM PDT 24
Peak memory 205212 kb
Host smart-92c5ba23-1024-4a99-ac99-e7c3e0e9ed36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683760721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1683760721
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.509527986
Short name T950
Test name
Test status
Simulation time 422515993 ps
CPU time 3.77 seconds
Started Jun 09 02:29:10 PM PDT 24
Finished Jun 09 02:29:14 PM PDT 24
Peak memory 224268 kb
Host smart-4f120c0b-ce9e-4cfb-a1ff-72f685be7b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509527986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.509527986
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1569213687
Short name T54
Test name
Test status
Simulation time 13773658 ps
CPU time 0.71 seconds
Started Jun 09 02:29:07 PM PDT 24
Finished Jun 09 02:29:13 PM PDT 24
Peak memory 205512 kb
Host smart-492e7e44-b236-441f-894f-0a82dc17c35a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569213687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
569213687
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3525436241
Short name T461
Test name
Test status
Simulation time 551378388 ps
CPU time 2.83 seconds
Started Jun 09 02:29:07 PM PDT 24
Finished Jun 09 02:29:10 PM PDT 24
Peak memory 224280 kb
Host smart-8ac816ec-2588-4f25-a815-93c362b10e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525436241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3525436241
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3717410663
Short name T566
Test name
Test status
Simulation time 78521715 ps
CPU time 0.76 seconds
Started Jun 09 02:29:13 PM PDT 24
Finished Jun 09 02:29:14 PM PDT 24
Peak memory 206112 kb
Host smart-fef00236-c22c-4a5a-8d7e-8d757563a08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717410663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3717410663
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.4021329963
Short name T165
Test name
Test status
Simulation time 230627361767 ps
CPU time 387.29 seconds
Started Jun 09 02:29:12 PM PDT 24
Finished Jun 09 02:35:45 PM PDT 24
Peak memory 250940 kb
Host smart-94a4bfb4-1459-40bf-9da1-a63a16f0cb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021329963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.4021329963
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.4176011149
Short name T221
Test name
Test status
Simulation time 7727573166 ps
CPU time 73.44 seconds
Started Jun 09 02:29:05 PM PDT 24
Finished Jun 09 02:30:19 PM PDT 24
Peak memory 253800 kb
Host smart-c9941c74-4e18-4a91-963a-9419911fdebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176011149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.4176011149
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.140924101
Short name T176
Test name
Test status
Simulation time 39642683559 ps
CPU time 224.82 seconds
Started Jun 09 02:29:05 PM PDT 24
Finished Jun 09 02:32:50 PM PDT 24
Peak memory 253200 kb
Host smart-4d75d1b8-c7aa-4cb8-a47d-fec08ed29f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140924101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
140924101
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2235801209
Short name T313
Test name
Test status
Simulation time 3489070186 ps
CPU time 15.07 seconds
Started Jun 09 02:29:26 PM PDT 24
Finished Jun 09 02:29:41 PM PDT 24
Peak memory 233696 kb
Host smart-9303d82c-e876-4ceb-93cb-da4ae2f6737b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235801209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2235801209
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1257710934
Short name T431
Test name
Test status
Simulation time 7019974179 ps
CPU time 21.42 seconds
Started Jun 09 02:29:19 PM PDT 24
Finished Jun 09 02:29:41 PM PDT 24
Peak memory 232540 kb
Host smart-9da8ddb2-6b69-467d-b624-84469cc3a7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257710934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1257710934
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1258747291
Short name T478
Test name
Test status
Simulation time 1911699111 ps
CPU time 18.42 seconds
Started Jun 09 02:29:19 PM PDT 24
Finished Jun 09 02:29:38 PM PDT 24
Peak memory 232500 kb
Host smart-b1c90d0c-d0d7-406e-a245-ea818451888b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258747291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1258747291
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.4088623934
Short name T834
Test name
Test status
Simulation time 58805210 ps
CPU time 1.12 seconds
Started Jun 09 02:29:25 PM PDT 24
Finished Jun 09 02:29:26 PM PDT 24
Peak memory 216344 kb
Host smart-5ec596f2-c12c-4967-97bc-c0df75d4f419
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088623934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.4088623934
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.75778447
Short name T187
Test name
Test status
Simulation time 10289606276 ps
CPU time 10.75 seconds
Started Jun 09 02:29:07 PM PDT 24
Finished Jun 09 02:29:18 PM PDT 24
Peak memory 224348 kb
Host smart-bb06c489-f992-4313-9530-41c17f75a86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75778447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.75778447
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2488262104
Short name T263
Test name
Test status
Simulation time 974775562 ps
CPU time 7.1 seconds
Started Jun 09 02:29:17 PM PDT 24
Finished Jun 09 02:29:25 PM PDT 24
Peak memory 232472 kb
Host smart-189dd758-0f35-4ad5-887f-efbe820bd1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488262104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2488262104
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.216620750
Short name T562
Test name
Test status
Simulation time 269815312 ps
CPU time 4.03 seconds
Started Jun 09 02:29:08 PM PDT 24
Finished Jun 09 02:29:13 PM PDT 24
Peak memory 222328 kb
Host smart-4056e176-339d-4894-98ac-9a76222de3a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=216620750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.216620750
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1946379333
Short name T713
Test name
Test status
Simulation time 117272104284 ps
CPU time 345.98 seconds
Started Jun 09 02:29:15 PM PDT 24
Finished Jun 09 02:35:02 PM PDT 24
Peak memory 265456 kb
Host smart-62b5c868-fff1-40e2-8635-3fbd23dd09d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946379333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1946379333
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2778636266
Short name T749
Test name
Test status
Simulation time 9468006597 ps
CPU time 47.46 seconds
Started Jun 09 02:29:25 PM PDT 24
Finished Jun 09 02:30:13 PM PDT 24
Peak memory 216176 kb
Host smart-0f38d081-12b7-45e4-ba63-9e121105ac33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778636266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2778636266
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1004570627
Short name T769
Test name
Test status
Simulation time 1014987278 ps
CPU time 5.9 seconds
Started Jun 09 02:29:07 PM PDT 24
Finished Jun 09 02:29:13 PM PDT 24
Peak memory 216016 kb
Host smart-0d57320e-8a0e-46d3-9e83-88d97be1d0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004570627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1004570627
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2415247428
Short name T428
Test name
Test status
Simulation time 609779475 ps
CPU time 3.56 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:33 PM PDT 24
Peak memory 216092 kb
Host smart-8c0969be-1f92-4486-a5e7-c9030f2fcf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415247428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2415247428
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.255591478
Short name T367
Test name
Test status
Simulation time 63629933 ps
CPU time 0.67 seconds
Started Jun 09 02:29:13 PM PDT 24
Finished Jun 09 02:29:19 PM PDT 24
Peak memory 205252 kb
Host smart-a55711df-63d8-4a99-a5fe-40ba78868325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255591478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.255591478
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1220754140
Short name T887
Test name
Test status
Simulation time 869555781 ps
CPU time 5.05 seconds
Started Jun 09 02:29:06 PM PDT 24
Finished Jun 09 02:29:12 PM PDT 24
Peak memory 232500 kb
Host smart-734a624f-380d-45f2-bd0d-e81a5886c1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220754140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1220754140
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2637092177
Short name T891
Test name
Test status
Simulation time 13303553 ps
CPU time 0.73 seconds
Started Jun 09 02:29:07 PM PDT 24
Finished Jun 09 02:29:08 PM PDT 24
Peak memory 205172 kb
Host smart-53a9744c-eff9-4072-ac8b-211c580eb674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637092177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
637092177
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2618295507
Short name T862
Test name
Test status
Simulation time 1165564814 ps
CPU time 13.41 seconds
Started Jun 09 02:29:09 PM PDT 24
Finished Jun 09 02:29:23 PM PDT 24
Peak memory 232444 kb
Host smart-87288c43-75f1-49d8-a18a-6f9860085385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618295507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2618295507
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2989665489
Short name T661
Test name
Test status
Simulation time 14709855 ps
CPU time 0.79 seconds
Started Jun 09 02:29:31 PM PDT 24
Finished Jun 09 02:29:32 PM PDT 24
Peak memory 206232 kb
Host smart-c24a37a1-6a27-4c77-a65b-f820eb4afc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989665489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2989665489
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1995991038
Short name T235
Test name
Test status
Simulation time 20154553102 ps
CPU time 81.37 seconds
Started Jun 09 02:29:20 PM PDT 24
Finished Jun 09 02:30:41 PM PDT 24
Peak memory 248920 kb
Host smart-61b0d392-924b-45f8-b737-0fc63db4e8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995991038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1995991038
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2128163795
Short name T349
Test name
Test status
Simulation time 22728954055 ps
CPU time 112.22 seconds
Started Jun 09 02:29:11 PM PDT 24
Finished Jun 09 02:31:03 PM PDT 24
Peak memory 249004 kb
Host smart-7575b33c-50e1-40a9-8663-1f0236c0e9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128163795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2128163795
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.806522962
Short name T191
Test name
Test status
Simulation time 156373932398 ps
CPU time 321.85 seconds
Started Jun 09 02:29:27 PM PDT 24
Finished Jun 09 02:34:49 PM PDT 24
Peak memory 255000 kb
Host smart-ca86d8ed-7d08-4d42-a7d6-2bbdda95610c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806522962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
806522962
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2165010434
Short name T842
Test name
Test status
Simulation time 121062577 ps
CPU time 2.84 seconds
Started Jun 09 02:29:08 PM PDT 24
Finished Jun 09 02:29:12 PM PDT 24
Peak memory 224524 kb
Host smart-a83bc95d-a5c3-4a0c-af86-393e4ea9d171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165010434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2165010434
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2552862250
Short name T739
Test name
Test status
Simulation time 7620666364 ps
CPU time 15.89 seconds
Started Jun 09 02:29:09 PM PDT 24
Finished Jun 09 02:29:25 PM PDT 24
Peak memory 232604 kb
Host smart-b65b4535-c144-4a43-a4e4-a952a55e50b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552862250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2552862250
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1892251679
Short name T76
Test name
Test status
Simulation time 1189413187 ps
CPU time 14.53 seconds
Started Jun 09 02:29:12 PM PDT 24
Finished Jun 09 02:29:27 PM PDT 24
Peak memory 240640 kb
Host smart-886ad3ba-53e7-4cdc-9b9a-c91c92ed3930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892251679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1892251679
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.736014323
Short name T563
Test name
Test status
Simulation time 56966363 ps
CPU time 1.02 seconds
Started Jun 09 02:29:19 PM PDT 24
Finished Jun 09 02:29:21 PM PDT 24
Peak memory 217628 kb
Host smart-8e254edd-7319-407c-818e-d0df37c586b1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736014323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.736014323
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2120620510
Short name T218
Test name
Test status
Simulation time 5931767921 ps
CPU time 19.95 seconds
Started Jun 09 02:29:09 PM PDT 24
Finished Jun 09 02:29:29 PM PDT 24
Peak memory 232592 kb
Host smart-ff25ef4c-93d6-4d32-80d2-6f76a3fd44c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120620510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2120620510
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1052522845
Short name T757
Test name
Test status
Simulation time 337353277 ps
CPU time 4.13 seconds
Started Jun 09 02:29:11 PM PDT 24
Finished Jun 09 02:29:15 PM PDT 24
Peak memory 222788 kb
Host smart-2c60570b-346e-4e66-909a-aa47eae2a76b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1052522845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1052522845
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1294031042
Short name T928
Test name
Test status
Simulation time 14964278481 ps
CPU time 29.23 seconds
Started Jun 09 02:29:11 PM PDT 24
Finished Jun 09 02:29:41 PM PDT 24
Peak memory 216164 kb
Host smart-52c39425-f6c2-421b-b199-6fcf2aa22c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294031042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1294031042
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.378671140
Short name T382
Test name
Test status
Simulation time 1566798584 ps
CPU time 5.08 seconds
Started Jun 09 02:29:15 PM PDT 24
Finished Jun 09 02:29:21 PM PDT 24
Peak memory 216028 kb
Host smart-4bdb081a-1759-401f-b130-fcb3d878b07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378671140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.378671140
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.340397029
Short name T416
Test name
Test status
Simulation time 113007625 ps
CPU time 3.74 seconds
Started Jun 09 02:29:07 PM PDT 24
Finished Jun 09 02:29:11 PM PDT 24
Peak memory 216048 kb
Host smart-d41b133f-cbbd-4c69-9b19-10323232d8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340397029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.340397029
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2496188114
Short name T793
Test name
Test status
Simulation time 40287516 ps
CPU time 0.81 seconds
Started Jun 09 02:29:14 PM PDT 24
Finished Jun 09 02:29:15 PM PDT 24
Peak memory 205936 kb
Host smart-6d2c85f9-fd4e-48b2-a3d2-a3af7e1361a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496188114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2496188114
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.449202432
Short name T261
Test name
Test status
Simulation time 1827183237 ps
CPU time 6.04 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:36 PM PDT 24
Peak memory 224296 kb
Host smart-7154820c-c822-4f9d-b96f-c9fbd4fbbbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449202432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.449202432
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4244215898
Short name T847
Test name
Test status
Simulation time 37249444 ps
CPU time 0.73 seconds
Started Jun 09 02:29:14 PM PDT 24
Finished Jun 09 02:29:15 PM PDT 24
Peak memory 205192 kb
Host smart-2ccbdbdb-7464-43c6-a67e-07b4bfc08158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244215898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
244215898
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.4185685208
Short name T472
Test name
Test status
Simulation time 103402309 ps
CPU time 1.91 seconds
Started Jun 09 02:29:28 PM PDT 24
Finished Jun 09 02:29:31 PM PDT 24
Peak memory 223016 kb
Host smart-8c0c3731-6dec-4f67-b91b-b3e31bdb8ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185685208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.4185685208
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3760085168
Short name T860
Test name
Test status
Simulation time 79627974 ps
CPU time 0.73 seconds
Started Jun 09 02:29:08 PM PDT 24
Finished Jun 09 02:29:10 PM PDT 24
Peak memory 205208 kb
Host smart-445efe1d-cf81-43f5-b991-9f173c9407a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760085168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3760085168
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3457346406
Short name T32
Test name
Test status
Simulation time 213629937311 ps
CPU time 381.57 seconds
Started Jun 09 02:29:21 PM PDT 24
Finished Jun 09 02:35:43 PM PDT 24
Peak memory 254228 kb
Host smart-c3952f51-2542-466c-a925-c98b4d450fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457346406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3457346406
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3935732079
Short name T226
Test name
Test status
Simulation time 25767988865 ps
CPU time 98.51 seconds
Started Jun 09 02:29:19 PM PDT 24
Finished Jun 09 02:30:58 PM PDT 24
Peak memory 250776 kb
Host smart-8725b930-0272-4ad2-bd10-fe37fd8fecbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935732079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3935732079
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3866319255
Short name T13
Test name
Test status
Simulation time 20242387295 ps
CPU time 46.59 seconds
Started Jun 09 02:29:11 PM PDT 24
Finished Jun 09 02:29:58 PM PDT 24
Peak memory 235504 kb
Host smart-bbbb9c68-a20b-4307-84a4-8ae8aa0bf437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866319255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3866319255
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4203732426
Short name T288
Test name
Test status
Simulation time 2379106665 ps
CPU time 20.3 seconds
Started Jun 09 02:29:16 PM PDT 24
Finished Jun 09 02:29:36 PM PDT 24
Peak memory 234804 kb
Host smart-eba935b9-3164-49fa-8ba2-1eb6f106fa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203732426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4203732426
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3760325476
Short name T253
Test name
Test status
Simulation time 5943481952 ps
CPU time 39.8 seconds
Started Jun 09 02:29:12 PM PDT 24
Finished Jun 09 02:29:52 PM PDT 24
Peak memory 224368 kb
Host smart-47255413-4a9b-482a-bc88-792f76b858f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760325476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3760325476
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2688983979
Short name T624
Test name
Test status
Simulation time 327410999 ps
CPU time 6.51 seconds
Started Jun 09 02:29:14 PM PDT 24
Finished Jun 09 02:29:21 PM PDT 24
Peak memory 224320 kb
Host smart-63c56ef6-de16-4b77-bff5-0a49abddd216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688983979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2688983979
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3612908679
Short name T335
Test name
Test status
Simulation time 25129936 ps
CPU time 0.98 seconds
Started Jun 09 02:29:10 PM PDT 24
Finished Jun 09 02:29:11 PM PDT 24
Peak memory 216376 kb
Host smart-61294aea-d959-4a8f-a6cd-b74b376c1d60
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612908679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3612908679
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1746965145
Short name T274
Test name
Test status
Simulation time 940467623 ps
CPU time 7.56 seconds
Started Jun 09 02:29:28 PM PDT 24
Finished Jun 09 02:29:36 PM PDT 24
Peak memory 240592 kb
Host smart-f15bccf3-b82b-4ea9-8176-f5e2ebcbf702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746965145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1746965145
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3819652656
Short name T786
Test name
Test status
Simulation time 7387222241 ps
CPU time 7.84 seconds
Started Jun 09 02:29:17 PM PDT 24
Finished Jun 09 02:29:25 PM PDT 24
Peak memory 224308 kb
Host smart-c324f064-6025-4679-8bad-ec8e26c971f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819652656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3819652656
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.117536649
Short name T559
Test name
Test status
Simulation time 156901553 ps
CPU time 4.05 seconds
Started Jun 09 02:29:14 PM PDT 24
Finished Jun 09 02:29:18 PM PDT 24
Peak memory 222784 kb
Host smart-6e9e5f2f-25e6-427b-b620-ddb2dde6c2ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=117536649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.117536649
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2516276564
Short name T465
Test name
Test status
Simulation time 41673660555 ps
CPU time 114.62 seconds
Started Jun 09 02:29:23 PM PDT 24
Finished Jun 09 02:31:18 PM PDT 24
Peak memory 253104 kb
Host smart-c7d11b9b-892d-4e9f-9335-611615c56468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516276564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2516276564
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4094104940
Short name T508
Test name
Test status
Simulation time 19597682167 ps
CPU time 31.71 seconds
Started Jun 09 02:29:10 PM PDT 24
Finished Jun 09 02:29:42 PM PDT 24
Peak memory 216256 kb
Host smart-b71d8d44-d87b-4ff7-ba53-3a2934f01c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094104940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4094104940
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2747539960
Short name T460
Test name
Test status
Simulation time 815623159 ps
CPU time 1.59 seconds
Started Jun 09 02:29:12 PM PDT 24
Finished Jun 09 02:29:14 PM PDT 24
Peak memory 207672 kb
Host smart-04328372-0f44-41a0-a970-3c815d451836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747539960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2747539960
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3098782895
Short name T520
Test name
Test status
Simulation time 552838824 ps
CPU time 1.89 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:32 PM PDT 24
Peak memory 216120 kb
Host smart-d1399999-8bda-4af7-be20-c9ef59e4c8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098782895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3098782895
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.778185744
Short name T308
Test name
Test status
Simulation time 93118816 ps
CPU time 0.99 seconds
Started Jun 09 02:29:09 PM PDT 24
Finished Jun 09 02:29:11 PM PDT 24
Peak memory 205608 kb
Host smart-691c55fd-6d2d-44c6-b92b-65cf483eece9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778185744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.778185744
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.4088353014
Short name T700
Test name
Test status
Simulation time 32709476909 ps
CPU time 25.14 seconds
Started Jun 09 02:29:13 PM PDT 24
Finished Jun 09 02:29:38 PM PDT 24
Peak memory 250460 kb
Host smart-690f6983-a20d-482b-b2d6-9cb3937ba0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088353014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4088353014
Directory /workspace/9.spi_device_upload/latest
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