Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2480525	1			T2	32711		T3	1336		T4	2275
all_values[1]	2480525	1			T2	32711		T3	1336		T4	2275
all_values[2]	2480525	1			T2	32711		T3	1336		T4	2275
all_values[3]	2480525	1			T2	32711		T3	1336		T4	2275
all_values[4]	2480525	1			T2	32711		T3	1336		T4	2275
all_values[5]	2480525	1			T2	32711		T3	1336		T4	2275
all_values[6]	2480525	1			T2	32711		T3	1336		T4	2275
all_values[7]	2480525	1			T2	32711		T3	1336		T4	2275

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19192788

1

T2

261688

T3

10688

T4

18200

auto[1]

651412

1

T17

37

T19

43

T20

89

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19823251

1

T2

261379

T3

10668

T4

18200

auto[1]

20949

1

T2

309

T3

20

T7

3

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2385927	1			T2	32450		T3	1322		T4	2275
all_values[0]	auto[0]	auto[1]	10931	1			T2	261		T3	14		T8	1
all_values[0]	auto[1]	auto[0]	83472	1			T17	4		T19	4		T20	9
all_values[0]	auto[1]	auto[1]	195	1			T17	3		T19	1		T20	7
all_values[1]	auto[0]	auto[0]	2344612	1			T2	32687		T3	1333		T4	2275
all_values[1]	auto[0]	auto[1]	5436	1			T2	24		T3	3		T9	68
all_values[1]	auto[1]	auto[0]	130207	1			T17	3		T19	6		T20	6
all_values[1]	auto[1]	auto[1]	270	1			T17	2		T19	1		T20	5
all_values[2]	auto[0]	auto[0]	2478050	1			T2	32687		T3	1333		T4	2275
all_values[2]	auto[0]	auto[1]	1988	1			T2	24		T3	3		T9	9
all_values[2]	auto[1]	auto[0]	295	1			T19	6		T20	6		T21	8
all_values[2]	auto[1]	auto[1]	192	1			T17	3		T20	6		T21	3
all_values[3]	auto[0]	auto[0]	2394170	1			T2	32711		T3	1336		T4	2275
all_values[3]	auto[0]	auto[1]	224	1			T17	1		T19	2		T20	4
all_values[3]	auto[1]	auto[0]	85953	1			T17	6		T19	1		T20	5
all_values[3]	auto[1]	auto[1]	178	1			T17	1		T20	5		T21	1
all_values[4]	auto[0]	auto[0]	2339171	1			T2	32711		T3	1336		T4	2275
all_values[4]	auto[0]	auto[1]	193	1			T17	2		T19	2		T20	5
all_values[4]	auto[1]	auto[0]	140986	1			T17	2		T19	5		T20	5
all_values[4]	auto[1]	auto[1]	175	1			T17	4		T19	1		T20	4
all_values[5]	auto[0]	auto[0]	2435042	1			T2	32711		T3	1336		T4	2275
all_values[5]	auto[0]	auto[1]	276	1			T7	3		T71	5		T169	8
all_values[5]	auto[1]	auto[0]	45048	1			T17	1		T19	4		T20	7
all_values[5]	auto[1]	auto[1]	159	1			T17	2		T19	4		T20	3
all_values[6]	auto[0]	auto[0]	2425081	1			T2	32711		T3	1336		T4	2275
all_values[6]	auto[0]	auto[1]	190	1			T17	2		T19	2		T20	2
all_values[6]	auto[1]	auto[0]	55094	1			T17	2		T19	1		T20	8
all_values[6]	auto[1]	auto[1]	160	1			T19	2		T20	1		T21	2
all_values[7]	auto[0]	auto[0]	2371319	1			T2	32711		T3	1336		T4	2275
all_values[7]	auto[0]	auto[1]	178	1			T19	2		T20	3		T21	1
all_values[7]	auto[1]	auto[0]	108824	1			T17	4		T19	4		T20	11
all_values[7]	auto[1]	auto[1]	204	1			T19	3		T20	1		T21	5