Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	28974	1			T2	105		T3	23		T6	6
auto[SpiFlashAddrCfg]	6144	1			T2	31		T3	7		T8	23
auto[SpiFlashAddr3b]	7512	1			T2	38		T3	1		T8	22
auto[SpiFlashAddr4b]	6392	1			T2	34		T3	5		T6	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28022

1

T2

143

T3

14

T6

8

auto[1]

21000

1

T2

65

T3

22

T8

99

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27140

1

T2

121

T3

10

T6

6

auto[1]

21882

1

T2

87

T3

26

T6

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	32663	1			T2	121		T3	29		T6	6
values[1]	882	1			T2	6		T8	3		T9	10
values[2]	1164	1			T2	9		T8	13		T9	4
values[3]	1244	1			T2	5		T3	2		T8	1
values[4]	1185	1			T2	3		T8	3		T9	9
values[5]	1176	1			T2	2		T3	2		T8	4
values[6]	1161	1			T2	12		T8	4		T9	7
values[7]	1317	1			T2	10		T8	6		T9	16
values[8]	8230	1			T2	40		T3	3		T6	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T3

36

T6

8

T8

145

auto[1]

26314

1

T2

208

T10

401

T12

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

47287

1

T2

200

T3

33

T6

8

write

1735

1

T2

8

T3

3

T8

3

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16571

1

T2

89

T3

16

T6

2

valids[0x1]

32451

1

T2

119

T3

20

T6

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1378	1			T2	5		T8	5		T9	10
internal_process_ops[0x5a]	1286	1			T2	8		T8	3		T9	4
internal_process_ops[0x05]	17078	1			T2	35		T3	16		T8	49
internal_process_ops[0x35]	1357	1			T2	5		T3	1		T6	4
internal_process_ops[0x15]	1311	1			T2	7		T6	2		T8	8
internal_process_ops[0x03]	846	1			T2	2		T6	2		T8	3
internal_process_ops[0x0b]	794	1			T2	1		T8	2		T9	9
internal_process_ops[0x3b]	811	1			T2	2		T8	2		T9	9
internal_process_ops[0x6b]	904	1			T2	1		T8	2		T9	7
internal_process_ops[0xbb]	853	1			T2	4		T8	3		T9	3
internal_process_ops[0xeb]	882	1			T2	1		T3	1		T8	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48120

1

T2

201

T3

34

T6

8

auto[1]

902

1

T2

7

T3

2

T8

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47358

1

T2

194

T3

31

T6

8

auto[1]

1664

1

T2

14

T3

5

T8

3

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7696

1

T3

7

T6

6

T8

17

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4728

1

T3

16

T8

59

T9

31

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1615

1

T3

1

T8

6

T9

36

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1379

1

T3

3

T8

16

T9

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1891

1

T8

11

T9

19

T14

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1639

1

T3

1

T8

11

T9

33

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1594

1

T3

5

T6

2

T8

11

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1413

1

T8

11

T9

21

T15

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

56

1

T41

1

T45

2

T157

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

49

1

T42

1

T122

2

T52

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

27

1

T9

2

T46

2

T52

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

44

1

T41

2

T46

1

T49

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

38

1

T3

1

T41

1

T42

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

60

1

T8

1

T9

2

T41

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

52

1

T41

1

T19

3

T49

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

61

1

T3

2

T44

1

T46

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

51

1

T41

1

T46

4

T122

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

45

1

T41

1

T45

3

T46

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

39

1

T9

3

T42

2

T122

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

63

1

T44

1

T46

1

T47

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

54

1

T41

1

T43

1

T165

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

33

1

T42

1

T46

2

T19

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

41

1

T8

2

T41

1

T46

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

40

1

T44

2

T19

1

T166

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9712

1

T2

87

T10

86

T16

265

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6405

1

T2

16

T10

179

T16

241

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1363

1

T2

20

T10

41

T16

24

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1352

1

T2

8

T10

12

T16

28

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1736

1

T2

19

T10

21

T16

38

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1791

1

T2

19

T10

12

T16

26

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1511

1

T2

14

T10

28

T12

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1462

1

T2

17

T10

9

T16

35

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

66

1

T72

3

T20

1

T167

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

73

1

T2

1

T16

2

T20

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

38

1

T16

5

T18

3

T167

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

80

1

T2

1

T72

1

T20

7

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

55

1

T158

1

T72

2

T167

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

50

1

T2

2

T10

1

T167

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

60

1

T2

1

T10

2

T16

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

59

1

T16

2

T26

1

T158

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

72

1

T10

3

T16

3

T26

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

67

1

T10

4

T168

1

T72

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

61

1

T10

1

T16

1

T26

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

57

1

T16

4

T72

1

T18

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

61

1

T10

1

T72

3

T20

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

74

1

T10

1

T16

1

T72

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

62

1

T16

6

T72

1

T167

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

47

1

T2

3

T16

2

T158

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3207	1			T3	9		T8	11		T9	41
auto[0]	values[0]	valids[0x1]	11220	1			T3	20		T6	6		T8	75
auto[0]	values[1]	valids[0x1]	431	1			T8	3		T9	10		T41	4
auto[0]	values[2]	valids[0x0]	357	1			T8	7		T9	4		T15	2
auto[0]	values[2]	valids[0x1]	214	1			T8	6		T41	4		T24	2
auto[0]	values[3]	valids[0x0]	440	1			T3	2		T8	1		T41	12
auto[0]	values[3]	valids[0x1]	199	1			T41	2		T43	1		T42	3
auto[0]	values[4]	valids[0x0]	388	1			T8	2		T9	6		T41	6
auto[0]	values[4]	valids[0x1]	215	1			T8	1		T9	3		T15	2
auto[0]	values[5]	valids[0x0]	388	1			T3	2		T8	2		T9	5
auto[0]	values[5]	valids[0x1]	205	1			T8	2		T9	4		T41	2
auto[0]	values[6]	valids[0x0]	374	1			T8	3		T9	5		T41	7
auto[0]	values[6]	valids[0x1]	200	1			T8	1		T9	2		T41	1
auto[0]	values[7]	valids[0x0]	437	1			T8	6		T9	10		T41	2
auto[0]	values[7]	valids[0x1]	266	1			T9	6		T41	2		T33	4
auto[0]	values[8]	valids[0x0]	2690	1			T3	3		T6	2		T8	15
auto[0]	values[8]	valids[0x1]	1477	1			T8	10		T9	25		T15	2
auto[1]	values[0]	valids[0x0]	3848	1			T2	50		T10	69		T16	70
auto[1]	values[0]	valids[0x1]	14388	1			T2	71		T10	214		T12	1
auto[1]	values[1]	valids[0x1]	451	1			T2	6		T10	3		T16	19
auto[1]	values[2]	valids[0x0]	309	1			T2	4		T10	3		T16	10
auto[1]	values[2]	valids[0x1]	284	1			T2	5		T10	6		T16	6
auto[1]	values[3]	valids[0x0]	354	1			T2	2		T10	3		T16	4
auto[1]	values[3]	valids[0x1]	251	1			T2	3		T10	5		T16	6
auto[1]	values[4]	valids[0x0]	347	1			T2	2		T10	7		T16	15
auto[1]	values[4]	valids[0x1]	235	1			T2	1		T10	4		T12	1
auto[1]	values[5]	valids[0x0]	354	1			T2	1		T10	4		T16	2
auto[1]	values[5]	valids[0x1]	229	1			T2	1		T10	5		T26	6
auto[1]	values[6]	valids[0x0]	359	1			T2	5		T10	1		T16	5
auto[1]	values[6]	valids[0x1]	228	1			T2	7		T10	4		T16	5
auto[1]	values[7]	valids[0x0]	370	1			T2	4		T10	3		T16	13
auto[1]	values[7]	valids[0x1]	244	1			T2	6		T10	3		T16	3
auto[1]	values[8]	valids[0x0]	2349	1			T2	21		T10	33		T16	53
auto[1]	values[8]	valids[0x1]	1714	1			T2	19		T10	34		T16	24