Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3078979

1

T2

6286

T3

18

T6

5623

auto[1]

15718

1

T2

28

T3

16

T8

45

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

999801

1

T2

67

T3

15

T6

1

auto[1]

2094896

1

T2

6247

T3

19

T6

5622

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	561200	1			T2	21		T3	24		T6	5623
auto[524288:1048575]	284254	1			T2	662		T8	1747		T9	2301
auto[1048576:1572863]	390546	1			T2	4		T3	1		T8	146
auto[1572864:2097151]	337627	1			T2	271		T9	270		T10	453
auto[2097152:2621439]	421293	1			T2	176		T9	6732		T10	2137
auto[2621440:3145727]	395542	1			T2	859		T3	4		T8	258
auto[3145728:3670015]	340835	1			T2	3916		T8	2695		T9	14
auto[3670016:4194303]	363400	1			T2	405		T3	5		T8	515

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2113078

1

T2

6312

T3

34

T6

5623

auto[1]

981619

1

T2

2

T8

2

T9

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2683333

1

T2

5880

T3

4

T6

5623

auto[1]

411364

1

T2

434

T3

30

T8

136

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	204245	1			T2	4		T6	1		T8	4
auto[0]	auto[0]	auto[0:524287]	auto[1]	303763	1			T2	1		T6	5622		T8	522
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	62837	1			T2	6		T8	1		T9	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	172290	1			T2	642		T8	1746		T9	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	132273	1			T2	1		T8	3		T9	6
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	211855	1			T2	2		T8	133		T9	261
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	70958	1			T2	4		T9	6		T10	10
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	218491	1			T2	1		T9	256		T10	436
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	157228	1			T2	2		T9	9		T10	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	193153	1			T2	174		T9	3485		T10	2019
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	142097	1			T2	4		T8	2		T9	8
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	191652	1			T2	851		T8	256		T9	387
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	129036	1			T2	5		T8	11		T10	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	173851	1			T2	3902		T8	2683		T10	128
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	92004	1			T2	6		T3	1		T8	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	215193	1			T2	257		T3	3		T8	512
auto[0]	auto[1]	auto[0:524287]	auto[0]	1157	1			T2	4		T3	6		T8	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	49503	1			T2	5		T3	4		T8	133
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	479	1			T2	2		T9	6		T10	10
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	46931	1			T2	5		T9	2288		T10	134
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1106	1			T2	1		T3	1		T10	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	42866	1			T41	3		T42	1		T46	1924
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	745	1			T2	4		T9	3		T41	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	45654	1			T2	258		T9	5		T41	2024
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	934	1			T9	3		T10	1		T41	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	68057	1			T9	3224		T10	105		T41	1025
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	673	1			T2	3		T3	1		T10	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	59274	1			T3	1		T9	4		T10	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1193	1			T9	4		T10	3		T16	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	34989	1			T2	5		T9	2		T10	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1170	1			T2	7		T3	1		T10	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	53322	1			T2	130		T10	3341		T16	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	201	1			T2	1		T8	1		T10	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2002	1			T2	2		T8	33		T41	7
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	175	1			T2	2		T9	1		T10	5
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1088	1			T2	5		T9	1		T10	69
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	176	1			T8	1		T9	1		T10	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1757	1			T8	9		T9	5		T10	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	138	1			T2	1		T10	1		T16	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1182	1			T10	6		T16	99		T26	9
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	159	1			T9	2		T10	1		T41	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1202	1			T9	9		T10	6		T41	50
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	145	1			T2	1		T9	3		T44	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1266	1			T9	4		T44	6		T158	9
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	160	1			T2	2		T8	1		T41	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1340	1			T2	2		T41	16		T16	43
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	178	1			T2	1		T9	1		T10	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1238	1			T2	1		T9	4		T10	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	43	1			T2	2		T3	4		T16	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	286	1			T2	2		T3	10		T16	29
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	42	1			T9	1		T10	8		T45	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	412	1			T9	1		T10	56		T21	63
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	41	1			T42	1		T19	1		T20	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	472	1			T42	26		T19	6		T20	29
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	45	1			T2	2		T42	1		T158	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	414	1			T2	1		T42	24		T158	7
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	41	1			T41	1		T26	1		T20	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	519	1			T41	22		T26	41		T20	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	39	1			T3	1		T46	1		T158	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	396	1			T3	1		T46	52		T158	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	41	1			T9	2		T10	1		T45	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	225	1			T9	6		T10	3		T45	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	42	1			T2	2		T16	1		T45	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	253	1			T2	1		T16	6		T45	11

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1694817	1			T2	5862		T3	4		T6	5623
auto[0]	auto[0]	auto[1]	976109	1			T8	2		T10	2		T12	605
auto[0]	auto[1]	auto[0]	402808	1			T2	424		T3	14		T8	136
auto[0]	auto[1]	auto[1]	5245	1			T9	1		T41	1		T72	4
auto[1]	auto[0]	auto[0]	12191	1			T2	17		T8	45		T9	31
auto[1]	auto[0]	auto[1]	216	1			T2	1		T42	2		T44	2
auto[1]	auto[1]	auto[0]	3262	1			T2	9		T3	16		T9	10
auto[1]	auto[1]	auto[1]	49	1			T2	1		T10	1		T46	1