Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13182

1

T3

14

T6

8

T8

46

auto[1]

9526

1

T3

22

T8

99

T9

96

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2737	1			T8	20		T9	74		T14	2
values[1]	3052	1			T42	47		T44	143		T45	36
values[2]	2907	1			T9	28		T13	28		T41	40
values[3]	2344	1			T8	64		T41	20		T35	2
values[4]	2822	1			T8	41		T9	25		T41	98
values[5]	3289	1			T3	36		T6	8		T8	20
values[6]	3091	1			T9	21		T41	20		T24	8
values[7]	2466	1			T9	73		T41	67		T239	14

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3555	1			T9	28		T41	63		T43	42
values[1]	2148	1			T8	20		T15	8		T41	56
values[2]	2804	1			T9	47		T41	40		T42	40
values[3]	2204	1			T9	25		T24	8		T138	2
values[4]	3017	1			T6	8		T8	61		T9	26
values[5]	2829	1			T9	75		T14	2		T41	20
values[6]	3054	1			T9	20		T41	95		T35	2
values[7]	3097	1			T3	36		T8	64		T9	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	218	1			T43	11		T182	27		T188	19
auto[0]	values[0]	values[1]	76	1			T122	11		T198	8		T221	10
auto[0]	values[0]	values[2]	231	1			T9	11		T44	11		T45	19
auto[0]	values[0]	values[3]	91	1			T138	2		T19	10		T52	16
auto[0]	values[0]	values[4]	283	1			T8	8		T9	17		T41	42
auto[0]	values[0]	values[5]	393	1			T9	15		T14	2		T41	14
auto[0]	values[0]	values[6]	163	1			T41	13		T240	2		T31	11
auto[0]	values[0]	values[7]	135	1			T241	58		T152	13		T242	9
auto[0]	values[1]	values[0]	258	1			T44	91		T21	5		T224	73
auto[0]	values[1]	values[1]	196	1			T65	11		T226	15		T243	20
auto[0]	values[1]	values[2]	203	1			T122	6		T49	14		T244	4
auto[0]	values[1]	values[3]	144	1			T42	14		T245	6		T216	12
auto[0]	values[1]	values[4]	238	1			T157	8		T19	25		T166	37
auto[0]	values[1]	values[5]	252	1			T42	14		T52	14		T246	10
auto[0]	values[1]	values[6]	182	1			T44	17		T45	8		T46	14
auto[0]	values[1]	values[7]	278	1			T46	9		T200	14		T247	17
auto[0]	values[2]	values[0]	169	1			T9	19		T41	5		T186	18
auto[0]	values[2]	values[1]	129	1			T46	15		T19	16		T222	15
auto[0]	values[2]	values[2]	250	1			T42	5		T182	13		T197	18
auto[0]	values[2]	values[3]	172	1			T248	20		T249	4		T250	2
auto[0]	values[2]	values[4]	309	1			T13	28		T19	13		T182	10
auto[0]	values[2]	values[5]	196	1			T42	8		T251	16		T49	19
auto[0]	values[2]	values[6]	187	1			T160	2		T222	14		T36	14
auto[0]	values[2]	values[7]	327	1			T41	5		T52	13		T123	11
auto[0]	values[3]	values[0]	280	1			T43	9		T46	16		T19	12
auto[0]	values[3]	values[1]	103	1			T139	6		T166	16		T252	2
auto[0]	values[3]	values[2]	64	1			T41	16		T187	16		T253	2
auto[0]	values[3]	values[3]	137	1			T166	10		T186	15		T207	13
auto[0]	values[3]	values[4]	223	1			T46	12		T49	11		T52	9
auto[0]	values[3]	values[5]	95	1			T122	10		T254	2		T255	6
auto[0]	values[3]	values[6]	220	1			T35	2		T79	6		T256	10
auto[0]	values[3]	values[7]	271	1			T8	4		T45	12		T49	8
auto[0]	values[4]	values[0]	196	1			T41	12		T45	14		T21	15
auto[0]	values[4]	values[1]	192	1			T42	11		T52	44		T201	9
auto[0]	values[4]	values[2]	212	1			T188	25		T257	4		T185	11
auto[0]	values[4]	values[3]	130	1			T9	20		T258	8		T31	3
auto[0]	values[4]	values[4]	179	1			T8	22		T42	15		T46	12
auto[0]	values[4]	values[5]	120	1			T42	8		T259	10		T260	2
auto[0]	values[4]	values[6]	372	1			T41	13		T45	7		T21	8
auto[0]	values[4]	values[7]	130	1			T84	8		T46	13		T122	7
auto[0]	values[5]	values[0]	403	1			T80	8		T21	12		T261	6
auto[0]	values[5]	values[1]	260	1			T8	12		T41	37		T65	11
auto[0]	values[5]	values[2]	101	1			T19	40		T262	10		T263	12
auto[0]	values[5]	values[3]	174	1			T178	6		T19	8		T21	13
auto[0]	values[5]	values[4]	170	1			T6	8		T42	9		T46	7
auto[0]	values[5]	values[5]	218	1			T44	75		T21	22		T36	10
auto[0]	values[5]	values[6]	354	1			T9	10		T44	31		T46	68
auto[0]	values[5]	values[7]	378	1			T3	14		T42	9		T122	14
auto[0]	values[6]	values[0]	249	1			T44	14		T182	11		T36	16
auto[0]	values[6]	values[1]	171	1			T21	11		T31	20		T230	11
auto[0]	values[6]	values[2]	317	1			T9	9		T41	15		T264	2
auto[0]	values[6]	values[3]	159	1			T21	12		T199	13		T200	15
auto[0]	values[6]	values[4]	320	1			T265	2		T49	14		T21	8
auto[0]	values[6]	values[5]	135	1			T42	8		T46	6		T52	15
auto[0]	values[6]	values[6]	197	1			T42	46		T182	11		T234	22
auto[0]	values[6]	values[7]	57	1			T21	8		T201	10		T124	12
auto[0]	values[7]	values[0]	228	1			T50	6		T266	36		T123	14
auto[0]	values[7]	values[1]	130	1			T44	12		T179	22		T238	6
auto[0]	values[7]	values[2]	288	1			T42	8		T46	50		T155	12
auto[0]	values[7]	values[3]	250	1			T267	12		T49	13		T268	16
auto[0]	values[7]	values[4]	149	1			T41	28		T239	14		T19	13
auto[0]	values[7]	values[5]	109	1			T9	34		T269	2		T222	10
auto[0]	values[7]	values[6]	209	1			T41	12		T270	12		T182	12
auto[0]	values[7]	values[7]	152	1			T9	10		T271	14		T272	6
auto[1]	values[0]	values[0]	179	1			T43	11		T182	8		T188	32
auto[1]	values[0]	values[1]	98	1			T122	33		T221	11		T273	9
auto[1]	values[0]	values[2]	164	1			T9	15		T44	9		T45	7
auto[1]	values[0]	values[3]	107	1			T19	10		T52	9		T21	12
auto[1]	values[0]	values[4]	162	1			T8	12		T9	9		T41	4
auto[1]	values[0]	values[5]	107	1			T9	7		T41	6		T46	9
auto[1]	values[0]	values[6]	273	1			T41	7		T31	10		T146	12
auto[1]	values[0]	values[7]	57	1			T274	8		T152	7		T275	4
auto[1]	values[1]	values[0]	252	1			T44	15		T21	99		T123	13
auto[1]	values[1]	values[1]	89	1			T65	9		T226	39		T124	5
auto[1]	values[1]	values[2]	118	1			T122	14		T276	18		T49	6
auto[1]	values[1]	values[3]	109	1			T42	8		T216	8		T207	7
auto[1]	values[1]	values[4]	121	1			T19	4		T166	6		T222	7
auto[1]	values[1]	values[5]	272	1			T42	11		T52	6		T65	7
auto[1]	values[1]	values[6]	147	1			T44	20		T45	28		T46	10
auto[1]	values[1]	values[7]	193	1			T46	11		T200	54		T247	3
auto[1]	values[2]	values[0]	275	1			T9	9		T41	15		T186	7
auto[1]	values[2]	values[1]	110	1			T46	15		T19	9		T222	6
auto[1]	values[2]	values[2]	120	1			T42	15		T182	7		T216	7
auto[1]	values[2]	values[3]	133	1			T210	3		T201	7		T124	5
auto[1]	values[2]	values[4]	133	1			T19	10		T182	77		T208	10
auto[1]	values[2]	values[5]	128	1			T42	66		T49	4		T207	8
auto[1]	values[2]	values[6]	100	1			T47	26		T222	7		T36	7
auto[1]	values[2]	values[7]	169	1			T41	15		T52	7		T123	15
auto[1]	values[3]	values[0]	146	1			T43	11		T46	4		T19	8
auto[1]	values[3]	values[1]	37	1			T166	4		T199	5		T221	3
auto[1]	values[3]	values[2]	30	1			T41	4		T48	12		T277	7
auto[1]	values[3]	values[3]	202	1			T166	10		T186	11		T207	7
auto[1]	values[3]	values[4]	163	1			T46	17		T49	9		T52	11
auto[1]	values[3]	values[5]	51	1			T122	10		T125	10		T278	10
auto[1]	values[3]	values[6]	108	1			T21	8		T123	3		T279	15
auto[1]	values[3]	values[7]	214	1			T8	60		T45	8		T49	12
auto[1]	values[4]	values[0]	321	1			T41	31		T45	10		T21	11
auto[1]	values[4]	values[1]	174	1			T42	9		T52	30		T201	61
auto[1]	values[4]	values[2]	135	1			T188	17		T185	9		T201	52
auto[1]	values[4]	values[3]	50	1			T9	5		T31	17		T186	5
auto[1]	values[4]	values[4]	121	1			T8	19		T42	5		T46	8
auto[1]	values[4]	values[5]	144	1			T42	23		T31	6		T149	3
auto[1]	values[4]	values[6]	196	1			T41	42		T45	16		T21	12
auto[1]	values[4]	values[7]	150	1			T46	7		T122	15		T230	77
auto[1]	values[5]	values[0]	126	1			T21	8		T280	12		T216	7
auto[1]	values[5]	values[1]	115	1			T8	8		T15	8		T41	19
auto[1]	values[5]	values[2]	62	1			T19	8		T262	25		T263	8
auto[1]	values[5]	values[3]	123	1			T19	12		T21	7		T201	8
auto[1]	values[5]	values[4]	167	1			T42	11		T46	13		T21	80
auto[1]	values[5]	values[5]	287	1			T44	7		T21	18		T281	18
auto[1]	values[5]	values[6]	121	1			T9	10		T44	9		T46	7
auto[1]	values[5]	values[7]	230	1			T3	22		T42	11		T122	10
auto[1]	values[6]	values[0]	119	1			T44	6		T182	14		T36	7
auto[1]	values[6]	values[1]	180	1			T21	22		T31	3		T230	9
auto[1]	values[6]	values[2]	390	1			T9	12		T41	5		T65	5
auto[1]	values[6]	values[3]	101	1			T24	8		T21	8		T199	7
auto[1]	values[6]	values[4]	175	1			T49	6		T21	12		T182	17
auto[1]	values[6]	values[5]	212	1			T42	12		T46	63		T52	14
auto[1]	values[6]	values[6]	94	1			T42	11		T182	9		T279	11
auto[1]	values[6]	values[7]	215	1			T21	12		T201	10		T124	116
auto[1]	values[7]	values[0]	136	1			T266	12		T123	6		T192	9
auto[1]	values[7]	values[1]	88	1			T44	8		T238	26		T216	5
auto[1]	values[7]	values[2]	119	1			T42	12		T46	6		T21	5
auto[1]	values[7]	values[3]	122	1			T282	18		T283	10		T49	12
auto[1]	values[7]	values[4]	104	1			T41	19		T19	7		T279	7
auto[1]	values[7]	values[5]	110	1			T9	19		T222	10		T146	8
auto[1]	values[7]	values[6]	131	1			T41	8		T182	10		T188	11
auto[1]	values[7]	values[7]	141	1			T9	10		T247	31		T124	13