Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2480525	1			T2	32711		T3	1336		T4	2275
all_pins[1]	2480525	1			T2	32711		T3	1336		T4	2275
all_pins[2]	2480525	1			T2	32711		T3	1336		T4	2275
all_pins[3]	2480525	1			T2	32711		T3	1336		T4	2275
all_pins[4]	2480525	1			T2	32711		T3	1336		T4	2275
all_pins[5]	2480525	1			T2	32711		T3	1336		T4	2275
all_pins[6]	2480525	1			T2	32711		T3	1336		T4	2275
all_pins[7]	2480525	1			T2	32711		T3	1336		T4	2275

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19787606	1			T2	261688		T3	10688		T4	18200
values[0x1]	56594	1			T17	15		T19	12		T20	32
transitions[0x0=>0x1]	55949	1			T17	15		T19	9		T20	23
transitions[0x1=>0x0]	55961	1			T17	15		T19	9		T20	23

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2480317	1			T2	32711		T3	1336		T4	2275
all_pins[0]	values[0x1]	208	1			T17	3		T19	1		T20	7
all_pins[0]	transitions[0x0=>0x1]	146	1			T17	3		T20	6		T21	2
all_pins[0]	transitions[0x1=>0x0]	218	1			T17	2		T20	4		T21	2
all_pins[1]	values[0x0]	2480245	1			T2	32711		T3	1336		T4	2275
all_pins[1]	values[0x1]	280	1			T17	2		T19	1		T20	5
all_pins[1]	transitions[0x0=>0x1]	236	1			T17	2		T19	1		T20	5
all_pins[1]	transitions[0x1=>0x0]	148	1			T17	3		T20	6		T21	3
all_pins[2]	values[0x0]	2480333	1			T2	32711		T3	1336		T4	2275
all_pins[2]	values[0x1]	192	1			T17	3		T20	6		T21	3
all_pins[2]	transitions[0x0=>0x1]	142	1			T17	3		T20	3		T21	3
all_pins[2]	transitions[0x1=>0x0]	128	1			T17	1		T20	2		T21	1
all_pins[3]	values[0x0]	2480347	1			T2	32711		T3	1336		T4	2275
all_pins[3]	values[0x1]	178	1			T17	1		T20	5		T21	1
all_pins[3]	transitions[0x0=>0x1]	140	1			T17	1		T20	4		T21	1
all_pins[3]	transitions[0x1=>0x0]	137	1			T17	4		T19	1		T20	3
all_pins[4]	values[0x0]	2480350	1			T2	32711		T3	1336		T4	2275
all_pins[4]	values[0x1]	175	1			T17	4		T19	1		T20	4
all_pins[4]	transitions[0x0=>0x1]	144	1			T17	4		T19	1		T20	2
all_pins[4]	transitions[0x1=>0x0]	412	1			T17	2		T19	4		T20	1
all_pins[5]	values[0x0]	2480082	1			T2	32711		T3	1336		T4	2275
all_pins[5]	values[0x1]	443	1			T17	2		T19	4		T20	3
all_pins[5]	transitions[0x0=>0x1]	127	1			T17	2		T19	3		T20	3
all_pins[5]	transitions[0x1=>0x0]	54598	1			T19	1		T20	1		T21	2
all_pins[6]	values[0x0]	2425611	1			T2	32711		T3	1336		T4	2275
all_pins[6]	values[0x1]	54914	1			T19	2		T20	1		T21	2
all_pins[6]	transitions[0x0=>0x1]	54862	1			T19	1		T31	44299		T162	1
all_pins[6]	transitions[0x1=>0x0]	152	1			T19	2		T21	3		T31	3
all_pins[7]	values[0x0]	2480321	1			T2	32711		T3	1336		T4	2275
all_pins[7]	values[0x1]	204	1			T19	3		T20	1		T21	5
all_pins[7]	transitions[0x0=>0x1]	152	1			T19	3		T21	2		T31	3
all_pins[7]	transitions[0x1=>0x0]	168	1			T17	3		T19	1		T20	6