Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	303	1			T8	1		T9	1		T41	6
auto[ReadAddrCrossIntoMailbox]	216	1			T8	6		T9	2		T41	3
auto[ReadAddrCrossOutOfMailbox]	226	1			T8	2		T41	7		T43	2
auto[ReadAddrCrossAllMailbox]	181	1			T8	1		T9	1		T41	3
auto[ReadAddrOutsideMailbox]	2694	1			T3	1		T8	7		T9	37

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1830

1

T3

1

T8

12

T9

26

auto[1]

1790

1

T8

5

T9

15

T14

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	587	1			T8	3		T9	5		T15	2
read_ops[0x0b]	610	1			T8	2		T9	9		T41	8
read_ops[0x3b]	592	1			T8	2		T9	9		T41	14
read_ops[0x6b]	652	1			T8	2		T9	7		T41	11
read_ops[0xbb]	576	1			T8	3		T9	3		T14	2
read_ops[0xeb]	603	1			T3	1		T8	5		T9	8

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T9	1		T122	1		T160	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T41	1		T42	2		T122	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T8	1		T9	1		T41	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T45	1		T19	2		T166	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	13	1			T44	1		T230	1		T192	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T41	1		T45	1		T52	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T46	1		T49	1		T188	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T42	1		T230	2		T124	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	232	1			T8	2		T9	3		T15	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	208	1			T15	1		T41	7		T84	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T41	2		T44	1		T122	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	15	1			T19	2		T222	1		T31	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T8	2		T46	2		T156	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T42	2		T156	1		T122	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T42	1		T122	1		T49	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T42	1		T19	2		T49	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T45	1		T156	1		T31	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T41	1		T156	1		T19	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	230	1			T9	5		T41	2		T33	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	212	1			T9	4		T41	3		T33	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T19	1		T166	1		T222	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T19	1		T21	1		T200	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T9	1		T42	2		T21	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T44	1		T122	1		T52	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T19	1		T123	1		T284	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T8	1		T19	1		T52	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T41	1		T19	1		T222	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T122	1		T19	1		T201	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	213	1			T9	5		T41	6		T43	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	216	1			T8	1		T9	3		T41	7
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T8	1		T41	2		T42	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T52	1		T182	1		T285	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	12	1			T42	2		T46	1		T65	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T8	1		T42	1		T46	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T41	2		T43	1		T42	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T46	1		T21	1		T182	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T42	2		T19	2		T49	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T21	1		T182	1		T286	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	224	1			T9	3		T41	2		T42	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T9	4		T41	5		T42	7
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	19	1			T43	1		T46	1		T122	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T19	2		T182	1		T123	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T42	2		T21	1		T65	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T122	1		T52	2		T21	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T122	1		T49	1		T36	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T44	1		T19	1		T36	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T9	1		T42	1		T287	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T8	1		T287	1		T182	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	234	1			T8	1		T9	1		T14	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	192	1			T8	1		T9	1		T14	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T43	1		T45	1		T19	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T41	1		T21	1		T222	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T8	2		T42	1		T44	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T41	1		T43	1		T46	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T8	1		T41	2		T43	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	12	1			T41	2		T52	1		T146	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T41	1		T45	1		T52	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T43	1		T288	1		T213	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	220	1			T3	1		T8	2		T9	5
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	248	1			T9	3		T41	6		T33	1