Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2334	1			T3	36		T9	20		T41	20
values[1]	3030	1			T9	71		T14	2		T41	20
values[2]	2856	1			T9	26		T41	75		T24	8
values[3]	3158	1			T8	20		T9	28		T42	129
values[4]	3036	1			T6	8		T9	43		T41	83
values[5]	2750	1			T9	53		T41	20		T138	2
values[6]	3139	1			T8	20		T41	67		T258	8
values[7]	2405	1			T8	105		T13	28		T15	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2962	1			T8	64		T9	26		T41	165
values[1]	3170	1			T3	36		T6	8		T42	69
values[2]	2926	1			T8	20		T9	40		T41	87
values[3]	2869	1			T9	26		T33	18		T35	2
values[4]	2907	1			T8	41		T9	79		T14	2
values[5]	2728	1			T9	22		T13	28		T41	20
values[6]	2823	1			T8	20		T9	20		T41	95
values[7]	2323	1			T9	28		T15	8		T41	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22313

1

T3

34

T6

8

T8

144

auto[1]

395

1

T3

2

T8

1

T9

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	391	1			T251	16		T49	25		T245	6
auto[0]	values[0]	values[1]	496	1			T3	34		T44	85		T19	20
auto[0]	values[0]	values[2]	201	1			T21	20		T213	26		T124	24
auto[0]	values[0]	values[3]	248	1			T139	6		T46	24		T122	20
auto[0]	values[0]	values[4]	353	1			T19	29		T21	32		T182	22
auto[0]	values[0]	values[5]	201	1			T43	20		T216	61		T268	16
auto[0]	values[0]	values[6]	233	1			T9	20		T41	20		T239	14
auto[0]	values[0]	values[7]	172	1			T42	25		T31	38		T289	10
auto[0]	values[1]	values[0]	261	1			T265	2		T49	20		T21	20
auto[0]	values[1]	values[1]	359	1			T165	8		T49	20		T290	14
auto[0]	values[1]	values[2]	411	1			T9	20		T19	22		T21	20
auto[0]	values[1]	values[3]	524	1			T9	26		T33	18		T35	2
auto[0]	values[1]	values[4]	273	1			T9	24		T14	2		T42	58
auto[0]	values[1]	values[5]	413	1			T122	20		T21	17		T254	2
auto[0]	values[1]	values[6]	387	1			T50	6		T203	16		T21	104
auto[0]	values[1]	values[7]	342	1			T41	19		T46	20		T49	19
auto[0]	values[2]	values[0]	319	1			T9	26		T79	6		T46	19
auto[0]	values[2]	values[1]	438	1			T46	29		T47	24		T36	17
auto[0]	values[2]	values[2]	276	1			T41	20		T182	23		T291	8
auto[0]	values[2]	values[3]	290	1			T46	19		T292	2		T293	10
auto[0]	values[2]	values[4]	254	1			T287	2		T19	46		T255	6
auto[0]	values[2]	values[5]	465	1			T42	31		T44	39		T46	29
auto[0]	values[2]	values[6]	356	1			T41	54		T46	20		T187	16
auto[0]	values[2]	values[7]	404	1			T24	8		T52	27		T280	12
auto[0]	values[3]	values[0]	242	1			T63	2		T222	21		T36	27
auto[0]	values[3]	values[1]	397	1			T42	69		T166	43		T222	20
auto[0]	values[3]	values[2]	584	1			T42	20		T19	62		T52	20
auto[0]	values[3]	values[3]	257	1			T46	31		T21	27		T146	70
auto[0]	values[3]	values[4]	556	1			T8	20		T42	20		T188	20
auto[0]	values[3]	values[5]	355	1			T42	20		T45	20		T267	12
auto[0]	values[3]	values[6]	460	1			T182	22		T146	24		T149	21
auto[0]	values[3]	values[7]	262	1			T9	28		T269	2		T19	24
auto[0]	values[4]	values[0]	461	1			T41	63		T46	19		T52	19
auto[0]	values[4]	values[1]	337	1			T6	8		T45	25		T294	6
auto[0]	values[4]	values[2]	224	1			T41	20		T80	8		T31	20
auto[0]	values[4]	values[3]	578	1			T42	74		T44	20		T226	52
auto[0]	values[4]	values[4]	409	1			T9	21		T52	20		T222	21
auto[0]	values[4]	values[5]	404	1			T9	22		T84	8		T182	40
auto[0]	values[4]	values[6]	347	1			T276	18		T21	31		T182	25
auto[0]	values[4]	values[7]	226	1			T199	19		T188	29		T36	27
auto[0]	values[5]	values[0]	459	1			T19	40		T49	20		T182	35
auto[0]	values[5]	values[1]	206	1			T46	68		T182	30		T260	2
auto[0]	values[5]	values[2]	443	1			T9	19		T264	2		T46	20
auto[0]	values[5]	values[3]	378	1			T295	2		T246	10		T296	12
auto[0]	values[5]	values[4]	405	1			T9	33		T157	8		T185	78
auto[0]	values[5]	values[5]	229	1			T41	20		T65	20		T216	20
auto[0]	values[5]	values[6]	357	1			T138	2		T252	2		T31	23
auto[0]	values[5]	values[7]	224	1			T42	20		T44	19		T122	24
auto[0]	values[6]	values[0]	336	1			T41	20		T44	37		T52	18
auto[0]	values[6]	values[1]	585	1			T122	22		T19	40		T282	18
auto[0]	values[6]	values[2]	344	1			T41	45		T21	26		T266	47
auto[0]	values[6]	values[3]	369	1			T44	81		T156	6		T248	20
auto[0]	values[6]	values[4]	377	1			T42	57		T65	24		T253	2
auto[0]	values[6]	values[5]	313	1			T258	8		T46	20		T122	42
auto[0]	values[6]	values[6]	393	1			T8	19		T122	20		T271	14
auto[0]	values[6]	values[7]	361	1			T45	18		T49	22		T52	20
auto[0]	values[7]	values[0]	450	1			T8	64		T41	81		T155	12
auto[0]	values[7]	values[1]	301	1			T44	40		T45	24		T46	55
auto[0]	values[7]	values[2]	397	1			T8	20		T178	6		T297	47
auto[0]	values[7]	values[3]	169	1			T261	6		T200	20		T298	12
auto[0]	values[7]	values[4]	218	1			T8	21		T48	10		T19	19
auto[0]	values[7]	values[5]	301	1			T13	28		T299	83		T36	20
auto[0]	values[7]	values[6]	235	1			T41	20		T52	20		T270	12
auto[0]	values[7]	values[7]	297	1			T15	8		T21	24		T31	20
auto[1]	values[0]	values[0]	10	1			T300	6		T301	2		T302	2
auto[1]	values[0]	values[1]	9	1			T3	2		T44	1		T182	3
auto[1]	values[0]	values[2]	5	1			T213	2		T124	1		T273	1
auto[1]	values[0]	values[3]	2	1			T303	2		-	-		-	-
auto[1]	values[0]	values[4]	7	1			T21	1		T149	3		T205	2
auto[1]	values[0]	values[5]	2	1			T216	2		-	-		-	-
auto[1]	values[0]	values[6]	2	1			T201	2		-	-		-	-
auto[1]	values[0]	values[7]	2	1			T31	2		-	-		-	-
auto[1]	values[1]	values[0]	2	1			T304	2		-	-		-	-
auto[1]	values[1]	values[1]	11	1			T266	1		T31	3		T274	2
auto[1]	values[1]	values[2]	5	1			T19	1		T207	2		T242	1
auto[1]	values[1]	values[3]	11	1			T182	2		T305	1		T306	4
auto[1]	values[1]	values[4]	9	1			T9	1		T42	2		T186	2
auto[1]	values[1]	values[5]	13	1			T21	3		T146	2		T124	2
auto[1]	values[1]	values[6]	3	1			T279	2		T206	1		-	-
auto[1]	values[1]	values[7]	6	1			T41	1		T49	1		T166	1
auto[1]	values[2]	values[0]	4	1			T46	1		T201	2		T208	1
auto[1]	values[2]	values[1]	13	1			T46	1		T47	2		T36	4
auto[1]	values[2]	values[2]	3	1			T262	2		T307	1		-	-
auto[1]	values[2]	values[3]	8	1			T46	1		T188	1		T123	1
auto[1]	values[2]	values[4]	6	1			T19	2		T301	4		-	-
auto[1]	values[2]	values[5]	13	1			T44	1		T123	2		T185	3
auto[1]	values[2]	values[6]	4	1			T41	1		T230	2		T303	1
auto[1]	values[2]	values[7]	3	1			T52	2		T152	1		-	-
auto[1]	values[3]	values[0]	6	1			T36	1		T286	4		T277	1
auto[1]	values[3]	values[1]	1	1			T221	1		-	-		-	-
auto[1]	values[3]	values[2]	4	1			T19	1		T21	1		T308	1
auto[1]	values[3]	values[3]	6	1			T46	1		T146	2		T152	1
auto[1]	values[3]	values[4]	9	1			T213	1		T221	3		T150	3
auto[1]	values[3]	values[5]	1	1			T305	1		-	-		-	-
auto[1]	values[3]	values[6]	12	1			T182	1		T146	3		T262	2
auto[1]	values[3]	values[7]	6	1			T19	1		T238	2		T213	1
auto[1]	values[4]	values[0]	7	1			T46	1		T52	1		T213	1
auto[1]	values[4]	values[1]	3	1			T45	1		T21	1		T205	1
auto[1]	values[4]	values[2]	3	1			T247	3		-	-		-	-
auto[1]	values[4]	values[3]	7	1			T226	2		T208	1		T193	2
auto[1]	values[4]	values[4]	10	1			T164	2		T217	1		T286	5
auto[1]	values[4]	values[5]	4	1			T200	3		T124	1		-	-
auto[1]	values[4]	values[6]	12	1			T186	3		T213	1		T124	1
auto[1]	values[4]	values[7]	4	1			T199	1		T188	2		T36	1
auto[1]	values[5]	values[0]	4	1			T236	1		T242	1		T309	2
auto[1]	values[5]	values[1]	3	1			T46	1		T310	2		-	-
auto[1]	values[5]	values[2]	13	1			T9	1		T52	4		T21	1
auto[1]	values[5]	values[3]	12	1			T123	5		T186	3		T247	2
auto[1]	values[5]	values[4]	2	1			T208	1		T302	1		-	-
auto[1]	values[5]	values[5]	1	1			T311	1		-	-		-	-
auto[1]	values[5]	values[6]	11	1			T36	4		T312	3		T149	4
auto[1]	values[5]	values[7]	3	1			T44	1		T207	1		T205	1
auto[1]	values[6]	values[0]	7	1			T52	2		T124	1		T263	1
auto[1]	values[6]	values[1]	8	1			T19	1		T207	2		T124	1
auto[1]	values[6]	values[2]	11	1			T41	2		T266	1		T188	1
auto[1]	values[6]	values[3]	7	1			T44	1		T221	4		T305	2
auto[1]	values[6]	values[4]	8	1			T65	2		T123	3		T213	1
auto[1]	values[6]	values[5]	7	1			T122	2		T192	2		T313	1
auto[1]	values[6]	values[6]	9	1			T8	1		T210	1		T146	1
auto[1]	values[6]	values[7]	4	1			T45	2		T49	1		T21	1
auto[1]	values[7]	values[0]	3	1			T41	1		T217	1		T314	1
auto[1]	values[7]	values[1]	3	1			T46	1		T149	1		T315	1
auto[1]	values[7]	values[2]	2	1			T152	1		T303	1		-	-
auto[1]	values[7]	values[3]	3	1			T200	1		T303	1		T212	1
auto[1]	values[7]	values[4]	11	1			T48	2		T19	1		T150	4
auto[1]	values[7]	values[5]	6	1			T149	1		T310	2		T316	3
auto[1]	values[7]	values[6]	2	1			T317	2		-	-		-	-
auto[1]	values[7]	values[7]	7	1			T152	1		T262	3		T318	3