Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1905

1

T2

14

T3

10

T4

5

auto[1]

1853

1

T2

6

T3

8

T4

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2046

1

T2

18

T3

12

T4

5

auto[1]

1712

1

T2

2

T3

6

T4

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2977

1

T2

11

T3

11

T4

6

auto[1]

781

1

T2

9

T3

7

T4

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	773	1			T2	1		T3	2		T4	2
valid[1]	770	1			T2	4		T3	2		T4	1
valid[2]	723	1			T2	4		T3	5		T4	1
valid[3]	748	1			T2	4		T3	6		T4	2
valid[4]	744	1			T2	7		T3	3		T4	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	131	1			T10	1		T16	1		T43	1
auto[0]	auto[0]	valid[0]	auto[1]	168	1			T4	1		T29	6		T16	1
auto[0]	auto[0]	valid[1]	auto[0]	121	1			T2	1		T9	1		T43	2
auto[0]	auto[0]	valid[1]	auto[1]	191	1			T29	7		T16	1		T26	1
auto[0]	auto[0]	valid[2]	auto[0]	139	1			T2	1		T9	2		T16	2
auto[0]	auto[0]	valid[2]	auto[1]	156	1			T2	1		T3	3		T29	4
auto[0]	auto[0]	valid[3]	auto[0]	139	1			T2	1		T3	2		T4	1
auto[0]	auto[0]	valid[3]	auto[1]	175	1			T3	2		T29	4		T16	1
auto[0]	auto[0]	valid[4]	auto[0]	124	1			T2	2		T8	1		T9	2
auto[0]	auto[0]	valid[4]	auto[1]	174	1			T2	1		T4	1		T29	4
auto[0]	auto[1]	valid[0]	auto[0]	122	1			T9	4		T10	2		T16	1
auto[0]	auto[1]	valid[0]	auto[1]	188	1			T29	6		T77	10		T46	1
auto[0]	auto[1]	valid[1]	auto[0]	138	1			T2	1		T3	1		T8	1
auto[0]	auto[1]	valid[1]	auto[1]	158	1			T4	1		T29	4		T16	1
auto[0]	auto[1]	valid[2]	auto[0]	113	1			T3	1		T10	1		T16	1
auto[0]	auto[1]	valid[2]	auto[1]	159	1			T29	3		T16	1		T77	3
auto[0]	auto[1]	valid[3]	auto[0]	124	1			T2	2		T4	1		T9	1
auto[0]	auto[1]	valid[3]	auto[1]	168	1			T29	2		T16	1		T77	3
auto[0]	auto[1]	valid[4]	auto[0]	114	1			T2	1		T3	1		T9	2
auto[0]	auto[1]	valid[4]	auto[1]	175	1			T3	1		T4	1		T8	1
auto[1]	auto[0]	valid[0]	auto[0]	78	1			T2	1		T3	1		T4	1
auto[1]	auto[0]	valid[1]	auto[0]	81	1			T2	2		T3	1		T10	1
auto[1]	auto[0]	valid[2]	auto[0]	82	1			T2	2		T4	1		T34	1
auto[1]	auto[0]	valid[3]	auto[0]	76	1			T2	1		T3	1		T9	1
auto[1]	auto[0]	valid[4]	auto[0]	70	1			T2	1		T8	1		T9	1
auto[1]	auto[1]	valid[0]	auto[0]	86	1			T3	1		T8	2		T9	1
auto[1]	auto[1]	valid[1]	auto[0]	81	1			T43	1		T42	1		T45	2
auto[1]	auto[1]	valid[2]	auto[0]	74	1			T3	1		T9	1		T10	1
auto[1]	auto[1]	valid[3]	auto[0]	66	1			T3	1		T10	1		T45	1
auto[1]	auto[1]	valid[4]	auto[0]	87	1			T2	2		T3	1		T4	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal